[llvm] 2915889 - [ScheduleDAGInstrs] Call adjustSchedDependency in more cases

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-10-22T20:03:29+01:00
New Revision: 2915889d74b124d3105d1e7583fbfb1cf1bad10d

URL: https://github.com/llvm/llvm-project/commit/2915889d74b124d3105d1e7583fbfb1cf1bad10d
DIFF: https://github.com/llvm/llvm-project/commit/2915889d74b124d3105d1e7583fbfb1cf1bad10d.diff

LOG: [ScheduleDAGInstrs] Call adjustSchedDependency in more cases

This removes a condition and the corresponding FIXME comment, because
the Hexagon assertion it refers to has apparently been fixed, probably
by D76134.

NFCI. This just gives targets the opportunity to adjust latencies that
were set to 0 by the generic code because they involve "implicit pseudo"
operands.

Differential Revision: https://reviews.llvm.org/D112306

Added: 
    

Modified: 
    llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index daff3af3bc3c..504341e4c96d 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -271,15 +271,10 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
       if (!ImplicitPseudoDef && !ImplicitPseudoUse) {
         Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
                                                         RegUse, UseOp));
-        ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
       } else {
         Dep.setLatency(0);
-        // FIXME: We could always let target to adjustSchedDependency(), and
-        // remove this condition, but that currently asserts in Hexagon BE.
-        if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle()))
-          ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
       }
-
+      ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
       UseSU->addPred(Dep);
     }
   }