[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added a comment.

In D109300#3076671 <https://reviews.llvm.org/D109300#3076671>, @arsenm wrote:

> In D109300#3073129 <https://reviews.llvm.org/D109300#3073129>, @cdevadas wrote:
>
>> Should we restrain the MIOperand regclasses based on the incoming regbank when the corresponding RC in the instruction definition is its superclass?
>
> Yes, I'm surprised this doesn't happen already. Just the instruction definition can be ambiguous

Posted D112323 <https://reviews.llvm.org/D112323>.


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