[llvm] 0766aef - [LegalizeTypes][RISCV][PowerPC] Expand CTLZ/CTTZ/CTPOP instead of promoting if they'll be expanded later.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 22 09:10:41 PDT 2021
Author: Craig Topper
Date: 2021-10-22T09:10:01-07:00
New Revision: 0766aef3f32d5d642d6436140b36689b1f2b5adf
URL: https://github.com/llvm/llvm-project/commit/0766aef3f32d5d642d6436140b36689b1f2b5adf
DIFF: https://github.com/llvm/llvm-project/commit/0766aef3f32d5d642d6436140b36689b1f2b5adf.diff
LOG: [LegalizeTypes][RISCV][PowerPC] Expand CTLZ/CTTZ/CTPOP instead of promoting if they'll be expanded later.
Expanding these requires multiple constants. If we promote during type
legalization when they'll end up getting expanded in LegalizeDAG, we'll
use larger constants. These constants may be harder to materialize.
For example, 64-bit constants on 64-bit RISCV are very expensive.
This is similar to what has already been done to BSWAP and BITREVERSE.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D112268
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/test/CodeGen/PowerPC/popcnt-zext.ll
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
llvm/test/CodeGen/RISCV/rv64zbb.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 728d3dbe10820..61ea98fd85e18 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -579,11 +579,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
+ EVT OVT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
+ SDLoc dl(N);
+
+ // If the larger CTLZ isn't supported by the target, try to expand now.
+ // If we expand later we'll end up with more operations since we lost the
+ // original type.
+ if (!OVT.isVector() &&
+ !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ, NVT) &&
+ !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ_ZERO_UNDEF, NVT)) {
+ if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
+ Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
+ return Result;
+ }
+ }
+
// Zero extend to the promoted type and do the count there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
- SDLoc dl(N);
- EVT OVT = N->getValueType(0);
- EVT NVT = Op.getValueType();
Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
// Subtract off the extra leading bits in the bigger type.
return DAG.getNode(
@@ -593,6 +606,22 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
+ EVT OVT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
+
+ // If the larger CTPOP isn't supported by the target, try to expand now.
+ // If we expand later we'll end up with more operations since we lost the
+ // original type.
+ // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
+ // TargetLowering.
+ if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() &&
+ !TLI.isOperationLegalOrCustomOrPromote(ISD::CTPOP, NVT)) {
+ if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
+ Result = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Result);
+ return Result;
+ }
+ }
+
// Zero extend to the promoted type and do the count or parity there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
@@ -603,6 +632,19 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
EVT OVT = N->getValueType(0);
EVT NVT = Op.getValueType();
SDLoc dl(N);
+
+ // If the larger CTTZ isn't supported by the target, try to expand now.
+ // If we expand later we'll end up with more operations since we lost the
+ // original type.
+ if (!OVT.isVector() &&
+ !TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ, NVT) &&
+ !TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ_ZERO_UNDEF, NVT)) {
+ if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
+ Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
+ return Result;
+ }
+ }
+
if (N->getOpcode() == ISD::CTTZ) {
// The count is the same in the promoted type except if the original
// value was zero. This can be handled by setting the bit just off
diff --git a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
index fdb99f4aba0bb..21f902f510e97 100644
--- a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
+++ b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
@@ -13,27 +13,19 @@ define i16 @zpop_i8_i16(i8 %x) {
;
; SLOW-LABEL: zpop_i8_i16:
; SLOW: # %bb.0:
-; SLOW-NEXT: clrlwi 5, 3, 24
+; SLOW-NEXT: clrlwi 4, 3, 24
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
-; SLOW-NEXT: lis 4, 13107
-; SLOW-NEXT: sub 3, 5, 3
-; SLOW-NEXT: ori 4, 4, 13107
-; SLOW-NEXT: rotlwi 5, 3, 30
-; SLOW-NEXT: and 3, 3, 4
-; SLOW-NEXT: andis. 4, 5, 13107
-; SLOW-NEXT: andi. 5, 5, 13107
-; SLOW-NEXT: or 4, 5, 4
-; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 5, 3855
+; SLOW-NEXT: sub 3, 4, 3
+; SLOW-NEXT: andi. 4, 3, 13107
+; SLOW-NEXT: rotlwi 3, 3, 30
+; SLOW-NEXT: andi. 3, 3, 13107
+; SLOW-NEXT: add 3, 4, 3
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 4, 257
-; SLOW-NEXT: ori 5, 5, 3855
-; SLOW-NEXT: and 3, 3, 5
-; SLOW-NEXT: ori 4, 4, 257
-; SLOW-NEXT: mullw 3, 3, 4
-; SLOW-NEXT: srwi 3, 3, 24
+; SLOW-NEXT: andi. 3, 3, 3855
+; SLOW-NEXT: mulli 3, 3, 257
+; SLOW-NEXT: rlwinm 3, 3, 24, 24, 31
; SLOW-NEXT: blr
%z = zext i8 %x to i16
%pop = tail call i16 @llvm.ctpop.i16(i16 %z)
@@ -49,27 +41,16 @@ define i16 @popz_i8_i16(i8 %x) {
;
; SLOW-LABEL: popz_i8_i16:
; SLOW: # %bb.0:
-; SLOW-NEXT: clrlwi 5, 3, 24
-; SLOW-NEXT: rotlwi 3, 3, 31
-; SLOW-NEXT: andi. 3, 3, 85
-; SLOW-NEXT: lis 4, 13107
-; SLOW-NEXT: sub 3, 5, 3
-; SLOW-NEXT: ori 4, 4, 13107
-; SLOW-NEXT: rotlwi 5, 3, 30
-; SLOW-NEXT: and 3, 3, 4
-; SLOW-NEXT: andis. 4, 5, 13107
-; SLOW-NEXT: andi. 5, 5, 13107
-; SLOW-NEXT: or 4, 5, 4
+; SLOW-NEXT: rotlwi 4, 3, 31
+; SLOW-NEXT: andi. 4, 4, 85
+; SLOW-NEXT: sub 3, 3, 4
+; SLOW-NEXT: rlwinm 4, 3, 30, 30, 31
+; SLOW-NEXT: rlwimi 4, 3, 30, 26, 27
+; SLOW-NEXT: andi. 3, 3, 51
; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 5, 3855
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 4, 257
-; SLOW-NEXT: ori 5, 5, 3855
-; SLOW-NEXT: and 3, 3, 5
-; SLOW-NEXT: ori 4, 4, 257
-; SLOW-NEXT: mullw 3, 3, 4
-; SLOW-NEXT: rlwinm 3, 3, 8, 24, 31
+; SLOW-NEXT: clrlwi 3, 3, 28
; SLOW-NEXT: blr
%pop = tail call i8 @llvm.ctpop.i8(i8 %x)
%z = zext i8 %pop to i16
@@ -121,27 +102,16 @@ define i32 @popz_i8_32(i8 %x) {
;
; SLOW-LABEL: popz_i8_32:
; SLOW: # %bb.0:
-; SLOW-NEXT: clrlwi 5, 3, 24
-; SLOW-NEXT: rotlwi 3, 3, 31
-; SLOW-NEXT: andi. 3, 3, 85
-; SLOW-NEXT: lis 4, 13107
-; SLOW-NEXT: sub 3, 5, 3
-; SLOW-NEXT: ori 4, 4, 13107
-; SLOW-NEXT: rotlwi 5, 3, 30
-; SLOW-NEXT: and 3, 3, 4
-; SLOW-NEXT: andis. 4, 5, 13107
-; SLOW-NEXT: andi. 5, 5, 13107
-; SLOW-NEXT: or 4, 5, 4
+; SLOW-NEXT: rotlwi 4, 3, 31
+; SLOW-NEXT: andi. 4, 4, 85
+; SLOW-NEXT: sub 3, 3, 4
+; SLOW-NEXT: rlwinm 4, 3, 30, 30, 31
+; SLOW-NEXT: rlwimi 4, 3, 30, 26, 27
+; SLOW-NEXT: andi. 3, 3, 51
; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 5, 3855
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 4, 257
-; SLOW-NEXT: ori 5, 5, 3855
-; SLOW-NEXT: and 3, 3, 5
-; SLOW-NEXT: ori 4, 4, 257
-; SLOW-NEXT: mullw 3, 3, 4
-; SLOW-NEXT: rlwinm 3, 3, 8, 24, 31
+; SLOW-NEXT: clrlwi 3, 3, 28
; SLOW-NEXT: blr
%pop = tail call i8 @llvm.ctpop.i8(i8 %x)
%z = zext i8 %pop to i32
@@ -193,27 +163,18 @@ define i32 @popz_i16_32(i16 %x) {
;
; SLOW-LABEL: popz_i16_32:
; SLOW: # %bb.0:
-; SLOW-NEXT: clrlwi 5, 3, 16
-; SLOW-NEXT: rotlwi 3, 3, 31
-; SLOW-NEXT: andi. 3, 3, 21845
-; SLOW-NEXT: lis 4, 13107
-; SLOW-NEXT: sub 3, 5, 3
-; SLOW-NEXT: ori 4, 4, 13107
-; SLOW-NEXT: rotlwi 5, 3, 30
-; SLOW-NEXT: and 3, 3, 4
-; SLOW-NEXT: andis. 4, 5, 13107
-; SLOW-NEXT: andi. 5, 5, 13107
-; SLOW-NEXT: or 4, 5, 4
-; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 5, 3855
+; SLOW-NEXT: rotlwi 4, 3, 31
+; SLOW-NEXT: andi. 4, 4, 21845
+; SLOW-NEXT: sub 3, 3, 4
+; SLOW-NEXT: andi. 4, 3, 13107
+; SLOW-NEXT: rotlwi 3, 3, 30
+; SLOW-NEXT: andi. 3, 3, 13107
+; SLOW-NEXT: add 3, 4, 3
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 4, 257
-; SLOW-NEXT: ori 5, 5, 3855
-; SLOW-NEXT: and 3, 3, 5
-; SLOW-NEXT: ori 4, 4, 257
-; SLOW-NEXT: mullw 3, 3, 4
-; SLOW-NEXT: rlwinm 3, 3, 8, 24, 31
+; SLOW-NEXT: andi. 3, 3, 3855
+; SLOW-NEXT: mulli 3, 3, 257
+; SLOW-NEXT: rlwinm 3, 3, 24, 24, 31
; SLOW-NEXT: blr
%pop = tail call i16 @llvm.ctpop.i16(i16 %x)
%z = zext i16 %pop to i32
@@ -306,27 +267,18 @@ define i64 @popa_i16_i64(i16 %x) {
;
; SLOW-LABEL: popa_i16_i64:
; SLOW: # %bb.0:
-; SLOW-NEXT: clrlwi 5, 3, 16
-; SLOW-NEXT: rotlwi 3, 3, 31
-; SLOW-NEXT: andi. 3, 3, 21845
-; SLOW-NEXT: lis 4, 13107
-; SLOW-NEXT: sub 3, 5, 3
-; SLOW-NEXT: ori 4, 4, 13107
-; SLOW-NEXT: rotlwi 5, 3, 30
-; SLOW-NEXT: and 3, 3, 4
-; SLOW-NEXT: andis. 4, 5, 13107
-; SLOW-NEXT: andi. 5, 5, 13107
-; SLOW-NEXT: or 4, 5, 4
-; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 5, 3855
+; SLOW-NEXT: rotlwi 4, 3, 31
+; SLOW-NEXT: andi. 4, 4, 21845
+; SLOW-NEXT: sub 3, 3, 4
+; SLOW-NEXT: andi. 4, 3, 13107
+; SLOW-NEXT: rotlwi 3, 3, 30
+; SLOW-NEXT: andi. 3, 3, 13107
+; SLOW-NEXT: add 3, 4, 3
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
-; SLOW-NEXT: lis 4, 257
-; SLOW-NEXT: ori 5, 5, 3855
-; SLOW-NEXT: and 3, 3, 5
-; SLOW-NEXT: ori 4, 4, 257
-; SLOW-NEXT: mullw 3, 3, 4
-; SLOW-NEXT: srwi 3, 3, 24
+; SLOW-NEXT: andi. 3, 3, 3855
+; SLOW-NEXT: mulli 3, 3, 257
+; SLOW-NEXT: srwi 3, 3, 8
; SLOW-NEXT: rlwinm 3, 3, 0, 27, 27
; SLOW-NEXT: blr
%pop = call i16 @llvm.ctpop.i16(i16 %x)
diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
index 8113b8d604d7a..acf6903b3626c 100644
--- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -139,33 +139,19 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1
-; RV32I-NEXT: lui a2, 349525
-; RV32I-NEXT: addi a2, a2, 1365
-; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: andi a1, a1, 85
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lui a1, 209715
-; RV32I-NEXT: addi a1, a1, 819
-; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: andi a1, a0, 51
; RV32I-NEXT: srli a0, a0, 2
-; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: add a0, a2, a0
+; RV32I-NEXT: andi a0, a0, 51
+; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lui a1, 61681
-; RV32I-NEXT: addi a1, a1, -241
-; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lui a1, 4112
-; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: call __mulsi3 at plt
-; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: andi a0, a0, 15
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
@@ -176,55 +162,19 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV64I-NEXT: andi a1, a0, 255
; RV64I-NEXT: beqz a1, .LBB3_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: andi a1, a1, 85
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: and a2, a0, a1
+; RV64I-NEXT: andi a1, a0, 51
; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
+; RV64I-NEXT: andi a0, a0, 51
+; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, 4112
-; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: addi a0, zero, 8
@@ -241,17 +191,15 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: beqz a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %cond.false
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1
-; RV32I-NEXT: lui a2, 349525
+; RV32I-NEXT: lui a2, 5
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lui a1, 209715
+; RV32I-NEXT: lui a1, 3
; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2
@@ -259,15 +207,15 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lui a1, 61681
+; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lui a1, 4112
-; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: call __mulsi3 at plt
-; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: add a0, a1, a0
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, -256
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
@@ -280,55 +228,31 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: beqz a1, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: lui a1, 3
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, 4112
-; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: add a0, a1, a0
+; RV64I-NEXT: lui a1, 2
+; RV64I-NEXT: addiw a1, a1, -256
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: addi a0, zero, 16
@@ -381,51 +305,29 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a1, a0, -1
+; RV64I-NEXT: addiw a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -489,63 +391,36 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 1
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 8
+; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
+; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: addi a0, a0, -32
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -693,86 +568,36 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8_zero_undef:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1
-; RV32I-NEXT: lui a2, 349525
-; RV32I-NEXT: addi a2, a2, 1365
-; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: andi a1, a1, 85
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lui a1, 209715
-; RV32I-NEXT: addi a1, a1, 819
-; RV32I-NEXT: and a2, a0, a1
+; RV32I-NEXT: andi a1, a0, 51
; RV32I-NEXT: srli a0, a0, 2
-; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: add a0, a2, a0
+; RV32I-NEXT: andi a0, a0, 51
+; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lui a1, 61681
-; RV32I-NEXT: addi a1, a1, -241
-; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lui a1, 4112
-; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: call __mulsi3 at plt
-; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: andi a0, a0, 15
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_cttz_i8_zero_undef:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: andi a1, a1, 85
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: and a2, a0, a1
+; RV64I-NEXT: andi a1, a0, 51
; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
+; RV64I-NEXT: andi a0, a0, 51
+; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, 4112
-; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: ret
%tmp = call i8 @llvm.cttz.i8(i8 %a, i1 true)
ret i8 %tmp
@@ -781,17 +606,15 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-LABEL: test_cttz_i16_zero_undef:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a1, a0, 1
-; RV32I-NEXT: lui a2, 349525
+; RV32I-NEXT: lui a2, 5
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lui a1, 209715
+; RV32I-NEXT: lui a1, 3
; RV32I-NEXT: addi a1, a1, 819
; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: srli a0, a0, 2
@@ -799,68 +622,44 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lui a1, 61681
+; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, -241
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lui a1, 4112
-; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: call __mulsi3 at plt
-; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: add a0, a1, a0
+; RV32I-NEXT: lui a1, 2
+; RV32I-NEXT: addi a1, a1, -256
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_cttz_i16_zero_undef:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 5
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: lui a1, 3
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 1
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, 4112
-; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: slli a1, a0, 8
+; RV64I-NEXT: add a0, a1, a0
+; RV64I-NEXT: lui a1, 2
+; RV64I-NEXT: addiw a1, a1, -256
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: srli a0, a0, 8
; RV64I-NEXT: ret
%tmp = call i16 @llvm.cttz.i16(i16 %a, i1 true)
ret i16 %tmp
@@ -902,51 +701,29 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a1, a0, -1
+; RV64I-NEXT: addiw a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -1116,44 +893,26 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: srli a1, a1, 32
-; RV64I-NEXT: srliw a0, a0, 1
+; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: sub a0, a1, a0
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: lui a2, 13107
-; RV64I-NEXT: addiw a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
+; RV64I-NEXT: addiw a1, a1, 819
+; RV64I-NEXT: and a2, a0, a1
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index 66e55bd278314..d10f54f67d6fd 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -14,63 +14,36 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 1
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 8
+; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: addi a0, a0, -32
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -94,63 +67,36 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srliw a1, a0, 1
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 8
+; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: addi a0, a0, -32
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: j .LBB1_3
@@ -184,63 +130,36 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: beqz a0, .LBB2_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
+; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 8
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
+; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: addi a1, a0, -32
+; RV64I-NEXT: srliw a1, a0, 24
; RV64I-NEXT: .LBB2_2: # %cond.end
; RV64I-NEXT: sub a0, s0, a1
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
@@ -268,68 +187,41 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: srliw a1, s0, 1
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 4
+; RV64I-NEXT: srliw a0, a0, 1
+; RV64I-NEXT: or a0, s0, a0
+; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 8
+; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
+; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srliw a1, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: beqz s0, .LBB3_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: srli a0, a1, 56
-; RV64I-NEXT: addi a0, a0, -32
+; RV64I-NEXT: srliw a0, a1, 24
; RV64I-NEXT: xori a0, a0, 31
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
@@ -372,54 +264,31 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: lui a1, 524272
+; RV64I-NEXT: and a1, a0, a1
+; RV64I-NEXT: srli a1, a1, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: addi a0, a0, -32
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -525,51 +394,29 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a1, a0, -1
+; RV64I-NEXT: addiw a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -590,51 +437,29 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a1, a0, -1
+; RV64I-NEXT: addiw a1, a0, -1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -654,55 +479,33 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
-; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: not a1, s0
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: beqz s0, .LBB8_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: srli a0, a1, 56
+; RV64I-NEXT: srliw a0, a1, 24
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
@@ -731,55 +534,33 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
-; RV64I-NEXT: addi a0, a0, -1
+; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: not a1, s0
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 21845
+; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 13107
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 819
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: beqz s0, .LBB9_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: srli a0, a1, 56
+; RV64I-NEXT: srliw a0, a1, 24
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
@@ -880,44 +661,26 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: srli a1, a1, 32
-; RV64I-NEXT: srliw a0, a0, 1
+; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: sub a0, a1, a0
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: lui a2, 13107
-; RV64I-NEXT: addiw a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
+; RV64I-NEXT: addiw a1, a1, 819
+; RV64I-NEXT: and a2, a0, a1
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -935,43 +698,27 @@ define signext i32 @ctpop_i32_load(i32* %p) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lwu a0, 0(a0)
+; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: lui a2, 13107
-; RV64I-NEXT: addiw a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
-; RV64I-NEXT: slli a2, a2, 12
-; RV64I-NEXT: addi a2, a2, 819
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 209715
+; RV64I-NEXT: addiw a1, a1, 819
+; RV64I-NEXT: and a2, a0, a1
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 3855
-; RV64I-NEXT: addiw a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, 241
-; RV64I-NEXT: slli a1, a1, 12
-; RV64I-NEXT: addi a1, a1, -241
+; RV64I-NEXT: lui a1, 61681
+; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
-; RV64I-NEXT: slli a1, a1, 16
-; RV64I-NEXT: addi a1, a1, 257
; RV64I-NEXT: call __muldi3 at plt
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
More information about the llvm-commits
mailing list