[PATCH] D112320: [SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added a comment.

Hey @kmclaughlin,
Thank you for  adding me as a reviewer  of the patch.
Do we know what was the logic to set ExtType to  ISD::EXTLOAD?
I don't see that on other parts of the legalisation for Masked load.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:762
+
   SDLoc dl(N);
   SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
----------------
As we are replacing ExtType, do we need to pass isExpanding?
I can see in void DAGTypeLegalizer::SplitVecRes_MLOAD and DAGTypeLegalizer::WidenVecRes_MLOAD 
they have a 
XLD->isExpandingLoad()


Repository:
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https://reviews.llvm.org/D112320