[PATCH] D111856: [AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

This is another case that would ideally be handled with demanded bits analysis. We would visit (or x, c1), see that none of the bits set in c1 are demanded, and simplify to x.


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https://reviews.llvm.org/D111856