[PATCH] D112311: [AArch64] Handle ST1iN instructions in isAArch64FrameOffsetLegal

[Danila Malyutin via Phabricator via llvm-commits]

danilaml created this revision.
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Before the code would crash with "unhandled opcode in
isAArch64FrameOffsetLegal" when there was a spill from extractelement.
Fixes pr52249


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112311

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/aarch64st1.ll


Index: llvm/test/CodeGen/AArch64/aarch64st1.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64st1.ll
@@ -0,0 +1,27 @@
+; Check that it doesn't crash with unhandled opcode error, see pr52249
+; RUN: llc < %s -o -| FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-none-linux-gnu"
+
+; CHECK-LABEL: test_st1_to_sp:
+define void @test_st1_to_sp(<2 x i32> %a, <4 x i16> %b, <8 x i8> %c) gc "statepoint-example" {
+entry:
+; CHECK-DAG: st1 { v0.s }
+; CHECK-DAG: st1 { v1.h }
+; CHECK-DAG: st1 { v2.b }
+  %0 = ashr exact <2 x i32> %a, <i32 1, i32 1>
+  %1 = extractelement <2 x i32> %0, i32 1
+  %2 = ashr exact <4 x i16> %b, <i16 1, i16 1, i16 1, i16 1>
+  %3 = extractelement <4 x i16> %2, i32 1
+  %4 = ashr exact <8 x i8> %c, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %5 = extractelement <8 x i8> %4, i32 1
+  %sp_token = call token (i64, i32, void (i32)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32f(i64 2, i32 4, void (i32)* nonnull @bar, i32 1, i32 0, i32 undef, i32 0, i32 0) [ "deopt"(i32 %1, i16 %3, i8 %5) ]
+  ret void
+}
+
+declare void @bar(i32) gc "statepoint-example"
+
+declare token @llvm.experimental.gc.statepoint.p0f_p1i8i64i64i64i64f(i64 immarg, i32 immarg, i8 addrspace(1)* (i64, i64, i64, i64)*, i32 immarg, i32 immarg, ...)
+
+declare token @llvm.experimental.gc.statepoint.p0f_isVoidi32f(i64 immarg, i32 immarg, void (i32)*, i32 immarg, i32 immarg, ...)
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4288,6 +4288,9 @@
   case AArch64::ST1Twov1d:
   case AArch64::ST1Threev1d:
   case AArch64::ST1Fourv1d:
+  case AArch64::ST1i8:
+  case AArch64::ST1i16:
+  case AArch64::ST1i32:
   case AArch64::IRG:
   case AArch64::IRGstack:
   case AArch64::STGloop:


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