[PATCH] D112063: [lld][ELF] Add first bits to support relocation relaxations for AArch64

[Wilco Dijkstra via Phabricator via llvm-commits]

Wilco1 added a comment.

This looks like a good start. Note to be 100% safe you need to check that these relocations always appear in pairs first, otherwise a sequence like this could fail:

     adrp x0, :got: x
     b    1f
     adrp x0, :got: x
  1: ldr  x0, [x0, :got_lo12: x]



================
Comment at: lld/ELF/Arch/AArch64.cpp:612
+  // Check if ADPR and LDR use the same register.
+  if (adrpDestReg != ldrDestReg)
+    return false;
----------------
The source of the ldr also needs to be the same as the destination


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https://reviews.llvm.org/D112063