[PATCH] D112306: [ScheduleDAGInstrs] Call adjustSchedDependency in more cases
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 22 04:31:07 PDT 2021
foad created this revision.
Herald added subscribers: hiraditya, MatzeB.
foad requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
This removes a condition and the corresponding FIXME comment, because
the Hexagon assertion it refers to has apparently been fixed, probably
by D76134 <https://reviews.llvm.org/D76134>.
NFCI. This just gives targets the opportunity to adjust latencies that
were set to 0 by the generic code because they involve "implicit pseudo"
operands.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D112306
Files:
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
Index: llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
===================================================================
--- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -271,15 +271,10 @@
if (!ImplicitPseudoDef && !ImplicitPseudoUse) {
Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
RegUse, UseOp));
- ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
} else {
Dep.setLatency(0);
- // FIXME: We could always let target to adjustSchedDependency(), and
- // remove this condition, but that currently asserts in Hexagon BE.
- if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle()))
- ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
}
-
+ ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
UseSU->addPred(Dep);
}
}
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