[PATCH] D112232: [NVPTX] Add imm variants for surface and texture instructions

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
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Texture/sampler/surface target operands can be either a register or 
an immediate (an index of .texref, .samplerref or .surfref).

TableGen declarations for these instructions used to have only
Int64Regs operands, so this caused issues when machine verifier
is turned on:

  *** Bad machine code: Expected a register operand. ***
  - function:    bar
  - basic block: %bb.0  (0x55b144d99ab8)
  - instruction: %4:int32regs = SULD_1D_I32_TRAP 0, killed %2:int32regs
  - operand 1:   0

The solution is to duplicate these instructions for all possible
operand types (i16imm and Int64Regs). Since this would
essentially double the amount code in TableGen, the patch also
does some refactoring for the original instructions to keep
things manageable.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112232

Files:
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
  llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
  llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
  llvm/test/CodeGen/NVPTX/surf-read.ll
  llvm/test/CodeGen/NVPTX/surf-write-cuda.ll
  llvm/test/CodeGen/NVPTX/surf-write.ll
  llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
  llvm/test/CodeGen/NVPTX/tex-read.ll
  llvm/test/CodeGen/NVPTX/texsurf-queries.ll

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