[PATCH] D111638: [AArch64][SVE] Combine predicated FMUL/FADD into FMA

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 381199.
MattDevereau added a comment.
Herald added a subscriber: dexonsmith.

Added != operator to FastMathFlags
Compared FastMathFlags for equality instead of taking their intersection for FMLA combines


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111638/new/

https://reviews.llvm.org/D111638

Files:
  llvm/include/llvm/IR/Operator.h
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmla.ll

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