[PATCH] D111657: [SVE][CodeGen] Enable reciprocal estimates for scalable fdiv/fsqrt

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll:24
+; CHECK-NEXT:    frecps z1.s, z1.s, z2.s
+; CHECK-NEXT:    fmul z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    fmul z0.s, p0/m, z0.s, z1.s
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david-arm wrote:
> It's interesting that the fmul here is the predicated form, whereas for fdiv_recip_4f32 it's the unpredicated form. This has nothing to do with your patch though, but perhaps worth investigating in the future?
@david-arm The predicate is generated for the unpacked types so that inactive lanes can never trigger floating point exceptions.  So this is expected behaviour.

@kmclaughlin This does raise an interesting point though.  Is it safe to use the reciprocal instructions for unpacked types?  With the answer depending on whether these instruction can generate exceptions.


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  https://reviews.llvm.org/D111657/new/

https://reviews.llvm.org/D111657