[PATCH] D112187: [SelectionDAG] Add widen result function for insert subvector

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-insert-vector.ll:407
+
+define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32(<vscale x 2 x i32> %sv0) {
+; CHECK-LABEL: insert_nxv3i32_nxv2i32:
----------------
Is it worth having an equivalent one for floats, i.e.

  define <vscale x 3 x float> @insert_nxv3f32_nxv2f32(<vscale x 2 x float> %sv0)

?


================
Comment at: llvm/test/CodeGen/AArch64/sve-insert-vector.ll:407
+
+define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32(<vscale x 2 x i32> %sv0) {
+; CHECK-LABEL: insert_nxv3i32_nxv2i32:
----------------
david-arm wrote:
> Is it worth having an equivalent one for floats, i.e.
> 
>   define <vscale x 3 x float> @insert_nxv3f32_nxv2f32(<vscale x 2 x float> %sv0)
> 
> ?
Also, I wonder if it's worth having a test where we also pass in a `<vscale x 3 x i32>` vector, i.e.

  define <vscale x 3 x i32> @insert_nxv3i32_nxv2i32_2(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1) {
    %v0 = call <vscale x 3 x i32> @llvm.experimental.vector.insert.nxv3i32.nxv2i32(<vscale x 3 x i32> %sv0, <vscale x 2 x i32> %sv1, i64 0)
    ret <vscale x 3 x i32> %v0
}

I realise this may be covered by one of the tests below, but I just wanted to make sure that a DAG combine wasn't hiding a bug somewhere that's all.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112187/new/

https://reviews.llvm.org/D112187