[PATCH] D112201: [CortexA55][SchedModels] Complete Cortex-A55 scheduler model

[Pavel Kosov via Phabricator via llvm-commits]

kpdev42 created this revision.
kpdev42 added reviewers: dmgreen, NickGuy, andreadb.
Herald added subscribers: gbedwell, hiraditya.
kpdev42 requested review of this revision.
Herald added a project: LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112201

Files:
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/Analysis/CostModel/AArch64/shuffle-select.ll
  llvm/test/Analysis/CostModel/AArch64/vector-select.ll
  llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
  llvm/test/CodeGen/AArch64/aarch64-addv.ll
  llvm/test/CodeGen/AArch64/aarch64-avoid-illegal-extract-subvector.ll
  llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
  llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-smull.ll
  llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
  llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
  llvm/test/CodeGen/AArch64/arm64-dup.ll
  llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
  llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
  llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
  llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
  llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
  llvm/test/CodeGen/AArch64/arm64-nvcast.ll
  llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll
  llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll
  llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/arm64-vhadd.ll
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
  llvm/test/CodeGen/AArch64/build-vector-extract.ll
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
  llvm/test/CodeGen/AArch64/dag-numsignbits.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/AArch64/expand-vector-rot.ll
  llvm/test/CodeGen/AArch64/f16-instructions.ll
  llvm/test/CodeGen/AArch64/fdiv_combine.ll
  llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
  llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
  llvm/test/CodeGen/AArch64/minmax-of-minmax.ll
  llvm/test/CodeGen/AArch64/minmax.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
  llvm/test/CodeGen/AArch64/neon-dotreduce.ll
  llvm/test/CodeGen/AArch64/neon-truncstore.ll
  llvm/test/CodeGen/AArch64/nontemporal.ll
  llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
  llvm/test/CodeGen/AArch64/pow.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
  llvm/test/CodeGen/AArch64/shift-mod.ll
  llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
  llvm/test/CodeGen/AArch64/sitofp-fixed-legal.ll
  llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/sve-fcvt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
  llvm/test/CodeGen/AArch64/sve-insert-element.ll
  llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
  llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
  llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
  llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
  llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/usub_sat_vec.ll
  llvm/test/CodeGen/AArch64/vec-extract-branch.ll
  llvm/test/CodeGen/AArch64/vec-libcalls.ll
  llvm/test/CodeGen/AArch64/vec_cttz.ll
  llvm/test/CodeGen/AArch64/vec_uaddo.ll
  llvm/test/CodeGen/AArch64/vec_umulo.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
  llvm/test/CodeGen/AArch64/vector-fcopysign.ll
  llvm/test/CodeGen/AArch64/vector-gep.ll
  llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll
  llvm/test/CodeGen/AArch64/vselect-constants.ll
  llvm/test/CodeGen/AArch64/xor.ll
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-readadv.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s
  llvm/utils/update_llc_test_checks.py