[PATCH] D110076: [AMDGPU][GlobalISel] Code quality: Combine V_RSQ
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 20 16:56:43 PDT 2021
arsenm requested changes to this revision.
arsenm added inline comments.
This revision now requires changes to proceed.
================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:832
-
-def : RsqPat<V_RSQ_F32_e32, f32>;
-
----------------
Can probably delete the definition of RsqPat too
================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir:14-16
+ ; GCN: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
+ ; GCN: $vgpr0 = COPY [[INT]](s32)
+ ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
----------------
This looks like it lost the fast math flags
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D110076/new/
https://reviews.llvm.org/D110076
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