[PATCH] D112135: [ARM] Fix inline assembly referencing floating point registers on soft-float targets

[Pavel Kosov via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcb9a0dc293cf: [ARM] Fix inline assembly referencing floating point registers on soft-float… (authored by kpdev42).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112135/new/

https://reviews.llvm.org/D112135

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c


Index: clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c
===================================================================
--- /dev/null
+++ clang/test/Sema/arm_inline_asm_constraints_no_fp_regs.c
@@ -0,0 +1,29 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang_cc1 -triple arm -target-feature -fpregs -verify=arm-nofp %s
+
+// w: A 32, 64, or 128-bit floating-point/SIMD register: s0-s31, d0-d31, or q0-q15.
+float test_w(float x) {
+  __asm__("vsqrt.f32 %0, %1"
+          : "=w"(x)
+          : "w"(x)); // No error expected.
+  // arm-nofp-error at 7 {{invalid output constraint '=w' in asm}}
+  return x;
+}
+
+// x: A 32, 64, or 128-bit floating-point/SIMD register: s0-s15, d0-d7, or q0-q3.
+float test_x(float x) {
+  __asm__("vsqrt.f32 %0, %1"
+          : "=x"(x)
+          : "x"(x)); // No error expected.
+  // arm-nofp-error at 16 {{invalid output constraint '=x' in asm}}
+  return x;
+}
+
+// t: A 32, 64, or 128-bit floating-point/SIMD register: s0-s31, d0-d15, or q0-q7.
+float test_t(float x) {
+  __asm__("vsqrt.f32 %0, %1"
+          : "=t"(x)
+          : "t"(x)); // No error expected.
+  // arm-nofp-error at 25 {{invalid output constraint '=t' in asm}}
+  return x;
+}
Index: clang/lib/Basic/Targets/ARM.h
===================================================================
--- clang/lib/Basic/Targets/ARM.h
+++ clang/lib/Basic/Targets/ARM.h
@@ -78,6 +78,7 @@
   unsigned Unaligned : 1;
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
+  unsigned FPRegsDisabled : 1;
 
   enum {
     LDREX_B = (1 << 0), /// byte (8-bit)
Index: clang/lib/Basic/Targets/ARM.cpp
===================================================================
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -446,6 +446,7 @@
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
+  FPRegsDisabled = false;
 
   // This does not diagnose illegal cases like having both
   // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
@@ -522,6 +523,8 @@
       ARMCDECoprocMask |= (1U << Coproc);
     } else if (Feature == "+bf16") {
       HasBFloat16 = true;
+    } else if (Feature == "-fpregs") {
+      FPRegsDisabled = true;
     }
   }
 
@@ -978,6 +981,8 @@
   case 't': // s0-s31, d0-d31, or q0-q15
   case 'w': // s0-s15, d0-d7, or q0-q3
   case 'x': // s0-s31, d0-d15, or q0-q7
+    if (FPRegsDisabled)
+      return false;
     Info.setAllowsRegister();
     return true;
   case 'j': // An immediate integer between 0 and 65535 (valid for MOVW)


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