[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Filipp Zhinkin via Phabricator via llvm-commits]

fzhinkin updated this revision to Diff 381086.
fzhinkin added a comment.

Fixed typos in ARM tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/icmp-shift-opt.ll
  llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
  llvm/test/CodeGen/ARM/icmp-shift-opt.ll
  llvm/test/CodeGen/X86/icmp-shift-opt.ll

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