[PATCH] D111638: [AArch64][SVE] Combine predicated FMUL/FADD into FMA

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 380971.
MattDevereau added a comment.

Restructured logic path by adding instCombineSVEVectorFAdd
Added check for no contract flag when comparing fast flags
Extended matching logic in instCombineSVEVectorFmla to capture value* FMul


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111638/new/

https://reviews.llvm.org/D111638

Files:
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmla.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D111638.380971.patch
Type: text/x-patch
Size: 12851 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211020/c232dfeb/attachment.bin>