[PATCH] D112138: [x86] add special-case lowering for usubsat for AVX512
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 20 07:25:32 PDT 2021
spatel created this revision.
spatel added reviewers: RKSimon, pengfei, craig.topper.
Herald added subscribers: hiraditya, mcrosier.
spatel requested review of this revision.
Herald added a project: LLVM.
This is a small extension of D112095 <https://reviews.llvm.org/D112095> to avoid another regression seen with D112085 <https://reviews.llvm.org/D112085>.
In this case, we allow the same conversion from usubsat to ALU ops if the target supports vpternlog.
That pattern will get converted later in X86DAGToDAGISel::tryVPTERNLOG(). This seems better than putting a magic immediate constant directly in this code to create the exact vpternlog that we need. It's possible that there are other special-cases along these lines, so we should try to keep all of the vpternlog magic in one place.
https://reviews.llvm.org/D112138
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/psubus.ll
Index: llvm/test/CodeGen/X86/psubus.ll
===================================================================
--- llvm/test/CodeGen/X86/psubus.ll
+++ llvm/test/CodeGen/X86/psubus.ll
@@ -162,9 +162,8 @@
;
; AVX512-LABEL: usubsat_custom:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpsubd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vpsrad $31, %xmm0, %xmm1
+; AVX512-NEXT: vpternlogd $72, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
; AVX512-NEXT: retq
%res = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 undef>)
ret <4 x i32> %res
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -28139,26 +28139,32 @@
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
unsigned BitWidth = VT.getScalarSizeInBits();
- if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) {
- // Handle a special-case with a bit-hack instead of cmp+select:
- // usubsat X, SMIN --> (X ^ SMIN) & (X s>> BW-1)
- ConstantSDNode *C = isConstOrConstSplat(Y, true);
- if (C && C->getAPIntValue().isSignMask()) {
- SDValue SignMask = DAG.getConstant(C->getAPIntValue(), DL, VT);
- SDValue ShiftAmt = DAG.getConstant(BitWidth - 1, DL, VT);
- SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, SignMask);
- SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShiftAmt);
- return DAG.getNode(ISD::AND, DL, VT, Xor, Sra);
- }
-
- // usubsat X, Y --> (X >u Y) ? X - Y : 0
- SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y);
- SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Y, ISD::SETUGT);
- // TODO: Move this to DAGCombiner?
- if (SetCCResultType == VT &&
- DAG.ComputeNumSignBits(Cmp) == VT.getScalarSizeInBits())
- return DAG.getNode(ISD::AND, DL, VT, Cmp, Sub);
- return DAG.getSelect(DL, VT, Cmp, Sub, DAG.getConstant(0, DL, VT));
+ if (Opcode == ISD::USUBSAT) {
+ if (!TLI.isOperationLegal(ISD::UMAX, VT) || useVPTERNLOG(Subtarget, VT)) {
+ // Handle a special-case with a bit-hack instead of cmp+select:
+ // usubsat X, SMIN --> (X ^ SMIN) & (X s>> BW-1)
+ // If the target can use VPTERNLOG, DAGToDAG will match this as
+ // "vpsra + vpternlog" which is better than "vpmax + vpsub" with a
+ // "broadcast" constant load.
+ ConstantSDNode *C = isConstOrConstSplat(Y, true);
+ if (C && C->getAPIntValue().isSignMask()) {
+ SDValue SignMask = DAG.getConstant(C->getAPIntValue(), DL, VT);
+ SDValue ShiftAmt = DAG.getConstant(BitWidth - 1, DL, VT);
+ SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, SignMask);
+ SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShiftAmt);
+ return DAG.getNode(ISD::AND, DL, VT, Xor, Sra);
+ }
+ }
+ if (!TLI.isOperationLegal(ISD::UMAX, VT)) {
+ // usubsat X, Y --> (X >u Y) ? X - Y : 0
+ SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y);
+ SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Y, ISD::SETUGT);
+ // TODO: Move this to DAGCombiner?
+ if (SetCCResultType == VT &&
+ DAG.ComputeNumSignBits(Cmp) == VT.getScalarSizeInBits())
+ return DAG.getNode(ISD::AND, DL, VT, Cmp, Sub);
+ return DAG.getSelect(DL, VT, Cmp, Sub, DAG.getConstant(0, DL, VT));
+ }
}
if ((Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) &&
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