[PATCH] D111638: [AArch64][SVE] Combine predicated FMUL/FADD into FMA

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:718
+  if (!match(AddOp1, m_Intrinsic<Intrinsic::aarch64_sve_fmul>()))
+    return None;
+
----------------
MattDevereau wrote:
> peterwaller-arm wrote:
> > peterwaller-arm wrote:
> > > I'd expect this all to look simpler, please have a go at simplifying. I think you can drop the matching logic above and instead add a condition that checks the AddOp1's predicate matches the Add's predicate.
> > > 
> > > One issue I have is that both the swap and m_SVEFAdd as it currently is serve the purpose of testing both operand orders. I think it's important for clarity to only do this once.
> > If you want to use the match syntax above I think you can also bind the fmul with `m_And(m_Value(FMul), m_SVEFMul(m_Deferred(p), m_Value(a), m_Value(b))` and then you could grab `FMul` and `c` simultaneously with the existing logic.
> I've opted to check AddOp1's predicate matches the Add's predicate
Was this what you meant?

```
  if (!match(&II, m_SVEFAdd(m_Value(p),
                            m_And(m_Value(FMul), m_SVEFMul(m_Deferred(p), m_Value(a), m_Value(b))),
                            m_Value(c)))){
    return None;
  }
```
FMul isn't matching in this expression


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111638/new/

https://reviews.llvm.org/D111638