[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

please can you pre-commit these new tests to trunk with current codegen and then rebase to show the diff?



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Comment at: llvm/test/CodeGen/AArch64/arm64-icmp-shift-opt.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
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rename icmp-shift-opt.ll?


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Comment at: llvm/test/CodeGen/ARM/arm-icmp-shift-opt.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
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rename icmp-shift-opt.ll?


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Comment at: llvm/test/CodeGen/X86/icmp-shift-opt.ll:8
+; See https://bugs.llvm.org/show_bug.cgi?id=50197
+define i128 @opt_setcc_lt_power_of_2(i128 %a) {
+; CHECK-LABEL: opt_setcc_lt_power_of_2:
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add nounwind to reduce cfi noise


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530