[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

[Zakk Chen via Phabricator via llvm-commits]

khchen added inline comments.


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Comment at: clang/include/clang/Basic/riscv_vector.td:120
 // type transformer (say "vv") each of the types is separated with an
 // underscore as in "__builtin_rvv_foo_i32m1_i32m1".
 //
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nit: we need to update this comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112102/new/

https://reviews.llvm.org/D112102