[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll:1358
+; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
+; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT:    ret
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vmerge.vvm is for integer vectors, doesn't it? Why does it work for floating point vector types?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D112102/new/

https://reviews.llvm.org/D112102