[PATCH] D112085: [DAGCombiner] fold bit-hack form of usubsat

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 19 10:23:23 PDT 2021


spatel created this revision.
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(i8 X ^ 128) & (i8 X s>> 7) --> usubsat X, 128

I haven't found a generalization of this identity:
https://alive2.llvm.org/ce/z/_sriEQ

Note: I was actually looking at the first form of the pattern in that link, but that's part of a long chain of potential missed transforms in codegen and IR....that I hope ends here!

The predicates for when this is profitable are a bit tricky. This version of the patch allows multi-use but excludes `custom` lowering (as opposed to `legal` only).

On x86, for example, we have custom lowering for some vector types and that uses umax and sub. So if we want to enable that fold, we need add use checks to avoid regressions. Even here, we see that legacy SSE code may need an extra instruction with extra uses, so I can add a constraint to make this more conservative if that seems better.


https://reviews.llvm.org/D112085

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/usubsat.ll
  llvm/test/CodeGen/X86/psubus.ll

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