[llvm] c1ca9e3 - [AMDGPU] add test for usubsat; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-10-19T13:05:23-04:00
New Revision: c1ca9e3077cb8ac39a56ebe73dd2b080fbe56c4e

URL: https://github.com/llvm/llvm-project/commit/c1ca9e3077cb8ac39a56ebe73dd2b080fbe56c4e
DIFF: https://github.com/llvm/llvm-project/commit/c1ca9e3077cb8ac39a56ebe73dd2b080fbe56c4e.diff

LOG: [AMDGPU] add test for usubsat; NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/usubsat.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/usubsat.ll b/llvm/test/CodeGen/AMDGPU/usubsat.ll
index 0c23ee9cf64a5..6d0c64f929bcd 100644
--- a/llvm/test/CodeGen/AMDGPU/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/usubsat.ll
@@ -73,6 +73,46 @@ define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
   ret i16 %result
 }
 
+define i16 @usubsat_as_bithack_i16(i16 %x) {
+; GFX6-LABEL: usubsat_as_bithack_i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v1, v0, 0, 16
+; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
+; GFX6-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; GFX6-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: usubsat_as_bithack_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_ashrrev_i16_e32 v1, 15, v0
+; GFX8-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; GFX8-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: usubsat_as_bithack_i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_ashrrev_i16_e32 v1, 15, v0
+; GFX9-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; GFX9-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: usubsat_as_bithack_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_ashrrev_i16 v1, 15, v0
+; GFX10-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; GFX10-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %signsplat = ashr i16 %x, 15
+  %flipsign = xor i16 %x, 32768
+  %result = and i16 %signsplat, %flipsign
+  ret i16 %result
+}
+
 define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
 ; GFX6-LABEL: v_usubsat_i32:
 ; GFX6:       ; %bb.0: