[PATCH] D112064: [GlobalISel] Combine (build_vector_trunc x, undef) -> (bitcast x)

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: Ravi, arsenm, aemerson, paquette.
Herald added subscribers: ormris, wenlei, kerbowa, steven_wu, hiraditya, tpr, rovka, nhaehnle, jvesely.
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This mostly benefits AMDGPU where arguments to IMAGE instructions are
sometimes packed into the two 16-bit halves of a 32-bit register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112064

Files:
  llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
  llvm/include/llvm/Target/GlobalISel/Combine.td
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll

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