[PATCH] D111846: [LV] Drop NUW/NSW flags from scalarized instructions that need predication

[Diego Caballero via Phabricator via llvm-commits]

dcaballe updated this revision to Diff 380589.
dcaballe marked 10 inline comments as done.
dcaballe added a comment.

Addressed feedback.
When creating a test case for the division instruction I realized that the problem
could also happen for vectorized instructions. For example, the address computation
of a memory access would also be vectorized if the access is a gather/scatter. I
added support for those cases to the VPWidenRecipe.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111846/new/

https://reviews.llvm.org/D111846

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
  llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
  llvm/test/Transforms/LoopVectorize/X86/pr52111.ll
  llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
  llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
  llvm/test/Transforms/LoopVectorize/X86/x86-pr39099.ll
  llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll

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