[llvm] facff46 - [RISCV] Reorder the vector register allocation order.
Hsiangkai Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 18 18:30:56 PDT 2021
Author: Hsiangkai Wang
Date: 2021-10-19T09:30:13+08:00
New Revision: facff468b6c47b954aebd297c90bd44accaa54c6
URL: https://github.com/llvm/llvm-project/commit/facff468b6c47b954aebd297c90bd44accaa54c6
DIFF: https://github.com/llvm/llvm-project/commit/facff468b6c47b954aebd297c90bd44accaa54c6.diff
LOG: [RISCV] Reorder the vector register allocation order.
GPR uses argument registers as the first group of registers to allocate.
This patch uses vector argument registers, v8 to v23, as the first group
to allocate.
Differential Revision: https://reviews.llvm.org/D111304
Added:
Modified:
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll
llvm/test/CodeGen/RISCV/byval.ll
llvm/test/CodeGen/RISCV/calls.ll
llvm/test/CodeGen/RISCV/copy-frameindex.mir
llvm/test/CodeGen/RISCV/double-calling-conv.ll
llvm/test/CodeGen/RISCV/double-previous-failure.ll
llvm/test/CodeGen/RISCV/fastcc-int.ll
llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
llvm/test/CodeGen/RISCV/rvv/load-mask.ll
llvm/test/CodeGen/RISCV/rvv/localvar.ll
llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll
llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll
llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/select-fp.ll
llvm/test/CodeGen/RISCV/rvv/select-int.ll
llvm/test/CodeGen/RISCV/rvv/select-sra.ll
llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
llvm/test/CodeGen/RISCV/rvv/stepvector.ll
llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
llvm/test/CodeGen/RISCV/select-optimize-multiple.mir
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 179494071c9d1..1d690d287f38b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -487,8 +487,7 @@ def VR : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t,
vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t,
vbool2_t, vbool1_t],
- (add (sequence "V%u", 25, 31),
- (sequence "V%u", 8, 24),
+ (add (sequence "V%u", 8, 31),
(sequence "V%u", 0, 7)), 1>;
def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
@@ -498,27 +497,26 @@ def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t,
vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t,
vbool2_t, vbool1_t],
- (add (sequence "V%u", 25, 31),
- (sequence "V%u", 8, 24),
+ (add (sequence "V%u", 8, 31),
(sequence "V%u", 1, 7)), 1>;
def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
vfloat16m2_t, vfloat32m2_t, vfloat64m2_t],
- (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2,
- V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2), 2>;
+ (add (sequence "V%uM2", 8, 31, 2),
+ (sequence "V%uM2", 0, 7, 2)), 2>;
def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
vfloat16m2_t, vfloat32m2_t, vfloat64m2_t],
- (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2,
- V18M2, V20M2, V22M2, V24M2, V2M2, V4M2, V6M2), 2>;
+ (add (sequence "V%uM2", 8, 31, 2),
+ (sequence "V%uM2", 2, 7, 2)), 2>;
def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
vfloat16m4_t, vfloat32m4_t, vfloat64m4_t],
- (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4), 4>;
+ (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>;
def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
vfloat16m4_t, vfloat32m4_t, vfloat64m4_t],
- (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V4M4), 4>;
+ (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>;
def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
vfloat16m8_t, vfloat32m8_t, vfloat64m8_t],
@@ -526,7 +524,7 @@ def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
vfloat16m8_t, vfloat32m8_t, vfloat64m8_t],
- (add V8M8, V16M8, V24M8), 8>;
+ (add V8M8, V16M8, V24M8), 8>;
defvar VMaskVTs = [vbool64_t, vbool32_t, vbool16_t, vbool8_t,
vbool4_t, vbool2_t, vbool1_t];
@@ -538,8 +536,7 @@ def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
// The register class is added for inline assembly for vector mask types.
def VM : VReg<[vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
vbool32_t, vbool64_t],
- (add (sequence "V%u", 25, 31),
- (sequence "V%u", 8, 24),
+ (add (sequence "V%u", 8, 31),
(sequence "V%u", 0, 7)), 1>;
foreach m = LMULList.m in {
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll b/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll
index 44438c1cc210c..6a7f04b6304eb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll
@@ -5,13 +5,14 @@
; RUN: | FileCheck -check-prefix=RV64I %s
define void @foo() {
- ; RV32I-LABEL: foo
- ; RV32I: # %bb.0: # %entry
- ; RV32I: ret
+; RV32I-LABEL: foo:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: foo:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: ret
- ; RV64I-LABEL: foo
- ; RV64I: # %bb.0: # %entry
- ; RV64I: ret
entry:
ret void
}
diff --git a/llvm/test/CodeGen/RISCV/byval.ll b/llvm/test/CodeGen/RISCV/byval.ll
index 684d3a8aab96b..113d5f468625d 100644
--- a/llvm/test/CodeGen/RISCV/byval.ll
+++ b/llvm/test/CodeGen/RISCV/byval.ll
@@ -33,7 +33,7 @@ define void @caller() nounwind {
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: addi a0, sp, 12
-; RV32I-NEXT: call callee
+; RV32I-NEXT: call callee at plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll
index a54d08dbbde61..7a964ebb42221 100644
--- a/llvm/test/CodeGen/RISCV/calls.ll
+++ b/llvm/test/CodeGen/RISCV/calls.ll
@@ -71,7 +71,7 @@ define i32 @test_call_defined(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: call defined_function
+; RV32I-NEXT: call defined_function at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -178,7 +178,7 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
-; RV32I-NEXT: call fastcc_function
+; RV32I-NEXT: call fastcc_function at plt
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -282,7 +282,7 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0
-; RV32I-NEXT: call defined_many_args
+; RV32I-NEXT: call defined_many_args at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/copy-frameindex.mir b/llvm/test/CodeGen/RISCV/copy-frameindex.mir
index be86a1af8b508..6280874c80441 100644
--- a/llvm/test/CodeGen/RISCV/copy-frameindex.mir
+++ b/llvm/test/CodeGen/RISCV/copy-frameindex.mir
@@ -39,15 +39,19 @@ stack:
body: |
; CHECK-LABEL: name: sink_addi_fi
; CHECK: bb.0:
- ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK: BEQ killed [[COPY]], $x0, %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0
- ; CHECK: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0)
- ; CHECK: bb.2:
- ; CHECK: PseudoRET
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: BEQ killed [[COPY]], $x0, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0
+ ; CHECK-NEXT: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: PseudoRET
bb.0:
liveins: $x10
%0:gpr = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
index b956611744197..5731216ba53bf 100644
--- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
@@ -41,7 +41,7 @@ define double @caller_double_inreg() nounwind {
; RV32IFD-NEXT: lui a2, 262364
; RV32IFD-NEXT: addi a3, a2, 655
; RV32IFD-NEXT: mv a2, a0
-; RV32IFD-NEXT: call callee_double_inreg
+; RV32IFD-NEXT: call callee_double_inreg at plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
@@ -88,7 +88,7 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: mv a4, zero
; RV32IFD-NEXT: mv a7, a5
-; RV32IFD-NEXT: call callee_double_split_reg_stack
+; RV32IFD-NEXT: call callee_double_split_reg_stack at plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
@@ -135,7 +135,7 @@ define double @caller_double_stack() nounwind {
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: mv a7, zero
-; RV32IFD-NEXT: call callee_double_stack
+; RV32IFD-NEXT: call callee_double_stack at plt
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
index b6969745d8545..d3c20db19716a 100644
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -19,7 +19,7 @@ define i32 @main() nounwind {
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: mv a0, zero
-; RV32IFD-NEXT: call test
+; RV32IFD-NEXT: call test at plt
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
diff --git a/llvm/test/CodeGen/RISCV/fastcc-int.ll b/llvm/test/CodeGen/RISCV/fastcc-int.ll
index 8b240dc8a6355..363fd5d3cc734 100644
--- a/llvm/test/CodeGen/RISCV/fastcc-int.ll
+++ b/llvm/test/CodeGen/RISCV/fastcc-int.ll
@@ -44,7 +44,7 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV32-NEXT: sw s0, 4(sp)
; RV32-NEXT: sw t1, 0(sp)
; RV32-NEXT: mv a0, t0
-; RV32-NEXT: call callee
+; RV32-NEXT: call callee at plt
; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
@@ -75,7 +75,7 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV64-NEXT: sd s0, 8(sp)
; RV64-NEXT: sd t1, 0(sp)
; RV64-NEXT: mv a0, t0
-; RV64-NEXT: call callee
+; RV64-NEXT: call callee at plt
; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 48
diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
index f7ce4ce98b5e6..575a09b7922b9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
@@ -8,8 +8,8 @@ define <vscale x 1 x i16> @vabs_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vabs_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vrsub.vi v25, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x i16> @llvm.abs.nxv1i16(<vscale x 1 x i16> %v, i1 false)
ret <vscale x 1 x i16> %r
@@ -21,8 +21,8 @@ define <vscale x 2 x i16> @vabs_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vabs_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v25, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 2 x i16> @llvm.abs.nxv2i16(<vscale x 2 x i16> %v, i1 false)
ret <vscale x 2 x i16> %r
@@ -34,8 +34,8 @@ define <vscale x 4 x i16> @vabs_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vabs_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v25, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 4 x i16> @llvm.abs.nxv4i16(<vscale x 4 x i16> %v, i1 false)
ret <vscale x 4 x i16> %r
@@ -47,8 +47,8 @@ define <vscale x 8 x i16> @vabs_nxv8i16(<vscale x 8 x i16> %v) {
; CHECK-LABEL: vabs_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v26, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v26
+; CHECK-NEXT: vrsub.vi v10, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %v, i1 false)
ret <vscale x 8 x i16> %r
@@ -60,8 +60,8 @@ define <vscale x 16 x i16> @vabs_nxv16i16(<vscale x 16 x i16> %v) {
; CHECK-LABEL: vabs_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v28, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v28
+; CHECK-NEXT: vrsub.vi v12, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %v, i1 false)
ret <vscale x 16 x i16> %r
@@ -86,8 +86,8 @@ define <vscale x 1 x i32> @vabs_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vabs_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v25, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x i32> @llvm.abs.nxv1i32(<vscale x 1 x i32> %v, i1 false)
ret <vscale x 1 x i32> %r
@@ -99,8 +99,8 @@ define <vscale x 2 x i32> @vabs_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vabs_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v25, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 2 x i32> @llvm.abs.nxv2i32(<vscale x 2 x i32> %v, i1 false)
ret <vscale x 2 x i32> %r
@@ -112,8 +112,8 @@ define <vscale x 4 x i32> @vabs_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vabs_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v26, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v26
+; CHECK-NEXT: vrsub.vi v10, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %v, i1 false)
ret <vscale x 4 x i32> %r
@@ -125,8 +125,8 @@ define <vscale x 8 x i32> @vabs_nxv8i32(<vscale x 8 x i32> %v) {
; CHECK-LABEL: vabs_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v28, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v28
+; CHECK-NEXT: vrsub.vi v12, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %v, i1 false)
ret <vscale x 8 x i32> %r
@@ -151,8 +151,8 @@ define <vscale x 1 x i64> @vabs_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vabs_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v25, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x i64> @llvm.abs.nxv1i64(<vscale x 1 x i64> %v, i1 false)
ret <vscale x 1 x i64> %r
@@ -164,8 +164,8 @@ define <vscale x 2 x i64> @vabs_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vabs_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v26, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v26
+; CHECK-NEXT: vrsub.vi v10, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %v, i1 false)
ret <vscale x 2 x i64> %r
@@ -177,8 +177,8 @@ define <vscale x 4 x i64> @vabs_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vabs_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v28, v8, 0
-; CHECK-NEXT: vmax.vv v8, v8, v28
+; CHECK-NEXT: vrsub.vi v12, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %v, i1 false)
ret <vscale x 4 x i64> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
index f6de53441a052..e46879448d6c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
@@ -35,12 +35,12 @@ define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: addi a0, sp, 24
-; RV64IV-NEXT: vl1re64.v v25, (a0)
+; RV64IV-NEXT: vl1re64.v v8, (a0)
; RV64IV-NEXT: ld a0, 536(sp)
; RV64IV-NEXT: addi a1, sp, 544
-; RV64IV-NEXT: vl1re64.v v26, (a1)
+; RV64IV-NEXT: vl1re64.v v9, (a1)
; RV64IV-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; RV64IV-NEXT: vadd.vv v8, v25, v26
+; RV64IV-NEXT: vadd.vv v8, v8, v9
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: addi sp, sp, 544
diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
index 5cd831a1d3a3b..9528631626810 100644
--- a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
@@ -40,13 +40,13 @@ body: |
; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB
; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12
; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 88, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: renamable $v25 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
+ ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
; CHECK-NEXT: $x11 = PseudoReadVLENB
; CHECK-NEXT: $x10 = LUI 1048575
; CHECK-NEXT: $x10 = ADDIW killed $x10, 1824
; CHECK-NEXT: $x10 = ADD $x8, killed $x10
; CHECK-NEXT: $x10 = SUB killed $x10, killed $x11
- ; CHECK-NEXT: VS1R_V killed renamable $v25, killed renamable $x10
+ ; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10
; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
index 468f1a0c2b320..0aca89c978c1c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
@@ -25,8 +25,8 @@ define <vscale x 2 x i64> @or_and_nxv2i64(<vscale x 2 x i64> %a0) {
; CHECK-LABEL: or_and_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vor.vi v26, v8, 3
-; CHECK-NEXT: vand.vi v8, v26, 7
+; CHECK-NEXT: vor.vi v8, v8, 3
+; CHECK-NEXT: vand.vi v8, v8, 7
; CHECK-NEXT: ret
%ins1 = insertelement <vscale x 2 x i64> poison, i64 7, i32 0
%splat1 = shufflevector <vscale x 2 x i64> %ins1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
@@ -61,11 +61,11 @@ define <vscale x 4 x i32> @combine_vec_shl_shl(<vscale x 4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 2
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, zero, 4
-; CHECK-NEXT: vmv.s.x v28, a0
-; CHECK-NEXT: vsll.vv v26, v8, v26
-; CHECK-NEXT: vsll.vv v8, v26, v28
+; CHECK-NEXT: vmv.s.x v12, a0
+; CHECK-NEXT: vsll.vv v8, v8, v10
+; CHECK-NEXT: vsll.vv v8, v8, v12
; CHECK-NEXT: ret
%ins1 = insertelement <vscale x 4 x i32> poison, i32 2, i32 0
%splat1 = shufflevector <vscale x 4 x i32> %ins1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
index 7b3a2bd8def7e..b7ef676a67258 100644
--- a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
@@ -7,8 +7,8 @@ define void @combine_fp_zero_stores_crash(float* %ptr) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%addr1 = getelementptr float, float * %ptr, i64 1
%addr2 = getelementptr float, float * %ptr, i64 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll b/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
index b24b747a52602..a18398c1e2419 100644
--- a/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
@@ -7,33 +7,33 @@ target triple = "riscv64-unknown-unknown-elf"
define dso_local <16 x i16> @interleave(<8 x i16> %v0, <8 x i16> %v1) {
; CHECK-LABEL: interleave:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v26, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8m2
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetivli zero, 8, e16, m2, tu, mu
-; CHECK-NEXT: vmv2r.v v30, v28
-; CHECK-NEXT: vslideup.vi v30, v8, 0
+; CHECK-NEXT: vmv2r.v v14, v12
+; CHECK-NEXT: vslideup.vi v14, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v30, v8, 8
+; CHECK-NEXT: vslideup.vi v14, v8, 8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vsrl.vi v12, v10, 1
-; CHECK-NEXT: vrgather.vv v14, v30, v12
+; CHECK-NEXT: vid.v v16
+; CHECK-NEXT: vsrl.vi v18, v16, 1
+; CHECK-NEXT: vrgather.vv v20, v14, v18
; CHECK-NEXT: vsetivli zero, 8, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v28, v26, 0
+; CHECK-NEXT: vslideup.vi v12, v10, 0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v28, v8, 8
+; CHECK-NEXT: vslideup.vi v12, v8, 8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v8, v14, v10
+; CHECK-NEXT: vrgather.vv v8, v20, v16
; CHECK-NEXT: lui a0, 11
; CHECK-NEXT: addiw a0, a0, -1366
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v8, v28, v12, v0.t
+; CHECK-NEXT: vrgather.vv v8, v12, v18, v0.t
; CHECK-NEXT: ret
entry:
%v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
index 6e311f4f6393c..31bde5a895315 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
@@ -17,22 +17,22 @@ define <2 x i16> @fixedlen(<2 x i32> %x) {
; RV32-LABEL: fixedlen:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vsrl.vi v25, v8, 16
+; RV32-NEXT: vsrl.vi v8, v8, 16
; RV32-NEXT: lui a0, 1048568
-; RV32-NEXT: vand.vx v25, v25, a0
+; RV32-NEXT: vand.vx v8, v8, a0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v8, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: ret
;
; RV64-LABEL: fixedlen:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vsrl.vi v25, v8, 16
+; RV64-NEXT: vsrl.vi v8, v8, 16
; RV64-NEXT: lui a0, 131071
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: vand.vx v25, v25, a0
+; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v8, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: ret
%v41 = insertelement <2 x i32> undef, i32 16, i32 0
%v42 = shufflevector <2 x i32> %v41, <2 x i32> undef, <2 x i32> zeroinitializer
@@ -49,11 +49,11 @@ define <vscale x 2 x i16> @scalable(<vscale x 2 x i32> %x) {
; CHECK-LABEL: scalable:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsrl.vi v25, v8, 16
+; CHECK-NEXT: vsrl.vi v8, v8, 16
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: lui a0, 1048568
-; CHECK-NEXT: vand.vx v8, v25, a0
+; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: ret
%v41 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
%v42 = shufflevector <vscale x 2 x i32> %v41, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
index 48ebe9f8ecad9..bf9c21bc50fc5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
@@ -7,8 +7,8 @@ define <vscale x 1 x i8> @sextload_nxv1i1_nxv1i8(<vscale x 1 x i1>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%y = load <vscale x 1 x i1>, <vscale x 1 x i1>* %x
%z = sext <vscale x 1 x i1> %y to <vscale x 1 x i8>
@@ -19,9 +19,9 @@ define <vscale x 1 x i16> @sextload_nxv1i8_nxv1i16(<vscale x 1 x i8>* %x) {
; CHECK-LABEL: sextload_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
%z = sext <vscale x 1 x i8> %y to <vscale x 1 x i16>
@@ -32,9 +32,9 @@ define <vscale x 1 x i16> @zextload_nxv1i8_nxv1i16(<vscale x 1 x i8>* %x) {
; CHECK-LABEL: zextload_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
%z = zext <vscale x 1 x i8> %y to <vscale x 1 x i16>
@@ -45,9 +45,9 @@ define <vscale x 1 x i32> @sextload_nxv1i8_nxv1i32(<vscale x 1 x i8>* %x) {
; CHECK-LABEL: sextload_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
%z = sext <vscale x 1 x i8> %y to <vscale x 1 x i32>
@@ -58,9 +58,9 @@ define <vscale x 1 x i32> @zextload_nxv1i8_nxv1i32(<vscale x 1 x i8>* %x) {
; CHECK-LABEL: zextload_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
%z = zext <vscale x 1 x i8> %y to <vscale x 1 x i32>
@@ -71,9 +71,9 @@ define <vscale x 1 x i64> @sextload_nxv1i8_nxv1i64(<vscale x 1 x i8>* %x) {
; CHECK-LABEL: sextload_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf8 v8, v25
+; CHECK-NEXT: vsext.vf8 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
%z = sext <vscale x 1 x i8> %y to <vscale x 1 x i64>
@@ -84,9 +84,9 @@ define <vscale x 1 x i64> @zextload_nxv1i8_nxv1i64(<vscale x 1 x i8>* %x) {
; CHECK-LABEL: zextload_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf8 v8, v25
+; CHECK-NEXT: vzext.vf8 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
%z = zext <vscale x 1 x i8> %y to <vscale x 1 x i64>
@@ -97,9 +97,9 @@ define <vscale x 2 x i16> @sextload_nxv2i8_nxv2i16(<vscale x 2 x i8>* %x) {
; CHECK-LABEL: sextload_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
%z = sext <vscale x 2 x i8> %y to <vscale x 2 x i16>
@@ -110,9 +110,9 @@ define <vscale x 2 x i16> @zextload_nxv2i8_nxv2i16(<vscale x 2 x i8>* %x) {
; CHECK-LABEL: zextload_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
%z = zext <vscale x 2 x i8> %y to <vscale x 2 x i16>
@@ -123,9 +123,9 @@ define <vscale x 2 x i32> @sextload_nxv2i8_nxv2i32(<vscale x 2 x i8>* %x) {
; CHECK-LABEL: sextload_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
%z = sext <vscale x 2 x i8> %y to <vscale x 2 x i32>
@@ -136,9 +136,9 @@ define <vscale x 2 x i32> @zextload_nxv2i8_nxv2i32(<vscale x 2 x i8>* %x) {
; CHECK-LABEL: zextload_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
%z = zext <vscale x 2 x i8> %y to <vscale x 2 x i32>
@@ -149,9 +149,9 @@ define <vscale x 2 x i64> @sextload_nxv2i8_nxv2i64(<vscale x 2 x i8>* %x) {
; CHECK-LABEL: sextload_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf8 v8, v25
+; CHECK-NEXT: vsext.vf8 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
%z = sext <vscale x 2 x i8> %y to <vscale x 2 x i64>
@@ -162,9 +162,9 @@ define <vscale x 2 x i64> @zextload_nxv2i8_nxv2i64(<vscale x 2 x i8>* %x) {
; CHECK-LABEL: zextload_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf8 v8, v25
+; CHECK-NEXT: vzext.vf8 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
%z = zext <vscale x 2 x i8> %y to <vscale x 2 x i64>
@@ -175,9 +175,9 @@ define <vscale x 4 x i16> @sextload_nxv4i8_nxv4i16(<vscale x 4 x i8>* %x) {
; CHECK-LABEL: sextload_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
%z = sext <vscale x 4 x i8> %y to <vscale x 4 x i16>
@@ -188,9 +188,9 @@ define <vscale x 4 x i16> @zextload_nxv4i8_nxv4i16(<vscale x 4 x i8>* %x) {
; CHECK-LABEL: zextload_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
%z = zext <vscale x 4 x i8> %y to <vscale x 4 x i16>
@@ -201,9 +201,9 @@ define <vscale x 4 x i32> @sextload_nxv4i8_nxv4i32(<vscale x 4 x i8>* %x) {
; CHECK-LABEL: sextload_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
%z = sext <vscale x 4 x i8> %y to <vscale x 4 x i32>
@@ -214,9 +214,9 @@ define <vscale x 4 x i32> @zextload_nxv4i8_nxv4i32(<vscale x 4 x i8>* %x) {
; CHECK-LABEL: zextload_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
%z = zext <vscale x 4 x i8> %y to <vscale x 4 x i32>
@@ -227,9 +227,9 @@ define <vscale x 4 x i64> @sextload_nxv4i8_nxv4i64(<vscale x 4 x i8>* %x) {
; CHECK-LABEL: sextload_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v12, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v8, v25
+; CHECK-NEXT: vsext.vf8 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
%z = sext <vscale x 4 x i8> %y to <vscale x 4 x i64>
@@ -240,9 +240,9 @@ define <vscale x 4 x i64> @zextload_nxv4i8_nxv4i64(<vscale x 4 x i8>* %x) {
; CHECK-LABEL: zextload_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v12, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v8, v25
+; CHECK-NEXT: vzext.vf8 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
%z = zext <vscale x 4 x i8> %y to <vscale x 4 x i64>
@@ -252,9 +252,9 @@ define <vscale x 4 x i64> @zextload_nxv4i8_nxv4i64(<vscale x 4 x i8>* %x) {
define <vscale x 8 x i16> @sextload_nxv8i8_nxv8i16(<vscale x 8 x i8>* %x) {
; CHECK-LABEL: sextload_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a0)
+; CHECK-NEXT: vl1r.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
%z = sext <vscale x 8 x i8> %y to <vscale x 8 x i16>
@@ -264,9 +264,9 @@ define <vscale x 8 x i16> @sextload_nxv8i8_nxv8i16(<vscale x 8 x i8>* %x) {
define <vscale x 8 x i16> @zextload_nxv8i8_nxv8i16(<vscale x 8 x i8>* %x) {
; CHECK-LABEL: zextload_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a0)
+; CHECK-NEXT: vl1r.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
%z = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>
@@ -276,9 +276,9 @@ define <vscale x 8 x i16> @zextload_nxv8i8_nxv8i16(<vscale x 8 x i8>* %x) {
define <vscale x 8 x i32> @sextload_nxv8i8_nxv8i32(<vscale x 8 x i8>* %x) {
; CHECK-LABEL: sextload_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a0)
+; CHECK-NEXT: vl1r.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
%z = sext <vscale x 8 x i8> %y to <vscale x 8 x i32>
@@ -288,9 +288,9 @@ define <vscale x 8 x i32> @sextload_nxv8i8_nxv8i32(<vscale x 8 x i8>* %x) {
define <vscale x 8 x i32> @zextload_nxv8i8_nxv8i32(<vscale x 8 x i8>* %x) {
; CHECK-LABEL: zextload_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a0)
+; CHECK-NEXT: vl1r.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
%z = zext <vscale x 8 x i8> %y to <vscale x 8 x i32>
@@ -300,9 +300,9 @@ define <vscale x 8 x i32> @zextload_nxv8i8_nxv8i32(<vscale x 8 x i8>* %x) {
define <vscale x 8 x i64> @sextload_nxv8i8_nxv8i64(<vscale x 8 x i8>* %x) {
; CHECK-LABEL: sextload_nxv8i8_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a0)
+; CHECK-NEXT: vl1r.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vsext.vf8 v8, v25
+; CHECK-NEXT: vsext.vf8 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
%z = sext <vscale x 8 x i8> %y to <vscale x 8 x i64>
@@ -312,9 +312,9 @@ define <vscale x 8 x i64> @sextload_nxv8i8_nxv8i64(<vscale x 8 x i8>* %x) {
define <vscale x 8 x i64> @zextload_nxv8i8_nxv8i64(<vscale x 8 x i8>* %x) {
; CHECK-LABEL: zextload_nxv8i8_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a0)
+; CHECK-NEXT: vl1r.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vzext.vf8 v8, v25
+; CHECK-NEXT: vzext.vf8 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
%z = zext <vscale x 8 x i8> %y to <vscale x 8 x i64>
@@ -324,9 +324,9 @@ define <vscale x 8 x i64> @zextload_nxv8i8_nxv8i64(<vscale x 8 x i8>* %x) {
define <vscale x 16 x i16> @sextload_nxv16i8_nxv16i16(<vscale x 16 x i8>* %x) {
; CHECK-LABEL: sextload_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2r.v v26, (a0)
+; CHECK-NEXT: vl2r.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v26
+; CHECK-NEXT: vsext.vf2 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 16 x i8>, <vscale x 16 x i8>* %x
%z = sext <vscale x 16 x i8> %y to <vscale x 16 x i16>
@@ -336,9 +336,9 @@ define <vscale x 16 x i16> @sextload_nxv16i8_nxv16i16(<vscale x 16 x i8>* %x) {
define <vscale x 16 x i16> @zextload_nxv16i8_nxv16i16(<vscale x 16 x i8>* %x) {
; CHECK-LABEL: zextload_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2r.v v26, (a0)
+; CHECK-NEXT: vl2r.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v26
+; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 16 x i8>, <vscale x 16 x i8>* %x
%z = zext <vscale x 16 x i8> %y to <vscale x 16 x i16>
@@ -348,9 +348,9 @@ define <vscale x 16 x i16> @zextload_nxv16i8_nxv16i16(<vscale x 16 x i8>* %x) {
define <vscale x 16 x i32> @sextload_nxv16i8_nxv16i32(<vscale x 16 x i8>* %x) {
; CHECK-LABEL: sextload_nxv16i8_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2r.v v26, (a0)
+; CHECK-NEXT: vl2r.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v26
+; CHECK-NEXT: vsext.vf4 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 16 x i8>, <vscale x 16 x i8>* %x
%z = sext <vscale x 16 x i8> %y to <vscale x 16 x i32>
@@ -360,9 +360,9 @@ define <vscale x 16 x i32> @sextload_nxv16i8_nxv16i32(<vscale x 16 x i8>* %x) {
define <vscale x 16 x i32> @zextload_nxv16i8_nxv16i32(<vscale x 16 x i8>* %x) {
; CHECK-LABEL: zextload_nxv16i8_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2r.v v26, (a0)
+; CHECK-NEXT: vl2r.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v26
+; CHECK-NEXT: vzext.vf4 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 16 x i8>, <vscale x 16 x i8>* %x
%z = zext <vscale x 16 x i8> %y to <vscale x 16 x i32>
@@ -372,9 +372,9 @@ define <vscale x 16 x i32> @zextload_nxv16i8_nxv16i32(<vscale x 16 x i8>* %x) {
define <vscale x 32 x i16> @sextload_nxv32i8_nxv32i16(<vscale x 32 x i8>* %x) {
; CHECK-LABEL: sextload_nxv32i8_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v28
+; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 32 x i8>, <vscale x 32 x i8>* %x
%z = sext <vscale x 32 x i8> %y to <vscale x 32 x i16>
@@ -384,9 +384,9 @@ define <vscale x 32 x i16> @sextload_nxv32i8_nxv32i16(<vscale x 32 x i8>* %x) {
define <vscale x 32 x i16> @zextload_nxv32i8_nxv32i16(<vscale x 32 x i8>* %x) {
; CHECK-LABEL: zextload_nxv32i8_nxv32i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v28
+; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 32 x i8>, <vscale x 32 x i8>* %x
%z = zext <vscale x 32 x i8> %y to <vscale x 32 x i16>
@@ -397,9 +397,9 @@ define void @truncstore_nxv1i8_nxv1i1(<vscale x 1 x i8> %x, <vscale x 1 x i1> *%
; CHECK-LABEL: truncstore_nxv1i8_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v8, v8, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i8> %x to <vscale x 1 x i1>
store <vscale x 1 x i1> %y, <vscale x 1 x i1>* %z
@@ -410,8 +410,8 @@ define void @truncstore_nxv1i16_nxv1i8(<vscale x 1 x i16> %x, <vscale x 1 x i8>*
; CHECK-LABEL: truncstore_nxv1i16_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>
store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z
@@ -422,9 +422,9 @@ define <vscale x 1 x i32> @sextload_nxv1i16_nxv1i32(<vscale x 1 x i16>* %x) {
; CHECK-LABEL: sextload_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i16>, <vscale x 1 x i16>* %x
%z = sext <vscale x 1 x i16> %y to <vscale x 1 x i32>
@@ -435,9 +435,9 @@ define <vscale x 1 x i32> @zextload_nxv1i16_nxv1i32(<vscale x 1 x i16>* %x) {
; CHECK-LABEL: zextload_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i16>, <vscale x 1 x i16>* %x
%z = zext <vscale x 1 x i16> %y to <vscale x 1 x i32>
@@ -448,9 +448,9 @@ define <vscale x 1 x i64> @sextload_nxv1i16_nxv1i64(<vscale x 1 x i16>* %x) {
; CHECK-LABEL: sextload_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i16>, <vscale x 1 x i16>* %x
%z = sext <vscale x 1 x i16> %y to <vscale x 1 x i64>
@@ -461,9 +461,9 @@ define <vscale x 1 x i64> @zextload_nxv1i16_nxv1i64(<vscale x 1 x i16>* %x) {
; CHECK-LABEL: zextload_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i16>, <vscale x 1 x i16>* %x
%z = zext <vscale x 1 x i16> %y to <vscale x 1 x i64>
@@ -474,8 +474,8 @@ define void @truncstore_nxv2i16_nxv2i8(<vscale x 2 x i16> %x, <vscale x 2 x i8>*
; CHECK-LABEL: truncstore_nxv2i16_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i16> %x to <vscale x 2 x i8>
store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z
@@ -486,9 +486,9 @@ define <vscale x 2 x i32> @sextload_nxv2i16_nxv2i32(<vscale x 2 x i16>* %x) {
; CHECK-LABEL: sextload_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x i16>, <vscale x 2 x i16>* %x
%z = sext <vscale x 2 x i16> %y to <vscale x 2 x i32>
@@ -499,9 +499,9 @@ define <vscale x 2 x i32> @zextload_nxv2i16_nxv2i32(<vscale x 2 x i16>* %x) {
; CHECK-LABEL: zextload_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x i16>, <vscale x 2 x i16>* %x
%z = zext <vscale x 2 x i16> %y to <vscale x 2 x i32>
@@ -512,9 +512,9 @@ define <vscale x 2 x i64> @sextload_nxv2i16_nxv2i64(<vscale x 2 x i16>* %x) {
; CHECK-LABEL: sextload_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x i16>, <vscale x 2 x i16>* %x
%z = sext <vscale x 2 x i16> %y to <vscale x 2 x i64>
@@ -525,9 +525,9 @@ define <vscale x 2 x i64> @zextload_nxv2i16_nxv2i64(<vscale x 2 x i16>* %x) {
; CHECK-LABEL: zextload_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x i16>, <vscale x 2 x i16>* %x
%z = zext <vscale x 2 x i16> %y to <vscale x 2 x i64>
@@ -538,8 +538,8 @@ define void @truncstore_nxv4i16_nxv4i8(<vscale x 4 x i16> %x, <vscale x 4 x i8>*
; CHECK-LABEL: truncstore_nxv4i16_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i16> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
@@ -549,9 +549,9 @@ define void @truncstore_nxv4i16_nxv4i8(<vscale x 4 x i16> %x, <vscale x 4 x i8>*
define <vscale x 4 x i32> @sextload_nxv4i16_nxv4i32(<vscale x 4 x i16>* %x) {
; CHECK-LABEL: sextload_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 4 x i16>, <vscale x 4 x i16>* %x
%z = sext <vscale x 4 x i16> %y to <vscale x 4 x i32>
@@ -561,9 +561,9 @@ define <vscale x 4 x i32> @sextload_nxv4i16_nxv4i32(<vscale x 4 x i16>* %x) {
define <vscale x 4 x i32> @zextload_nxv4i16_nxv4i32(<vscale x 4 x i16>* %x) {
; CHECK-LABEL: zextload_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 4 x i16>, <vscale x 4 x i16>* %x
%z = zext <vscale x 4 x i16> %y to <vscale x 4 x i32>
@@ -573,9 +573,9 @@ define <vscale x 4 x i32> @zextload_nxv4i16_nxv4i32(<vscale x 4 x i16>* %x) {
define <vscale x 4 x i64> @sextload_nxv4i16_nxv4i64(<vscale x 4 x i16>* %x) {
; CHECK-LABEL: sextload_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x i16>, <vscale x 4 x i16>* %x
%z = sext <vscale x 4 x i16> %y to <vscale x 4 x i64>
@@ -585,9 +585,9 @@ define <vscale x 4 x i64> @sextload_nxv4i16_nxv4i64(<vscale x 4 x i16>* %x) {
define <vscale x 4 x i64> @zextload_nxv4i16_nxv4i64(<vscale x 4 x i16>* %x) {
; CHECK-LABEL: zextload_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x i16>, <vscale x 4 x i16>* %x
%z = zext <vscale x 4 x i16> %y to <vscale x 4 x i64>
@@ -598,8 +598,8 @@ define void @truncstore_nxv8i16_nxv8i8(<vscale x 8 x i16> %x, <vscale x 8 x i8>*
; CHECK-LABEL: truncstore_nxv8i16_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i16> %x to <vscale x 8 x i8>
store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z
@@ -609,9 +609,9 @@ define void @truncstore_nxv8i16_nxv8i8(<vscale x 8 x i16> %x, <vscale x 8 x i8>*
define <vscale x 8 x i32> @sextload_nxv8i16_nxv8i32(<vscale x 8 x i16>* %x) {
; CHECK-LABEL: sextload_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v26
+; CHECK-NEXT: vsext.vf2 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 8 x i16>, <vscale x 8 x i16>* %x
%z = sext <vscale x 8 x i16> %y to <vscale x 8 x i32>
@@ -621,9 +621,9 @@ define <vscale x 8 x i32> @sextload_nxv8i16_nxv8i32(<vscale x 8 x i16>* %x) {
define <vscale x 8 x i32> @zextload_nxv8i16_nxv8i32(<vscale x 8 x i16>* %x) {
; CHECK-LABEL: zextload_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v26
+; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 8 x i16>, <vscale x 8 x i16>* %x
%z = zext <vscale x 8 x i16> %y to <vscale x 8 x i32>
@@ -633,9 +633,9 @@ define <vscale x 8 x i32> @zextload_nxv8i16_nxv8i32(<vscale x 8 x i16>* %x) {
define <vscale x 8 x i64> @sextload_nxv8i16_nxv8i64(<vscale x 8 x i16>* %x) {
; CHECK-LABEL: sextload_nxv8i16_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v26
+; CHECK-NEXT: vsext.vf4 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x i16>, <vscale x 8 x i16>* %x
%z = sext <vscale x 8 x i16> %y to <vscale x 8 x i64>
@@ -645,9 +645,9 @@ define <vscale x 8 x i64> @sextload_nxv8i16_nxv8i64(<vscale x 8 x i16>* %x) {
define <vscale x 8 x i64> @zextload_nxv8i16_nxv8i64(<vscale x 8 x i16>* %x) {
; CHECK-LABEL: zextload_nxv8i16_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v26
+; CHECK-NEXT: vzext.vf4 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x i16>, <vscale x 8 x i16>* %x
%z = zext <vscale x 8 x i16> %y to <vscale x 8 x i64>
@@ -658,8 +658,8 @@ define void @truncstore_nxv16i16_nxv16i8(<vscale x 16 x i16> %x, <vscale x 16 x
; CHECK-LABEL: truncstore_nxv16i16_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 16 x i16> %x to <vscale x 16 x i8>
store <vscale x 16 x i8> %y, <vscale x 16 x i8>* %z
@@ -669,9 +669,9 @@ define void @truncstore_nxv16i16_nxv16i8(<vscale x 16 x i16> %x, <vscale x 16 x
define <vscale x 16 x i32> @sextload_nxv16i16_nxv16i32(<vscale x 16 x i16>* %x) {
; CHECK-LABEL: sextload_nxv16i16_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v28
+; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 16 x i16>, <vscale x 16 x i16>* %x
%z = sext <vscale x 16 x i16> %y to <vscale x 16 x i32>
@@ -681,9 +681,9 @@ define <vscale x 16 x i32> @sextload_nxv16i16_nxv16i32(<vscale x 16 x i16>* %x)
define <vscale x 16 x i32> @zextload_nxv16i16_nxv16i32(<vscale x 16 x i16>* %x) {
; CHECK-LABEL: zextload_nxv16i16_nxv16i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v28
+; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 16 x i16>, <vscale x 16 x i16>* %x
%z = zext <vscale x 16 x i16> %y to <vscale x 16 x i32>
@@ -694,8 +694,8 @@ define void @truncstore_nxv32i16_nxv32i8(<vscale x 32 x i16> %x, <vscale x 32 x
; CHECK-LABEL: truncstore_nxv32i16_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 32 x i16> %x to <vscale x 32 x i8>
store <vscale x 32 x i8> %y, <vscale x 32 x i8>* %z
@@ -706,10 +706,10 @@ define void @truncstore_nxv1i32_nxv1i8(<vscale x 1 x i32> %x, <vscale x 1 x i8>*
; CHECK-LABEL: truncstore_nxv1i32_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i8>
store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z
@@ -720,8 +720,8 @@ define void @truncstore_nxv1i32_nxv1i16(<vscale x 1 x i32> %x, <vscale x 1 x i16
; CHECK-LABEL: truncstore_nxv1i32_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16>
store <vscale x 1 x i16> %y, <vscale x 1 x i16>* %z
@@ -732,9 +732,9 @@ define <vscale x 1 x i64> @sextload_nxv1i32_nxv1i64(<vscale x 1 x i32>* %x) {
; CHECK-LABEL: sextload_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i32>, <vscale x 1 x i32>* %x
%z = sext <vscale x 1 x i32> %y to <vscale x 1 x i64>
@@ -745,9 +745,9 @@ define <vscale x 1 x i64> @zextload_nxv1i32_nxv1i64(<vscale x 1 x i32>* %x) {
; CHECK-LABEL: zextload_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x i32>, <vscale x 1 x i32>* %x
%z = zext <vscale x 1 x i32> %y to <vscale x 1 x i64>
@@ -758,10 +758,10 @@ define void @truncstore_nxv2i32_nxv2i8(<vscale x 2 x i32> %x, <vscale x 2 x i8>*
; CHECK-LABEL: truncstore_nxv2i32_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i8>
store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z
@@ -772,8 +772,8 @@ define void @truncstore_nxv2i32_nxv2i16(<vscale x 2 x i32> %x, <vscale x 2 x i16
; CHECK-LABEL: truncstore_nxv2i32_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i32> %x to <vscale x 2 x i16>
store <vscale x 2 x i16> %y, <vscale x 2 x i16>* %z
@@ -783,9 +783,9 @@ define void @truncstore_nxv2i32_nxv2i16(<vscale x 2 x i32> %x, <vscale x 2 x i16
define <vscale x 2 x i64> @sextload_nxv2i32_nxv2i64(<vscale x 2 x i32>* %x) {
; CHECK-LABEL: sextload_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re32.v v25, (a0)
+; CHECK-NEXT: vl1re32.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x i32>, <vscale x 2 x i32>* %x
%z = sext <vscale x 2 x i32> %y to <vscale x 2 x i64>
@@ -795,9 +795,9 @@ define <vscale x 2 x i64> @sextload_nxv2i32_nxv2i64(<vscale x 2 x i32>* %x) {
define <vscale x 2 x i64> @zextload_nxv2i32_nxv2i64(<vscale x 2 x i32>* %x) {
; CHECK-LABEL: zextload_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re32.v v25, (a0)
+; CHECK-NEXT: vl1re32.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x i32>, <vscale x 2 x i32>* %x
%z = zext <vscale x 2 x i32> %y to <vscale x 2 x i64>
@@ -808,10 +808,10 @@ define void @truncstore_nxv4i32_nxv4i8(<vscale x 4 x i32> %x, <vscale x 4 x i8>*
; CHECK-LABEL: truncstore_nxv4i32_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
@@ -822,8 +822,8 @@ define void @truncstore_nxv4i32_nxv4i16(<vscale x 4 x i32> %x, <vscale x 4 x i16
; CHECK-LABEL: truncstore_nxv4i32_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i32> %x to <vscale x 4 x i16>
store <vscale x 4 x i16> %y, <vscale x 4 x i16>* %z
@@ -833,9 +833,9 @@ define void @truncstore_nxv4i32_nxv4i16(<vscale x 4 x i32> %x, <vscale x 4 x i16
define <vscale x 4 x i64> @sextload_nxv4i32_nxv4i64(<vscale x 4 x i32>* %x) {
; CHECK-LABEL: sextload_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re32.v v26, (a0)
+; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v26
+; CHECK-NEXT: vsext.vf2 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x i32>, <vscale x 4 x i32>* %x
%z = sext <vscale x 4 x i32> %y to <vscale x 4 x i64>
@@ -845,9 +845,9 @@ define <vscale x 4 x i64> @sextload_nxv4i32_nxv4i64(<vscale x 4 x i32>* %x) {
define <vscale x 4 x i64> @zextload_nxv4i32_nxv4i64(<vscale x 4 x i32>* %x) {
; CHECK-LABEL: zextload_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re32.v v26, (a0)
+; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v26
+; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x i32>, <vscale x 4 x i32>* %x
%z = zext <vscale x 4 x i32> %y to <vscale x 4 x i64>
@@ -858,10 +858,10 @@ define void @truncstore_nxv8i32_nxv8i8(<vscale x 8 x i32> %x, <vscale x 8 x i8>*
; CHECK-LABEL: truncstore_nxv8i32_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i8>
store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z
@@ -872,8 +872,8 @@ define void @truncstore_nxv8i32_nxv8i16(<vscale x 8 x i32> %x, <vscale x 8 x i16
; CHECK-LABEL: truncstore_nxv8i32_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i32> %x to <vscale x 8 x i16>
store <vscale x 8 x i16> %y, <vscale x 8 x i16>* %z
@@ -883,9 +883,9 @@ define void @truncstore_nxv8i32_nxv8i16(<vscale x 8 x i32> %x, <vscale x 8 x i16
define <vscale x 8 x i64> @sextload_nxv8i32_nxv8i64(<vscale x 8 x i32>* %x) {
; CHECK-LABEL: sextload_nxv8i32_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v28
+; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x i32>, <vscale x 8 x i32>* %x
%z = sext <vscale x 8 x i32> %y to <vscale x 8 x i64>
@@ -895,9 +895,9 @@ define <vscale x 8 x i64> @sextload_nxv8i32_nxv8i64(<vscale x 8 x i32>* %x) {
define <vscale x 8 x i64> @zextload_nxv8i32_nxv8i64(<vscale x 8 x i32>* %x) {
; CHECK-LABEL: zextload_nxv8i32_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v28
+; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x i32>, <vscale x 8 x i32>* %x
%z = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>
@@ -908,10 +908,10 @@ define void @truncstore_nxv16i32_nxv16i8(<vscale x 16 x i32> %x, <vscale x 16 x
; CHECK-LABEL: truncstore_nxv16i32_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v28, 0
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i8>
store <vscale x 16 x i8> %y, <vscale x 16 x i8>* %z
@@ -922,8 +922,8 @@ define void @truncstore_nxv16i32_nxv16i16(<vscale x 16 x i32> %x, <vscale x 16 x
; CHECK-LABEL: truncstore_nxv16i32_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 16 x i32> %x to <vscale x 16 x i16>
store <vscale x 16 x i16> %y, <vscale x 16 x i16>* %z
@@ -934,12 +934,12 @@ define void @truncstore_nxv1i64_nxv1i8(<vscale x 1 x i64> %x, <vscale x 1 x i8>*
; CHECK-LABEL: truncstore_nxv1i64_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i8>
store <vscale x 1 x i8> %y, <vscale x 1 x i8>* %z
@@ -950,10 +950,10 @@ define void @truncstore_nxv1i64_nxv1i16(<vscale x 1 x i64> %x, <vscale x 1 x i16
; CHECK-LABEL: truncstore_nxv1i64_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i16>
store <vscale x 1 x i16> %y, <vscale x 1 x i16>* %z
@@ -964,8 +964,8 @@ define void @truncstore_nxv1i64_nxv1i32(<vscale x 1 x i64> %x, <vscale x 1 x i32
; CHECK-LABEL: truncstore_nxv1i64_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
store <vscale x 1 x i32> %y, <vscale x 1 x i32>* %z
@@ -976,12 +976,12 @@ define void @truncstore_nxv2i64_nxv2i8(<vscale x 2 x i64> %x, <vscale x 2 x i8>*
; CHECK-LABEL: truncstore_nxv2i64_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i8>
store <vscale x 2 x i8> %y, <vscale x 2 x i8>* %z
@@ -992,10 +992,10 @@ define void @truncstore_nxv2i64_nxv2i16(<vscale x 2 x i64> %x, <vscale x 2 x i16
; CHECK-LABEL: truncstore_nxv2i64_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i16>
store <vscale x 2 x i16> %y, <vscale x 2 x i16>* %z
@@ -1006,8 +1006,8 @@ define void @truncstore_nxv2i64_nxv2i32(<vscale x 2 x i64> %x, <vscale x 2 x i32
; CHECK-LABEL: truncstore_nxv2i64_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
store <vscale x 2 x i32> %y, <vscale x 2 x i32>* %z
@@ -1018,12 +1018,12 @@ define void @truncstore_nxv4i64_nxv4i8(<vscale x 4 x i64> %x, <vscale x 4 x i8>*
; CHECK-LABEL: truncstore_nxv4i64_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i8>
store <vscale x 4 x i8> %y, <vscale x 4 x i8>* %z
@@ -1034,10 +1034,10 @@ define void @truncstore_nxv4i64_nxv4i16(<vscale x 4 x i64> %x, <vscale x 4 x i16
; CHECK-LABEL: truncstore_nxv4i64_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i16>
store <vscale x 4 x i16> %y, <vscale x 4 x i16>* %z
@@ -1048,8 +1048,8 @@ define void @truncstore_nxv4i64_nxv4i32(<vscale x 4 x i64> %x, <vscale x 4 x i32
; CHECK-LABEL: truncstore_nxv4i64_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
store <vscale x 4 x i32> %y, <vscale x 4 x i32>* %z
@@ -1060,12 +1060,12 @@ define void @truncstore_nxv8i64_nxv8i8(<vscale x 8 x i64> %x, <vscale x 8 x i8>*
; CHECK-LABEL: truncstore_nxv8i64_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i8>
store <vscale x 8 x i8> %y, <vscale x 8 x i8>* %z
@@ -1076,10 +1076,10 @@ define void @truncstore_nxv8i64_nxv8i16(<vscale x 8 x i64> %x, <vscale x 8 x i16
; CHECK-LABEL: truncstore_nxv8i64_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v28, 0
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i16>
store <vscale x 8 x i16> %y, <vscale x 8 x i16>* %z
@@ -1090,8 +1090,8 @@ define void @truncstore_nxv8i64_nxv8i32(<vscale x 8 x i64> %x, <vscale x 8 x i32
; CHECK-LABEL: truncstore_nxv8i64_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
store <vscale x 8 x i32> %y, <vscale x 8 x i32>* %z
@@ -1102,8 +1102,8 @@ define <vscale x 1 x float> @extload_nxv1f16_nxv1f32(<vscale x 1 x half>* %x) {
; CHECK-LABEL: extload_nxv1f16_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x half>, <vscale x 1 x half>* %x
%z = fpext <vscale x 1 x half> %y to <vscale x 1 x float>
@@ -1114,10 +1114,10 @@ define <vscale x 1 x double> @extload_nxv1f16_nxv1f64(<vscale x 1 x half>* %x) {
; CHECK-LABEL: extload_nxv1f16_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x half>, <vscale x 1 x half>* %x
%z = fpext <vscale x 1 x half> %y to <vscale x 1 x double>
@@ -1128,8 +1128,8 @@ define <vscale x 2 x float> @extload_nxv2f16_nxv2f32(<vscale x 2 x half>* %x) {
; CHECK-LABEL: extload_nxv2f16_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x half>, <vscale x 2 x half>* %x
%z = fpext <vscale x 2 x half> %y to <vscale x 2 x float>
@@ -1140,10 +1140,10 @@ define <vscale x 2 x double> @extload_nxv2f16_nxv2f64(<vscale x 2 x half>* %x) {
; CHECK-LABEL: extload_nxv2f16_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x half>, <vscale x 2 x half>* %x
%z = fpext <vscale x 2 x half> %y to <vscale x 2 x double>
@@ -1153,9 +1153,9 @@ define <vscale x 2 x double> @extload_nxv2f16_nxv2f64(<vscale x 2 x half>* %x) {
define <vscale x 4 x float> @extload_nxv4f16_nxv4f32(<vscale x 4 x half>* %x) {
; CHECK-LABEL: extload_nxv4f16_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 4 x half>, <vscale x 4 x half>* %x
%z = fpext <vscale x 4 x half> %y to <vscale x 4 x float>
@@ -1165,11 +1165,11 @@ define <vscale x 4 x float> @extload_nxv4f16_nxv4f32(<vscale x 4 x half>* %x) {
define <vscale x 4 x double> @extload_nxv4f16_nxv4f64(<vscale x 4 x half>* %x) {
; CHECK-LABEL: extload_nxv4f16_nxv4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x half>, <vscale x 4 x half>* %x
%z = fpext <vscale x 4 x half> %y to <vscale x 4 x double>
@@ -1179,9 +1179,9 @@ define <vscale x 4 x double> @extload_nxv4f16_nxv4f64(<vscale x 4 x half>* %x) {
define <vscale x 8 x float> @extload_nxv8f16_nxv8f32(<vscale x 8 x half>* %x) {
; CHECK-LABEL: extload_nxv8f16_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 8 x half>, <vscale x 8 x half>* %x
%z = fpext <vscale x 8 x half> %y to <vscale x 8 x float>
@@ -1191,11 +1191,11 @@ define <vscale x 8 x float> @extload_nxv8f16_nxv8f32(<vscale x 8 x half>* %x) {
define <vscale x 8 x double> @extload_nxv8f16_nxv8f64(<vscale x 8 x half>* %x) {
; CHECK-LABEL: extload_nxv8f16_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v26
+; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x half>, <vscale x 8 x half>* %x
%z = fpext <vscale x 8 x half> %y to <vscale x 8 x double>
@@ -1205,9 +1205,9 @@ define <vscale x 8 x double> @extload_nxv8f16_nxv8f64(<vscale x 8 x half>* %x) {
define <vscale x 16 x float> @extload_nxv16f16_nxv16f32(<vscale x 16 x half>* %x) {
; CHECK-LABEL: extload_nxv16f16_nxv16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 16 x half>, <vscale x 16 x half>* %x
%z = fpext <vscale x 16 x half> %y to <vscale x 16 x float>
@@ -1218,8 +1218,8 @@ define void @truncstore_nxv1f32_nxv1f16(<vscale x 1 x float> %x, <vscale x 1 x h
; CHECK-LABEL: truncstore_nxv1f32_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 1 x float> %x to <vscale x 1 x half>
store <vscale x 1 x half> %y, <vscale x 1 x half>* %z
@@ -1230,8 +1230,8 @@ define <vscale x 1 x double> @extload_nxv1f32_nxv1f64(<vscale x 1 x float>* %x)
; CHECK-LABEL: extload_nxv1f32_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 1 x float>, <vscale x 1 x float>* %x
%z = fpext <vscale x 1 x float> %y to <vscale x 1 x double>
@@ -1242,8 +1242,8 @@ define void @truncstore_nxv2f32_nxv2f16(<vscale x 2 x float> %x, <vscale x 2 x h
; CHECK-LABEL: truncstore_nxv2f32_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 2 x float> %x to <vscale x 2 x half>
store <vscale x 2 x half> %y, <vscale x 2 x half>* %z
@@ -1253,9 +1253,9 @@ define void @truncstore_nxv2f32_nxv2f16(<vscale x 2 x float> %x, <vscale x 2 x h
define <vscale x 2 x double> @extload_nxv2f32_nxv2f64(<vscale x 2 x float>* %x) {
; CHECK-LABEL: extload_nxv2f32_nxv2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re32.v v25, (a0)
+; CHECK-NEXT: vl1re32.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x float>, <vscale x 2 x float>* %x
%z = fpext <vscale x 2 x float> %y to <vscale x 2 x double>
@@ -1266,8 +1266,8 @@ define void @truncstore_nxv4f32_nxv4f16(<vscale x 4 x float> %x, <vscale x 4 x h
; CHECK-LABEL: truncstore_nxv4f32_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 4 x float> %x to <vscale x 4 x half>
store <vscale x 4 x half> %y, <vscale x 4 x half>* %z
@@ -1277,9 +1277,9 @@ define void @truncstore_nxv4f32_nxv4f16(<vscale x 4 x float> %x, <vscale x 4 x h
define <vscale x 4 x double> @extload_nxv4f32_nxv4f64(<vscale x 4 x float>* %x) {
; CHECK-LABEL: extload_nxv4f32_nxv4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re32.v v26, (a0)
+; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x float>, <vscale x 4 x float>* %x
%z = fpext <vscale x 4 x float> %y to <vscale x 4 x double>
@@ -1290,8 +1290,8 @@ define void @truncstore_nxv8f32_nxv8f16(<vscale x 8 x float> %x, <vscale x 8 x h
; CHECK-LABEL: truncstore_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 8 x float> %x to <vscale x 8 x half>
store <vscale x 8 x half> %y, <vscale x 8 x half>* %z
@@ -1301,9 +1301,9 @@ define void @truncstore_nxv8f32_nxv8f16(<vscale x 8 x float> %x, <vscale x 8 x h
define <vscale x 8 x double> @extload_nxv8f32_nxv8f64(<vscale x 8 x float>* %x) {
; CHECK-LABEL: extload_nxv8f32_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x float>, <vscale x 8 x float>* %x
%z = fpext <vscale x 8 x float> %y to <vscale x 8 x double>
@@ -1314,8 +1314,8 @@ define void @truncstore_nxv16f32_nxv16f16(<vscale x 16 x float> %x, <vscale x 16
; CHECK-LABEL: truncstore_nxv16f32_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 16 x float> %x to <vscale x 16 x half>
store <vscale x 16 x half> %y, <vscale x 16 x half>* %z
@@ -1326,10 +1326,10 @@ define void @truncstore_nxv1f64_nxv1f16(<vscale x 1 x double> %x, <vscale x 1 x
; CHECK-LABEL: truncstore_nxv1f64_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 1 x double> %x to <vscale x 1 x half>
store <vscale x 1 x half> %y, <vscale x 1 x half>* %z
@@ -1340,8 +1340,8 @@ define void @truncstore_nxv1f64_nxv1f32(<vscale x 1 x double> %x, <vscale x 1 x
; CHECK-LABEL: truncstore_nxv1f64_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 1 x double> %x to <vscale x 1 x float>
store <vscale x 1 x float> %y, <vscale x 1 x float>* %z
@@ -1352,10 +1352,10 @@ define void @truncstore_nxv2f64_nxv2f16(<vscale x 2 x double> %x, <vscale x 2 x
; CHECK-LABEL: truncstore_nxv2f64_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v8, v10
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 2 x double> %x to <vscale x 2 x half>
store <vscale x 2 x half> %y, <vscale x 2 x half>* %z
@@ -1366,8 +1366,8 @@ define void @truncstore_nxv2f64_nxv2f32(<vscale x 2 x double> %x, <vscale x 2 x
; CHECK-LABEL: truncstore_nxv2f64_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 2 x double> %x to <vscale x 2 x float>
store <vscale x 2 x float> %y, <vscale x 2 x float>* %z
@@ -1378,10 +1378,10 @@ define void @truncstore_nxv4f64_nxv4f16(<vscale x 4 x double> %x, <vscale x 4 x
; CHECK-LABEL: truncstore_nxv4f64_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v26
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v8, v12
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 4 x double> %x to <vscale x 4 x half>
store <vscale x 4 x half> %y, <vscale x 4 x half>* %z
@@ -1392,8 +1392,8 @@ define void @truncstore_nxv4f64_nxv4f32(<vscale x 4 x double> %x, <vscale x 4 x
; CHECK-LABEL: truncstore_nxv4f64_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 4 x double> %x to <vscale x 4 x float>
store <vscale x 4 x float> %y, <vscale x 4 x float>* %z
@@ -1404,10 +1404,10 @@ define void @truncstore_nxv8f64_nxv8f16(<vscale x 8 x double> %x, <vscale x 8 x
; CHECK-LABEL: truncstore_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v8, v16
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 8 x double> %x to <vscale x 8 x half>
store <vscale x 8 x half> %y, <vscale x 8 x half>* %z
@@ -1418,8 +1418,8 @@ define void @truncstore_nxv8f64_nxv8f32(<vscale x 8 x double> %x, <vscale x 8 x
; CHECK-LABEL: truncstore_nxv8f64_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 8 x double> %x to <vscale x 8 x float>
store <vscale x 8 x float> %y, <vscale x 8 x float>* %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
index 79c1b7781aff9..8da02c3333d6d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
@@ -409,9 +409,9 @@ define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_2(<vscale x 64 x i1> %mask) {
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%c = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 2)
ret <vscale x 2 x i1> %c
@@ -429,14 +429,14 @@ define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_4(<vscale x 32 x i1> %x) {
; CHECK-LABEL: extract_nxv4i1_nxv32i1_4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v28, a0
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%c = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 4)
ret <vscale x 4 x i1> %c
@@ -480,15 +480,15 @@ define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v10, a0
-; CHECK-NEXT: vslidedown.vx v26, v9, a0
+; CHECK-NEXT: vslidedown.vx v14, v10, a0
+; CHECK-NEXT: vslidedown.vx v12, v9, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v27, v25, 0
+; CHECK-NEXT: vslideup.vi v13, v14, 0
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v27, v25, a0
-; CHECK-NEXT: vslideup.vx v26, v10, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslideup.vx v13, v8, a0
+; CHECK-NEXT: vslideup.vx v12, v10, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
ret <vscale x 6 x half> %res
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
index 91bbcf015143f..de46a2d53bc34 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
@@ -16,8 +16,8 @@ define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
; CHECK-LABEL: extractelt_nxv1f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 2
ret half %r
@@ -27,8 +27,8 @@ define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 %idx
ret half %r
@@ -48,8 +48,8 @@ define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
; CHECK-LABEL: extractelt_nxv2f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 2
ret half %r
@@ -59,8 +59,8 @@ define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 %idx
ret half %r
@@ -80,8 +80,8 @@ define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
; CHECK-LABEL: extractelt_nxv4f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 2
ret half %r
@@ -91,8 +91,8 @@ define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 %idx
ret half %r
@@ -112,8 +112,8 @@ define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
; CHECK-LABEL: extractelt_nxv8f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 2
ret half %r
@@ -123,8 +123,8 @@ define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv8f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 %idx
ret half %r
@@ -144,8 +144,8 @@ define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
; CHECK-LABEL: extractelt_nxv16f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 2
ret half %r
@@ -155,8 +155,8 @@ define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv16f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 %idx
ret half %r
@@ -208,8 +208,8 @@ define float @extractelt_nxv1f32_imm(<vscale x 1 x float> %v) {
; CHECK-LABEL: extractelt_nxv1f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x float> %v, i32 2
ret float %r
@@ -219,8 +219,8 @@ define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x float> %v, i32 %idx
ret float %r
@@ -240,8 +240,8 @@ define float @extractelt_nxv2f32_imm(<vscale x 2 x float> %v) {
; CHECK-LABEL: extractelt_nxv2f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x float> %v, i32 2
ret float %r
@@ -251,8 +251,8 @@ define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x float> %v, i32 %idx
ret float %r
@@ -272,8 +272,8 @@ define float @extractelt_nxv4f32_imm(<vscale x 4 x float> %v) {
; CHECK-LABEL: extractelt_nxv4f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x float> %v, i32 2
ret float %r
@@ -283,8 +283,8 @@ define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x float> %v, i32 %idx
ret float %r
@@ -304,8 +304,8 @@ define float @extractelt_nxv8f32_imm(<vscale x 8 x float> %v) {
; CHECK-LABEL: extractelt_nxv8f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x float> %v, i32 2
ret float %r
@@ -315,8 +315,8 @@ define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv8f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x float> %v, i32 %idx
ret float %r
@@ -368,8 +368,8 @@ define double @extractelt_nxv1f64_imm(<vscale x 1 x double> %v) {
; CHECK-LABEL: extractelt_nxv1f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x double> %v, i32 2
ret double %r
@@ -379,8 +379,8 @@ define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x double> %v, i32 %idx
ret double %r
@@ -400,8 +400,8 @@ define double @extractelt_nxv2f64_imm(<vscale x 2 x double> %v) {
; CHECK-LABEL: extractelt_nxv2f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x double> %v, i32 2
ret double %r
@@ -411,8 +411,8 @@ define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x double> %v, i32 %idx
ret double %r
@@ -432,8 +432,8 @@ define double @extractelt_nxv4f64_imm(<vscale x 4 x double> %v) {
; CHECK-LABEL: extractelt_nxv4f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x double> %v, i32 2
ret double %r
@@ -443,8 +443,8 @@ define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x double> %v, i32 %idx
ret double %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
index 0fa1f18624d48..935a12f81b460 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
@@ -16,8 +16,8 @@ define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
; CHECK-LABEL: extractelt_nxv1f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 2
ret half %r
@@ -27,8 +27,8 @@ define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv1f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 %idx
ret half %r
@@ -48,8 +48,8 @@ define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
; CHECK-LABEL: extractelt_nxv2f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 2
ret half %r
@@ -59,8 +59,8 @@ define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv2f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 %idx
ret half %r
@@ -80,8 +80,8 @@ define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
; CHECK-LABEL: extractelt_nxv4f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 2
ret half %r
@@ -91,8 +91,8 @@ define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv4f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 %idx
ret half %r
@@ -112,8 +112,8 @@ define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
; CHECK-LABEL: extractelt_nxv8f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 2
ret half %r
@@ -123,8 +123,8 @@ define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv8f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 %idx
ret half %r
@@ -144,8 +144,8 @@ define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
; CHECK-LABEL: extractelt_nxv16f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 2
ret half %r
@@ -155,8 +155,8 @@ define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv16f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 %idx
ret half %r
@@ -208,8 +208,8 @@ define float @extractelt_nxv1f32_imm(<vscale x 1 x float> %v) {
; CHECK-LABEL: extractelt_nxv1f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x float> %v, i32 2
ret float %r
@@ -219,8 +219,8 @@ define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv1f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x float> %v, i32 %idx
ret float %r
@@ -240,8 +240,8 @@ define float @extractelt_nxv2f32_imm(<vscale x 2 x float> %v) {
; CHECK-LABEL: extractelt_nxv2f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x float> %v, i32 2
ret float %r
@@ -251,8 +251,8 @@ define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv2f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x float> %v, i32 %idx
ret float %r
@@ -272,8 +272,8 @@ define float @extractelt_nxv4f32_imm(<vscale x 4 x float> %v) {
; CHECK-LABEL: extractelt_nxv4f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x float> %v, i32 2
ret float %r
@@ -283,8 +283,8 @@ define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv4f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x float> %v, i32 %idx
ret float %r
@@ -304,8 +304,8 @@ define float @extractelt_nxv8f32_imm(<vscale x 8 x float> %v) {
; CHECK-LABEL: extractelt_nxv8f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x float> %v, i32 2
ret float %r
@@ -315,8 +315,8 @@ define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv8f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x float> %v, i32 %idx
ret float %r
@@ -368,8 +368,8 @@ define double @extractelt_nxv1f64_imm(<vscale x 1 x double> %v) {
; CHECK-LABEL: extractelt_nxv1f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x double> %v, i32 2
ret double %r
@@ -379,8 +379,8 @@ define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 signext %idx
; CHECK-LABEL: extractelt_nxv1f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x double> %v, i32 %idx
ret double %r
@@ -400,8 +400,8 @@ define double @extractelt_nxv2f64_imm(<vscale x 2 x double> %v) {
; CHECK-LABEL: extractelt_nxv2f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x double> %v, i32 2
ret double %r
@@ -411,8 +411,8 @@ define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 signext %idx
; CHECK-LABEL: extractelt_nxv2f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x double> %v, i32 %idx
ret double %r
@@ -432,8 +432,8 @@ define double @extractelt_nxv4f64_imm(<vscale x 4 x double> %v) {
; CHECK-LABEL: extractelt_nxv4f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x double> %v, i32 2
ret double %r
@@ -443,8 +443,8 @@ define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 signext %idx
; CHECK-LABEL: extractelt_nxv4f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vfmv.f.s fa0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x double> %v, i32 %idx
ret double %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
index 7e48f1c15df87..27d609e6f8a7c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
@@ -6,13 +6,13 @@ define i1 @extractelt_nxv1i1(<vscale x 1 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <vscale x 1 x i8>, <vscale x 1 x i8>* %x
%b = icmp eq <vscale x 1 x i8> %a, zeroinitializer
@@ -24,13 +24,13 @@ define i1 @extractelt_nxv2i1(<vscale x 2 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <vscale x 2 x i8>, <vscale x 2 x i8>* %x
%b = icmp eq <vscale x 2 x i8> %a, zeroinitializer
@@ -42,13 +42,13 @@ define i1 @extractelt_nxv4i1(<vscale x 4 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <vscale x 4 x i8>, <vscale x 4 x i8>* %x
%b = icmp eq <vscale x 4 x i8> %a, zeroinitializer
@@ -59,14 +59,14 @@ define i1 @extractelt_nxv4i1(<vscale x 4 x i8>* %x, i64 %idx) nounwind {
define i1 @extractelt_nxv8i1(<vscale x 8 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_nxv8i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a0)
+; CHECK-NEXT: vl1r.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <vscale x 8 x i8>, <vscale x 8 x i8>* %x
%b = icmp eq <vscale x 8 x i8> %a, zeroinitializer
@@ -77,14 +77,14 @@ define i1 @extractelt_nxv8i1(<vscale x 8 x i8>* %x, i64 %idx) nounwind {
define i1 @extractelt_nxv16i1(<vscale x 16 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_nxv16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2r.v v26, (a0)
+; CHECK-NEXT: vl2r.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <vscale x 16 x i8>, <vscale x 16 x i8>* %x
%b = icmp eq <vscale x 16 x i8> %a, zeroinitializer
@@ -95,14 +95,14 @@ define i1 @extractelt_nxv16i1(<vscale x 16 x i8>* %x, i64 %idx) nounwind {
define i1 @extractelt_nxv32i1(<vscale x 32 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_nxv32i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v28, a1
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <vscale x 32 x i8>, <vscale x 32 x i8>* %x
%b = icmp eq <vscale x 32 x i8> %a, zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
index 70e742ebd5605..31f3c3004b191 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
@@ -16,8 +16,8 @@ define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
; CHECK-LABEL: extractelt_nxv1i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i8> %v, i32 2
ret i8 %r
@@ -27,8 +27,8 @@ define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i8> %v, i32 %idx
ret i8 %r
@@ -48,8 +48,8 @@ define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
; CHECK-LABEL: extractelt_nxv2i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i8> %v, i32 2
ret i8 %r
@@ -59,8 +59,8 @@ define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i8> %v, i32 %idx
ret i8 %r
@@ -80,8 +80,8 @@ define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
; CHECK-LABEL: extractelt_nxv4i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i8> %v, i32 2
ret i8 %r
@@ -91,8 +91,8 @@ define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i8> %v, i32 %idx
ret i8 %r
@@ -112,8 +112,8 @@ define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
; CHECK-LABEL: extractelt_nxv8i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i8> %v, i32 2
ret i8 %r
@@ -123,8 +123,8 @@ define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv8i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i8> %v, i32 %idx
ret i8 %r
@@ -144,8 +144,8 @@ define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
; CHECK-LABEL: extractelt_nxv16i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i8> %v, i32 2
ret i8 %r
@@ -155,8 +155,8 @@ define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv16i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i8> %v, i32 %idx
ret i8 %r
@@ -176,8 +176,8 @@ define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
; CHECK-LABEL: extractelt_nxv32i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i8> %v, i32 2
ret i8 %r
@@ -187,8 +187,8 @@ define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv32i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i8> %v, i32 %idx
ret i8 %r
@@ -240,8 +240,8 @@ define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
; CHECK-LABEL: extractelt_nxv1i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i16> %v, i32 2
ret i16 %r
@@ -251,8 +251,8 @@ define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i16> %v, i32 %idx
ret i16 %r
@@ -272,8 +272,8 @@ define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
; CHECK-LABEL: extractelt_nxv2i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i16> %v, i32 2
ret i16 %r
@@ -283,8 +283,8 @@ define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i16> %v, i32 %idx
ret i16 %r
@@ -304,8 +304,8 @@ define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
; CHECK-LABEL: extractelt_nxv4i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i16> %v, i32 2
ret i16 %r
@@ -315,8 +315,8 @@ define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i16> %v, i32 %idx
ret i16 %r
@@ -336,8 +336,8 @@ define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
; CHECK-LABEL: extractelt_nxv8i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i16> %v, i32 2
ret i16 %r
@@ -347,8 +347,8 @@ define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv8i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i16> %v, i32 %idx
ret i16 %r
@@ -368,8 +368,8 @@ define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
; CHECK-LABEL: extractelt_nxv16i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i16> %v, i32 2
ret i16 %r
@@ -379,8 +379,8 @@ define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv16i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i16> %v, i32 %idx
ret i16 %r
@@ -432,8 +432,8 @@ define i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {
; CHECK-LABEL: extractelt_nxv1i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i32> %v, i32 2
ret i32 %r
@@ -443,8 +443,8 @@ define i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i32> %v, i32 %idx
ret i32 %r
@@ -464,8 +464,8 @@ define i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {
; CHECK-LABEL: extractelt_nxv2i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i32> %v, i32 2
ret i32 %r
@@ -475,8 +475,8 @@ define i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i32> %v, i32 %idx
ret i32 %r
@@ -496,8 +496,8 @@ define i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {
; CHECK-LABEL: extractelt_nxv4i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i32> %v, i32 2
ret i32 %r
@@ -507,8 +507,8 @@ define i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i32> %v, i32 %idx
ret i32 %r
@@ -528,8 +528,8 @@ define i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {
; CHECK-LABEL: extractelt_nxv8i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i32> %v, i32 2
ret i32 %r
@@ -539,8 +539,8 @@ define i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv8i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i32> %v, i32 %idx
ret i32 %r
@@ -583,8 +583,8 @@ define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v9, v8, a0
+; CHECK-NEXT: vmv.x.s a1, v9
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i64> %v, i32 0
@@ -595,11 +595,11 @@ define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {
; CHECK-LABEL: extractelt_nxv1i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i64> %v, i32 2
ret i64 %r
@@ -609,11 +609,11 @@ define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i64> %v, i32 %idx
ret i64 %r
@@ -624,8 +624,8 @@ define i64 @extractelt_nxv2i64_0(<vscale x 2 x i64> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vsrl.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a1, v26
+; CHECK-NEXT: vsrl.vx v10, v8, a0
+; CHECK-NEXT: vmv.x.s a1, v10
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i64> %v, i32 0
@@ -636,11 +636,11 @@ define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {
; CHECK-LABEL: extractelt_nxv2i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
-; CHECK-NEXT: vsrl.vx v26, v26, a1
-; CHECK-NEXT: vmv.x.s a1, v26
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i64> %v, i32 2
ret i64 %r
@@ -650,11 +650,11 @@ define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
-; CHECK-NEXT: vsrl.vx v26, v26, a1
-; CHECK-NEXT: vmv.x.s a1, v26
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i64> %v, i32 %idx
ret i64 %r
@@ -665,8 +665,8 @@ define i64 @extractelt_nxv4i64_0(<vscale x 4 x i64> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vsrl.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a1, v28
+; CHECK-NEXT: vsrl.vx v12, v8, a0
+; CHECK-NEXT: vmv.x.s a1, v12
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i64> %v, i32 0
@@ -677,11 +677,11 @@ define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {
; CHECK-LABEL: extractelt_nxv4i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
-; CHECK-NEXT: vsrl.vx v28, v28, a1
-; CHECK-NEXT: vmv.x.s a1, v28
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i64> %v, i32 2
ret i64 %r
@@ -691,11 +691,11 @@ define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
-; CHECK-NEXT: vsrl.vx v28, v28, a1
-; CHECK-NEXT: vmv.x.s a1, v28
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i64> %v, i32 %idx
ret i64 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
index 1c9ee97f3cd03..1d4983f280f37 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
@@ -16,8 +16,8 @@ define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
; CHECK-LABEL: extractelt_nxv1i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i8> %v, i32 2
ret i8 %r
@@ -27,8 +27,8 @@ define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv1i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i8> %v, i32 %idx
ret i8 %r
@@ -48,8 +48,8 @@ define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
; CHECK-LABEL: extractelt_nxv2i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i8> %v, i32 2
ret i8 %r
@@ -59,8 +59,8 @@ define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv2i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i8> %v, i32 %idx
ret i8 %r
@@ -80,8 +80,8 @@ define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
; CHECK-LABEL: extractelt_nxv4i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i8> %v, i32 2
ret i8 %r
@@ -91,8 +91,8 @@ define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv4i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i8> %v, i32 %idx
ret i8 %r
@@ -112,8 +112,8 @@ define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
; CHECK-LABEL: extractelt_nxv8i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i8> %v, i32 2
ret i8 %r
@@ -123,8 +123,8 @@ define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 signext %idx)
; CHECK-LABEL: extractelt_nxv8i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i8> %v, i32 %idx
ret i8 %r
@@ -144,8 +144,8 @@ define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
; CHECK-LABEL: extractelt_nxv16i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i8> %v, i32 2
ret i8 %r
@@ -155,8 +155,8 @@ define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 signext %id
; CHECK-LABEL: extractelt_nxv16i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i8> %v, i32 %idx
ret i8 %r
@@ -176,8 +176,8 @@ define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
; CHECK-LABEL: extractelt_nxv32i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i8> %v, i32 2
ret i8 %r
@@ -187,8 +187,8 @@ define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 signext %id
; CHECK-LABEL: extractelt_nxv32i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i8> %v, i32 %idx
ret i8 %r
@@ -240,8 +240,8 @@ define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
; CHECK-LABEL: extractelt_nxv1i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i16> %v, i32 2
ret i16 %r
@@ -251,8 +251,8 @@ define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv1i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i16> %v, i32 %idx
ret i16 %r
@@ -272,8 +272,8 @@ define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
; CHECK-LABEL: extractelt_nxv2i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i16> %v, i32 2
ret i16 %r
@@ -283,8 +283,8 @@ define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv2i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i16> %v, i32 %idx
ret i16 %r
@@ -304,8 +304,8 @@ define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
; CHECK-LABEL: extractelt_nxv4i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i16> %v, i32 2
ret i16 %r
@@ -315,8 +315,8 @@ define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv4i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i16> %v, i32 %idx
ret i16 %r
@@ -336,8 +336,8 @@ define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
; CHECK-LABEL: extractelt_nxv8i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i16> %v, i32 2
ret i16 %r
@@ -347,8 +347,8 @@ define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv8i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i16> %v, i32 %idx
ret i16 %r
@@ -368,8 +368,8 @@ define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
; CHECK-LABEL: extractelt_nxv16i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i16> %v, i32 2
ret i16 %r
@@ -379,8 +379,8 @@ define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 signext
; CHECK-LABEL: extractelt_nxv16i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i16> %v, i32 %idx
ret i16 %r
@@ -432,8 +432,8 @@ define signext i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {
; CHECK-LABEL: extractelt_nxv1i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i32> %v, i32 2
ret i32 %r
@@ -443,8 +443,8 @@ define signext i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv1i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i32> %v, i32 %idx
ret i32 %r
@@ -464,8 +464,8 @@ define signext i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {
; CHECK-LABEL: extractelt_nxv2i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i32> %v, i32 2
ret i32 %r
@@ -475,8 +475,8 @@ define signext i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv2i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i32> %v, i32 %idx
ret i32 %r
@@ -496,8 +496,8 @@ define signext i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {
; CHECK-LABEL: extractelt_nxv4i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i32> %v, i32 2
ret i32 %r
@@ -507,8 +507,8 @@ define signext i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv4i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i32> %v, i32 %idx
ret i32 %r
@@ -528,8 +528,8 @@ define signext i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {
; CHECK-LABEL: extractelt_nxv8i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i32> %v, i32 2
ret i32 %r
@@ -539,8 +539,8 @@ define signext i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %i
; CHECK-LABEL: extractelt_nxv8i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i32> %v, i32 %idx
ret i32 %r
@@ -592,8 +592,8 @@ define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {
; CHECK-LABEL: extractelt_nxv1i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i64> %v, i32 2
ret i64 %r
@@ -603,8 +603,8 @@ define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv1i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i64> %v, i32 %idx
ret i64 %r
@@ -624,8 +624,8 @@ define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {
; CHECK-LABEL: extractelt_nxv2i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i64> %v, i32 2
ret i64 %r
@@ -635,8 +635,8 @@ define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv2i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i64> %v, i32 %idx
ret i64 %r
@@ -656,8 +656,8 @@ define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {
; CHECK-LABEL: extractelt_nxv4i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v8, 2
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i64> %v, i32 2
ret i64 %r
@@ -667,8 +667,8 @@ define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv4i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i64> %v, i32 %idx
ret i64 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
index 9d8da31c6d925..33c68c1a88215 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
@@ -38,11 +38,11 @@ define void @gather(i8* noalias nocapture %A, i8* noalias nocapture readonly %B)
; CHECK-ASM-NEXT: .LBB0_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vlse8.v v25, (a1), a4
+; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4
; CHECK-ASM-NEXT: add a3, a0, a2
-; CHECK-ASM-NEXT: vle8.v v26, (a3)
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vse8.v v25, (a3)
+; CHECK-ASM-NEXT: vle8.v v9, (a3)
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vse8.v v8, (a3)
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB0_1
@@ -107,12 +107,12 @@ define void @gather_masked(i8* noalias nocapture %A, i8* noalias nocapture reado
; CHECK-ASM-NEXT: .LBB1_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vmv1r.v v25, v8
-; CHECK-ASM-NEXT: vlse8.v v25, (a1), a4, v0.t
+; CHECK-ASM-NEXT: vmv1r.v v9, v8
+; CHECK-ASM-NEXT: vlse8.v v9, (a1), a4, v0.t
; CHECK-ASM-NEXT: add a3, a0, a2
-; CHECK-ASM-NEXT: vle8.v v26, (a3)
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vse8.v v25, (a3)
+; CHECK-ASM-NEXT: vle8.v v10, (a3)
+; CHECK-ASM-NEXT: vadd.vv v9, v10, v9
+; CHECK-ASM-NEXT: vse8.v v9, (a3)
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB1_1
@@ -174,11 +174,11 @@ define void @gather_negative_stride(i8* noalias nocapture %A, i8* noalias nocapt
; CHECK-ASM-NEXT: .LBB2_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vlse8.v v25, (a1), a4
+; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4
; CHECK-ASM-NEXT: add a3, a0, a2
-; CHECK-ASM-NEXT: vle8.v v26, (a3)
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vse8.v v25, (a3)
+; CHECK-ASM-NEXT: vle8.v v9, (a3)
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vse8.v v8, (a3)
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB2_1
@@ -238,11 +238,11 @@ define void @gather_zero_stride(i8* noalias nocapture %A, i8* noalias nocapture
; CHECK-ASM-NEXT: .LBB3_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vlse8.v v25, (a1), zero
+; CHECK-ASM-NEXT: vlse8.v v8, (a1), zero
; CHECK-ASM-NEXT: add a5, a0, a2
-; CHECK-ASM-NEXT: vle8.v v26, (a5)
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vse8.v v25, (a5)
+; CHECK-ASM-NEXT: vle8.v v9, (a5)
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vse8.v v8, (a5)
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a4, .LBB3_1
@@ -310,10 +310,10 @@ define void @scatter(i8* noalias nocapture %A, i8* noalias nocapture readonly %B
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: add a3, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vle8.v v25, (a3)
-; CHECK-ASM-NEXT: vlse8.v v26, (a0), a4
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vsse8.v v25, (a0), a4
+; CHECK-ASM-NEXT: vle8.v v8, (a3)
+; CHECK-ASM-NEXT: vlse8.v v9, (a0), a4
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vsse8.v v8, (a0), a4
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a0, a0, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB4_1
@@ -380,11 +380,11 @@ define void @scatter_masked(i8* noalias nocapture %A, i8* noalias nocapture read
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: add a3, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vle8.v v25, (a3)
-; CHECK-ASM-NEXT: vmv1r.v v26, v8
-; CHECK-ASM-NEXT: vlse8.v v26, (a0), a4, v0.t
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vsse8.v v25, (a0), a4, v0.t
+; CHECK-ASM-NEXT: vle8.v v9, (a3)
+; CHECK-ASM-NEXT: vmv1r.v v10, v8
+; CHECK-ASM-NEXT: vlse8.v v10, (a0), a4, v0.t
+; CHECK-ASM-NEXT: vadd.vv v9, v10, v9
+; CHECK-ASM-NEXT: vsse8.v v9, (a0), a4, v0.t
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a0, a0, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB5_1
@@ -448,13 +448,13 @@ define void @gather_pow2(i32* noalias nocapture %A, i32* noalias nocapture reado
; CHECK-ASM-NEXT: .LBB6_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; CHECK-ASM-NEXT: vlse32.v v25, (a1), a3
+; CHECK-ASM-NEXT: vlse32.v v8, (a1), a3
; CHECK-ASM-NEXT: vsetvli zero, a4, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vle8.v v26, (a0)
+; CHECK-ASM-NEXT: vle8.v v9, (a0)
; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vsetvli zero, a4, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vse8.v v25, (a0)
+; CHECK-ASM-NEXT: vse8.v v8, (a0)
; CHECK-ASM-NEXT: addi a2, a2, -8
; CHECK-ASM-NEXT: addi a0, a0, 32
; CHECK-ASM-NEXT: addi a1, a1, 128
@@ -523,11 +523,11 @@ define void @scatter_pow2(i32* noalias nocapture %A, i32* noalias nocapture read
; CHECK-ASM-NEXT: .LBB7_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
-; CHECK-ASM-NEXT: vle8.v v25, (a1)
+; CHECK-ASM-NEXT: vle8.v v8, (a1)
; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; CHECK-ASM-NEXT: vlse32.v v26, (a0), a4
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vsse32.v v25, (a0), a4
+; CHECK-ASM-NEXT: vlse32.v v9, (a0), a4
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vsse32.v v8, (a0), a4
; CHECK-ASM-NEXT: addi a2, a2, -8
; CHECK-ASM-NEXT: addi a1, a1, 32
; CHECK-ASM-NEXT: addi a0, a0, 128
@@ -609,15 +609,15 @@ define void @struct_gather(i32* noalias nocapture %A, %struct.foo* noalias nocap
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: addi a4, a1, -128
; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; CHECK-ASM-NEXT: vlse32.v v25, (a4), a3
-; CHECK-ASM-NEXT: vlse32.v v26, (a1), a3
+; CHECK-ASM-NEXT: vlse32.v v8, (a4), a3
+; CHECK-ASM-NEXT: vlse32.v v9, (a1), a3
; CHECK-ASM-NEXT: addi a4, a0, -32
-; CHECK-ASM-NEXT: vle32.v v27, (a4)
-; CHECK-ASM-NEXT: vle32.v v28, (a0)
-; CHECK-ASM-NEXT: vadd.vv v25, v27, v25
-; CHECK-ASM-NEXT: vadd.vv v26, v28, v26
-; CHECK-ASM-NEXT: vse32.v v25, (a4)
-; CHECK-ASM-NEXT: vse32.v v26, (a0)
+; CHECK-ASM-NEXT: vle32.v v10, (a4)
+; CHECK-ASM-NEXT: vle32.v v11, (a0)
+; CHECK-ASM-NEXT: vadd.vv v8, v10, v8
+; CHECK-ASM-NEXT: vadd.vv v9, v11, v9
+; CHECK-ASM-NEXT: vse32.v v8, (a4)
+; CHECK-ASM-NEXT: vse32.v v9, (a0)
; CHECK-ASM-NEXT: addi a2, a2, -16
; CHECK-ASM-NEXT: addi a0, a0, 64
; CHECK-ASM-NEXT: addi a1, a1, 256
@@ -748,28 +748,28 @@ define void @gather_unroll(i32* noalias nocapture %A, i32* noalias nocapture rea
; CHECK-ASM-NEXT: .LBB9_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; CHECK-ASM-NEXT: vlse32.v v25, (a1), a3
-; CHECK-ASM-NEXT: vlse32.v v26, (a0), a4
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vsse32.v v25, (a0), a4
+; CHECK-ASM-NEXT: vlse32.v v8, (a1), a3
+; CHECK-ASM-NEXT: vlse32.v v9, (a0), a4
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vsse32.v v8, (a0), a4
; CHECK-ASM-NEXT: addi a5, a1, 16
-; CHECK-ASM-NEXT: vlse32.v v25, (a5), a3
+; CHECK-ASM-NEXT: vlse32.v v8, (a5), a3
; CHECK-ASM-NEXT: addi a5, a0, 4
-; CHECK-ASM-NEXT: vlse32.v v26, (a5), a4
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vsse32.v v25, (a5), a4
+; CHECK-ASM-NEXT: vlse32.v v9, (a5), a4
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vsse32.v v8, (a5), a4
; CHECK-ASM-NEXT: addi a5, a1, 32
-; CHECK-ASM-NEXT: vlse32.v v25, (a5), a3
+; CHECK-ASM-NEXT: vlse32.v v8, (a5), a3
; CHECK-ASM-NEXT: addi a5, a0, 8
-; CHECK-ASM-NEXT: vlse32.v v26, (a5), a4
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vsse32.v v25, (a5), a4
+; CHECK-ASM-NEXT: vlse32.v v9, (a5), a4
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vsse32.v v8, (a5), a4
; CHECK-ASM-NEXT: addi a5, a1, 48
-; CHECK-ASM-NEXT: vlse32.v v25, (a5), a3
+; CHECK-ASM-NEXT: vlse32.v v8, (a5), a3
; CHECK-ASM-NEXT: addi a5, a0, 12
-; CHECK-ASM-NEXT: vlse32.v v26, (a5), a4
-; CHECK-ASM-NEXT: vadd.vv v25, v26, v25
-; CHECK-ASM-NEXT: vsse32.v v25, (a5), a4
+; CHECK-ASM-NEXT: vlse32.v v9, (a5), a4
+; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
+; CHECK-ASM-NEXT: vsse32.v v8, (a5), a4
; CHECK-ASM-NEXT: addi a2, a2, -8
; CHECK-ASM-NEXT: addi a1, a1, 512
; CHECK-ASM-NEXT: addi a0, a0, 128
@@ -863,11 +863,11 @@ define void @gather_of_pointers(i32** noalias nocapture %0, i32** noalias nocapt
; CHECK-ASM-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: addi a4, a1, 80
; CHECK-ASM-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-ASM-NEXT: vlse64.v v25, (a1), a3
-; CHECK-ASM-NEXT: vlse64.v v26, (a4), a3
+; CHECK-ASM-NEXT: vlse64.v v8, (a1), a3
+; CHECK-ASM-NEXT: vlse64.v v9, (a4), a3
; CHECK-ASM-NEXT: addi a4, a0, -16
-; CHECK-ASM-NEXT: vse64.v v25, (a4)
-; CHECK-ASM-NEXT: vse64.v v26, (a0)
+; CHECK-ASM-NEXT: vse64.v v8, (a4)
+; CHECK-ASM-NEXT: vse64.v v9, (a0)
; CHECK-ASM-NEXT: addi a2, a2, -4
; CHECK-ASM-NEXT: addi a0, a0, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
@@ -939,11 +939,11 @@ define void @scatter_of_pointers(i32** noalias nocapture %0, i32** noalias nocap
; CHECK-ASM-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: addi a4, a1, -16
; CHECK-ASM-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-ASM-NEXT: vle64.v v25, (a4)
-; CHECK-ASM-NEXT: vle64.v v26, (a1)
+; CHECK-ASM-NEXT: vle64.v v8, (a4)
+; CHECK-ASM-NEXT: vle64.v v9, (a1)
; CHECK-ASM-NEXT: addi a4, a0, 80
-; CHECK-ASM-NEXT: vsse64.v v25, (a0), a3
-; CHECK-ASM-NEXT: vsse64.v v26, (a4), a3
+; CHECK-ASM-NEXT: vsse64.v v8, (a0), a3
+; CHECK-ASM-NEXT: vsse64.v v9, (a4), a3
; CHECK-ASM-NEXT: addi a2, a2, -4
; CHECK-ASM-NEXT: addi a1, a1, 32
; CHECK-ASM-NEXT: addi a0, a0, 160
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
index f3b380bafd1ba..ce06f8faf4c34 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
@@ -8,10 +8,10 @@ define void @abs_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: abs_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v26, v25, 0
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false)
@@ -24,10 +24,10 @@ define void @abs_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: abs_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v26, v25, 0
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false)
@@ -40,10 +40,10 @@ define void @abs_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: abs_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v26, v25, 0
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false)
@@ -56,10 +56,10 @@ define void @abs_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: abs_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v26, v25, 0
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v9, v8, 0
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 false)
@@ -73,38 +73,38 @@ define void @abs_v32i8(<32 x i8>* %x) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: abs_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: abs_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 false)
@@ -117,38 +117,38 @@ define void @abs_v16i16(<16 x i16>* %x) {
; LMULMAX2-LABEL: abs_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: abs_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: abs_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 false)
@@ -161,38 +161,38 @@ define void @abs_v8i32(<8 x i32>* %x) {
; LMULMAX2-LABEL: abs_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: abs_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: abs_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false)
@@ -205,38 +205,38 @@ define void @abs_v4i64(<4 x i64>* %x) {
; LMULMAX2-LABEL: abs_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: abs_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: abs_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 false)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
index b0a46cfaa8567..6d24d0b440574 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
@@ -79,8 +79,8 @@ define i64 @bitcast_v8i8_i64(<8 x i8> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -98,8 +98,8 @@ define i64 @bitcast_v4i16_i64(<4 x i16> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -117,8 +117,8 @@ define i64 @bitcast_v2i32_i64(<2 x i32> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -136,8 +136,8 @@ define i64 @bitcast_v1i64_i64(<1 x i64> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -205,8 +205,8 @@ define double @bitcast_v8i8_f64(<8 x i8> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -224,8 +224,8 @@ define double @bitcast_v4i16_f64(<4 x i16> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -243,8 +243,8 @@ define double @bitcast_v2i32_f64(<2 x i32> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -262,8 +262,8 @@ define double @bitcast_v1i64_f64(<1 x i64> %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v8, a0
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
@@ -322,11 +322,11 @@ define <4 x i16> @bitcast_i64_v4i16(i64 %a) {
; RV32-LABEL: bitcast_i64_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vslide1up.vx v26, v25, a1
-; RV32-NEXT: vslide1up.vx v25, v26, a0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vslide1up.vx v9, v8, a1
+; RV32-NEXT: vslide1up.vx v10, v9, a0
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vslideup.vi v8, v25, 0
+; RV32-NEXT: vslideup.vi v8, v10, 0
; RV32-NEXT: ret
;
; RV64-LABEL: bitcast_i64_v4i16:
@@ -342,11 +342,11 @@ define <2 x i32> @bitcast_i64_v2i32(i64 %a) {
; RV32-LABEL: bitcast_i64_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vslide1up.vx v26, v25, a1
-; RV32-NEXT: vslide1up.vx v25, v26, a0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vslide1up.vx v9, v8, a1
+; RV32-NEXT: vslide1up.vx v10, v9, a0
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vslideup.vi v8, v25, 0
+; RV32-NEXT: vslideup.vi v8, v10, 0
; RV32-NEXT: ret
;
; RV64-LABEL: bitcast_i64_v2i32:
@@ -362,11 +362,11 @@ define <1 x i64> @bitcast_i64_v1i64(i64 %a) {
; RV32-LABEL: bitcast_i64_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vslide1up.vx v26, v25, a1
-; RV32-NEXT: vslide1up.vx v25, v26, a0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vslide1up.vx v9, v8, a1
+; RV32-NEXT: vslide1up.vx v10, v9, a0
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vslideup.vi v8, v25, 0
+; RV32-NEXT: vslideup.vi v8, v10, 0
; RV32-NEXT: ret
;
; RV64-LABEL: bitcast_i64_v1i64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
index c857165debd1f..ca0b59eb2672d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
@@ -8,125 +8,125 @@ define void @bitreverse_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-LABEL: bitreverse_v8i16:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 8
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 8
-; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 8
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v9
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 1
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX2-RV32-NEXT: lui a1, 3
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 5
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: bitreverse_v8i16:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 8
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 8
-; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 8
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v9
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 1
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 3
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 5
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: bitreverse_v8i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 8
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 8
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 8
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV32-NEXT: lui a1, 1
; LMULMAX1-RV32-NEXT: addi a1, a1, -241
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV32-NEXT: lui a1, 3
; LMULMAX1-RV32-NEXT: addi a1, a1, 819
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: lui a1, 5
; LMULMAX1-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: bitreverse_v8i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 8
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 8
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 8
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV64-NEXT: lui a1, 1
; LMULMAX1-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV64-NEXT: lui a1, 3
; LMULMAX1-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV64-NEXT: lui a1, 5
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -140,161 +140,161 @@ define void @bitreverse_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-LABEL: bitreverse_v4i32:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 8
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v27, v25, 24
-; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX2-RV32-NEXT: vsll.vi v27, v25, 8
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 24
+; LMULMAX2-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX2-RV32-NEXT: vsll.vi v10, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 4080
-; LMULMAX2-RV32-NEXT: vand.vx v27, v27, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 24
-; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v27
-; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v9
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: bitreverse_v4i32:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 8
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v27, v25, 24
-; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v27
-; LMULMAX2-RV64-NEXT: vsll.vi v27, v25, 8
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 24
+; LMULMAX2-RV64-NEXT: vor.vv v9, v9, v10
+; LMULMAX2-RV64-NEXT: vsll.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 4080
-; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 24
-; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v27
-; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v9
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 61681
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 209715
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 349525
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: bitreverse_v4i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 8
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 8
; LMULMAX1-RV32-NEXT: lui a1, 16
; LMULMAX1-RV32-NEXT: addi a1, a1, -256
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 24
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsll.vi v27, v25, 8
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 24
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsll.vi v10, v8, 8
; LMULMAX1-RV32-NEXT: lui a1, 4080
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a1
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 24
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV32-NEXT: lui a1, 61681
; LMULMAX1-RV32-NEXT: addi a1, a1, -241
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV32-NEXT: lui a1, 209715
; LMULMAX1-RV32-NEXT: addi a1, a1, 819
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: lui a1, 349525
; LMULMAX1-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: bitreverse_v4i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 8
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 8
; LMULMAX1-RV64-NEXT: lui a1, 16
; LMULMAX1-RV64-NEXT: addiw a1, a1, -256
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 24
-; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vsll.vi v27, v25, 8
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 24
+; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vsll.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a1, 4080
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a1
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 24
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV64-NEXT: lui a1, 61681
; LMULMAX1-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV64-NEXT: lui a1, 209715
; LMULMAX1-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV64-NEXT: lui a1, 349525
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -308,123 +308,123 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-LABEL: bitreverse_v2i64:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi a1, zero, 56
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a1
+; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a1
; LMULMAX2-RV32-NEXT: addi a2, zero, 40
-; LMULMAX2-RV32-NEXT: vsrl.vx v27, v25, a2
+; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a2
; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256
-; LMULMAX2-RV32-NEXT: vand.vx v27, v27, a3
-; LMULMAX2-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v27, v25, 24
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a3
+; LMULMAX2-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 24
; LMULMAX2-RV32-NEXT: lui a4, 4080
-; LMULMAX2-RV32-NEXT: vand.vx v27, v27, a4
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX2-RV32-NEXT: addi a5, zero, 5
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.i v28, 0
+; LMULMAX2-RV32-NEXT: vmv.v.i v11, 0
; LMULMAX2-RV32-NEXT: lui a5, 1044480
-; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a5, v0
+; LMULMAX2-RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vsrl.vi v29, v25, 8
-; LMULMAX2-RV32-NEXT: vand.vv v28, v29, v28
-; LMULMAX2-RV32-NEXT: vor.vv v27, v28, v27
-; LMULMAX2-RV32-NEXT: vor.vv v26, v27, v26
+; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 8
+; LMULMAX2-RV32-NEXT: vand.vv v11, v12, v11
+; LMULMAX2-RV32-NEXT: vor.vv v10, v11, v10
+; LMULMAX2-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX2-RV32-NEXT: addi a5, zero, 255
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v27, a5
-; LMULMAX2-RV32-NEXT: vmerge.vim v27, v27, 0, v0
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a5
+; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vsll.vi v28, v25, 8
-; LMULMAX2-RV32-NEXT: vand.vv v27, v28, v27
+; LMULMAX2-RV32-NEXT: vsll.vi v11, v8, 8
+; LMULMAX2-RV32-NEXT: vand.vv v10, v11, v10
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a3
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 0, v0
+; LMULMAX2-RV32-NEXT: vmv.v.x v11, a3
+; LMULMAX2-RV32-NEXT: vmerge.vim v11, v11, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vsll.vi v29, v25, 24
-; LMULMAX2-RV32-NEXT: vand.vv v28, v29, v28
-; LMULMAX2-RV32-NEXT: vor.vv v27, v28, v27
-; LMULMAX2-RV32-NEXT: vsll.vx v28, v25, a2
+; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 24
+; LMULMAX2-RV32-NEXT: vand.vv v11, v12, v11
+; LMULMAX2-RV32-NEXT: vor.vv v10, v11, v10
+; LMULMAX2-RV32-NEXT: vsll.vx v11, v8, a2
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v29, a4
-; LMULMAX2-RV32-NEXT: vmerge.vim v29, v29, 0, v0
+; LMULMAX2-RV32-NEXT: vmv.v.x v12, a4
+; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v29
-; LMULMAX2-RV32-NEXT: vsll.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v27
-; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX2-RV32-NEXT: vand.vv v11, v11, v12
+; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v9
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v27
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v27
-; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v27
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: bitreverse_v2i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi a1, zero, 56
-; LMULMAX2-RV64-NEXT: vsrl.vx v26, v25, a1
+; LMULMAX2-RV64-NEXT: vsrl.vx v9, v8, a1
; LMULMAX2-RV64-NEXT: addi a2, zero, 40
-; LMULMAX2-RV64-NEXT: vsrl.vx v27, v25, a2
+; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX2-RV64-NEXT: lui a3, 16
; LMULMAX2-RV64-NEXT: addiw a3, a3, -256
-; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX2-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v27, v25, 24
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX2-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 24
; LMULMAX2-RV64-NEXT: lui a3, 4080
-; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v25, 8
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX2-RV64-NEXT: vsrl.vi v11, v8, 8
; LMULMAX2-RV64-NEXT: addi a3, zero, 255
; LMULMAX2-RV64-NEXT: slli a4, a3, 24
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a4
-; LMULMAX2-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX2-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX2-RV64-NEXT: vsll.vi v27, v25, 8
+; LMULMAX2-RV64-NEXT: vand.vx v11, v11, a4
+; LMULMAX2-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX2-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX2-RV64-NEXT: vsll.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: slli a4, a3, 32
-; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX2-RV64-NEXT: vsll.vi v28, v25, 24
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX2-RV64-NEXT: vsll.vi v11, v8, 24
; LMULMAX2-RV64-NEXT: slli a4, a3, 40
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a4
-; LMULMAX2-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX2-RV64-NEXT: vsll.vx v28, v25, a1
-; LMULMAX2-RV64-NEXT: vsll.vx v25, v25, a2
+; LMULMAX2-RV64-NEXT: vand.vx v11, v11, a4
+; LMULMAX2-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX2-RV64-NEXT: vsll.vx v11, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2
; LMULMAX2-RV64-NEXT: slli a1, a3, 48
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vor.vv v25, v28, v25
-; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v27
-; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vor.vv v8, v11, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v9
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 3855
; LMULMAX2-RV64-NEXT: addiw a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -433,11 +433,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 13107
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -446,11 +446,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 21845
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -459,133 +459,133 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: bitreverse_v2i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, zero, 56
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a1
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a1
; LMULMAX1-RV32-NEXT: addi a2, zero, 40
-; LMULMAX1-RV32-NEXT: vsrl.vx v27, v25, a2
+; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: lui a3, 16
; LMULMAX1-RV32-NEXT: addi a3, a3, -256
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 24
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 24
; LMULMAX1-RV32-NEXT: lui a4, 4080
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV32-NEXT: addi a5, zero, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.i v28, 0
+; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0
; LMULMAX1-RV32-NEXT: lui a5, 1044480
-; LMULMAX1-RV32-NEXT: vmerge.vxm v28, v28, a5, v0
+; LMULMAX1-RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsrl.vi v29, v25, 8
-; LMULMAX1-RV32-NEXT: vand.vv v28, v29, v28
-; LMULMAX1-RV32-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
+; LMULMAX1-RV32-NEXT: vsrl.vi v12, v8, 8
+; LMULMAX1-RV32-NEXT: vand.vv v11, v12, v11
+; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: addi a5, zero, 255
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a5
-; LMULMAX1-RV32-NEXT: vmerge.vim v27, v27, 0, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5
+; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsll.vi v28, v25, 8
-; LMULMAX1-RV32-NEXT: vand.vv v27, v28, v27
+; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8
+; LMULMAX1-RV32-NEXT: vand.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v28, a3
-; LMULMAX1-RV32-NEXT: vmerge.vim v28, v28, 0, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v11, a3
+; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsll.vi v29, v25, 24
-; LMULMAX1-RV32-NEXT: vand.vv v28, v29, v28
-; LMULMAX1-RV32-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV32-NEXT: vsll.vx v28, v25, a2
+; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 24
+; LMULMAX1-RV32-NEXT: vand.vv v11, v12, v11
+; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV32-NEXT: vsll.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v29, a4
-; LMULMAX1-RV32-NEXT: vmerge.vim v29, v29, 0, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v12, a4
+; LMULMAX1-RV32-NEXT: vmerge.vim v12, v12, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v28, v28, v29
-; LMULMAX1-RV32-NEXT: vsll.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v12
+; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV32-NEXT: lui a1, 61681
; LMULMAX1-RV32-NEXT: addi a1, a1, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV32-NEXT: lui a1, 209715
; LMULMAX1-RV32-NEXT: addi a1, a1, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: lui a1, 349525
; LMULMAX1-RV32-NEXT: addi a1, a1, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: bitreverse_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a1, zero, 56
-; LMULMAX1-RV64-NEXT: vsrl.vx v26, v25, a1
+; LMULMAX1-RV64-NEXT: vsrl.vx v9, v8, a1
; LMULMAX1-RV64-NEXT: addi a2, zero, 40
-; LMULMAX1-RV64-NEXT: vsrl.vx v27, v25, a2
+; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: lui a3, 16
; LMULMAX1-RV64-NEXT: addiw a3, a3, -256
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 24
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 24
; LMULMAX1-RV64-NEXT: lui a3, 4080
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV64-NEXT: vsrl.vi v28, v25, 8
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: addi a3, zero, 255
; LMULMAX1-RV64-NEXT: slli a4, a3, 24
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a4
-; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsll.vi v27, v25, 8
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
+; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsll.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: slli a4, a3, 32
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV64-NEXT: vsll.vi v28, v25, 24
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: slli a4, a3, 40
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a4
-; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV64-NEXT: vsll.vx v28, v25, a1
-; LMULMAX1-RV64-NEXT: vsll.vx v25, v25, a2
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
+; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV64-NEXT: vsll.vx v11, v8, a1
+; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a2
; LMULMAX1-RV64-NEXT: slli a1, a3, 48
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vor.vv v25, v28, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vor.vv v8, v11, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV64-NEXT: lui a1, 3855
; LMULMAX1-RV64-NEXT: addiw a1, a1, 241
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
@@ -594,11 +594,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a1, a1, 241
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -241
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 2
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV64-NEXT: lui a1, 13107
; LMULMAX1-RV64-NEXT: addiw a1, a1, 819
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
@@ -607,11 +607,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a1, a1, 819
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 819
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV64-NEXT: lui a1, 21845
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
@@ -620,11 +620,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -638,167 +638,167 @@ define void @bitreverse_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-LABEL: bitreverse_v16i16:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 8
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 8
-; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 1
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 4
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 2
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV32-NEXT: lui a1, 3
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 2
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 5
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: bitreverse_v16i16:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 8
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 8
-; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 1
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 4
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 2
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 3
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 2
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 5
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: bitreverse_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 8
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 8
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: lui a2, 1
; LMULMAX1-RV32-NEXT: addi a2, a2, -241
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a2
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 2
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a2
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV32-NEXT: lui a3, 3
; LMULMAX1-RV32-NEXT: addi a3, a3, 819
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a4, 5
; LMULMAX1-RV32-NEXT: addi a4, a4, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 8
-; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 8
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a2
-; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 4
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 2
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v26
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
+; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a2
+; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: bitreverse_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 8
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 8
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: lui a2, 1
; LMULMAX1-RV64-NEXT: addiw a2, a2, -241
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a2
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 2
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a2
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: lui a3, 3
; LMULMAX1-RV64-NEXT: addiw a3, a3, 819
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a4, 5
; LMULMAX1-RV64-NEXT: addiw a4, a4, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 8
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 8
-; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a2
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 4
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 2
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v26
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 8
+; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a2
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -812,215 +812,215 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-LABEL: bitreverse_v8i32:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 8
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v30, v26, 24
-; LMULMAX2-RV32-NEXT: vor.vv v28, v28, v30
-; LMULMAX2-RV32-NEXT: vsll.vi v30, v26, 8
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
+; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12
+; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 4080
-; LMULMAX2-RV32-NEXT: vand.vx v30, v30, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 24
-; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4
+; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 4
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 2
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 2
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: bitreverse_v8i32:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 8
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v30, v26, 24
-; LMULMAX2-RV64-NEXT: vor.vv v28, v28, v30
-; LMULMAX2-RV64-NEXT: vsll.vi v30, v26, 8
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
+; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
+; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 4080
-; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 24
-; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4
+; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 61681
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 4
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 2
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 209715
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 2
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 349525
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: bitreverse_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 8
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vsrl.vi v28, v25, 24
-; LMULMAX1-RV32-NEXT: vor.vv v27, v27, v28
-; LMULMAX1-RV32-NEXT: vsll.vi v28, v25, 8
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
+; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
+; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV32-NEXT: lui a6, 4080
-; LMULMAX1-RV32-NEXT: vand.vx v28, v28, a6
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 24
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4
+; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: lui a4, 61681
; LMULMAX1-RV32-NEXT: addi a4, a4, -241
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 2
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV32-NEXT: lui a5, 209715
; LMULMAX1-RV32-NEXT: addi a5, a5, 819
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a5
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a5
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a3, 349525
; LMULMAX1-RV32-NEXT: addi a3, a3, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 8
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vsrl.vi v28, v26, 24
-; LMULMAX1-RV32-NEXT: vor.vv v27, v27, v28
-; LMULMAX1-RV32-NEXT: vsll.vi v28, v26, 8
-; LMULMAX1-RV32-NEXT: vand.vx v28, v28, a6
-; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 24
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v28
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 4
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a5
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a5
-; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 2
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v26
-; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
+; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
+; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 8
+; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6
+; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
+; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9
+; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: bitreverse_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 8
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsrl.vi v28, v25, 24
-; LMULMAX1-RV64-NEXT: vor.vv v27, v27, v28
-; LMULMAX1-RV64-NEXT: vsll.vi v28, v25, 8
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
+; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
+; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: lui a6, 4080
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 24
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: lui a4, 61681
; LMULMAX1-RV64-NEXT: addiw a4, a4, -241
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 2
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: lui a5, 209715
; LMULMAX1-RV64-NEXT: addiw a5, a5, 819
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a5
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a3, 349525
; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 8
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsrl.vi v28, v26, 24
-; LMULMAX1-RV64-NEXT: vor.vv v27, v27, v28
-; LMULMAX1-RV64-NEXT: vsll.vi v28, v26, 8
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 24
-; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v28
-; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 4
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a5
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 2
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v26
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
+; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
+; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
+; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
+; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -1034,123 +1034,123 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-LABEL: bitreverse_v4i64:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi a1, zero, 56
-; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a1
+; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV32-NEXT: addi a2, zero, 40
-; LMULMAX2-RV32-NEXT: vsrl.vx v30, v26, a2
+; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256
-; LMULMAX2-RV32-NEXT: vand.vx v30, v30, a3
-; LMULMAX2-RV32-NEXT: vor.vv v28, v30, v28
-; LMULMAX2-RV32-NEXT: vsrl.vi v30, v26, 24
+; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3
+; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
+; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV32-NEXT: lui a4, 4080
-; LMULMAX2-RV32-NEXT: vand.vx v30, v30, a4
+; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a4
; LMULMAX2-RV32-NEXT: addi a5, zero, 85
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.i v8, 0
+; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: lui a5, 1044480
-; LMULMAX2-RV32-NEXT: vmerge.vxm v8, v8, a5, v0
+; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vsrl.vi v10, v26, 8
-; LMULMAX2-RV32-NEXT: vand.vv v8, v10, v8
-; LMULMAX2-RV32-NEXT: vor.vv v30, v8, v30
-; LMULMAX2-RV32-NEXT: vor.vv v28, v30, v28
+; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8
+; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14
+; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12
+; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: addi a5, zero, 255
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v30, a5
-; LMULMAX2-RV32-NEXT: vmerge.vim v30, v30, 0, v0
+; LMULMAX2-RV32-NEXT: vmv.v.x v12, a5
+; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vsll.vi v8, v26, 8
-; LMULMAX2-RV32-NEXT: vand.vv v30, v8, v30
+; LMULMAX2-RV32-NEXT: vsll.vi v14, v8, 8
+; LMULMAX2-RV32-NEXT: vand.vv v12, v14, v12
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v8, a3
-; LMULMAX2-RV32-NEXT: vmerge.vim v8, v8, 0, v0
+; LMULMAX2-RV32-NEXT: vmv.v.x v14, a3
+; LMULMAX2-RV32-NEXT: vmerge.vim v14, v14, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vsll.vi v10, v26, 24
-; LMULMAX2-RV32-NEXT: vand.vv v8, v10, v8
-; LMULMAX2-RV32-NEXT: vor.vv v30, v8, v30
-; LMULMAX2-RV32-NEXT: vsll.vx v8, v26, a2
+; LMULMAX2-RV32-NEXT: vsll.vi v16, v8, 24
+; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14
+; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12
+; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a2
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v10, a4
-; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 0, v0
+; LMULMAX2-RV32-NEXT: vmv.v.x v16, a4
+; LMULMAX2-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10
-; LMULMAX2-RV32-NEXT: vsll.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v8
-; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4
+; LMULMAX2-RV32-NEXT: vand.vv v14, v14, v16
+; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v14
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
+; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 4
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 2
+; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 2
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12
+; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26
-; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: bitreverse_v4i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi a1, zero, 56
-; LMULMAX2-RV64-NEXT: vsrl.vx v28, v26, a1
+; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV64-NEXT: addi a2, zero, 40
-; LMULMAX2-RV64-NEXT: vsrl.vx v30, v26, a2
+; LMULMAX2-RV64-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV64-NEXT: lui a3, 16
; LMULMAX2-RV64-NEXT: addiw a3, a3, -256
-; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a3
-; LMULMAX2-RV64-NEXT: vor.vv v28, v30, v28
-; LMULMAX2-RV64-NEXT: vsrl.vi v30, v26, 24
+; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3
+; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
+; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: lui a3, 4080
-; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a3
-; LMULMAX2-RV64-NEXT: vsrl.vi v8, v26, 8
+; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3
+; LMULMAX2-RV64-NEXT: vsrl.vi v14, v8, 8
; LMULMAX2-RV64-NEXT: addi a3, zero, 255
; LMULMAX2-RV64-NEXT: slli a4, a3, 24
-; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a4
-; LMULMAX2-RV64-NEXT: vor.vv v30, v8, v30
-; LMULMAX2-RV64-NEXT: vor.vv v28, v30, v28
-; LMULMAX2-RV64-NEXT: vsll.vi v30, v26, 8
+; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4
+; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
+; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
+; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8
; LMULMAX2-RV64-NEXT: slli a4, a3, 32
-; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a4
-; LMULMAX2-RV64-NEXT: vsll.vi v8, v26, 24
+; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a4
+; LMULMAX2-RV64-NEXT: vsll.vi v14, v8, 24
; LMULMAX2-RV64-NEXT: slli a4, a3, 40
-; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a4
-; LMULMAX2-RV64-NEXT: vor.vv v30, v8, v30
-; LMULMAX2-RV64-NEXT: vsll.vx v8, v26, a1
-; LMULMAX2-RV64-NEXT: vsll.vx v26, v26, a2
+; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4
+; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
+; LMULMAX2-RV64-NEXT: vsll.vx v14, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2
; LMULMAX2-RV64-NEXT: slli a1, a3, 48
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vor.vv v26, v8, v26
-; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vor.vv v8, v14, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
+; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 3855
; LMULMAX2-RV64-NEXT: addiw a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -1159,11 +1159,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 4
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 2
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX2-RV64-NEXT: lui a1, 13107
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -1172,11 +1172,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 2
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 21845
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -1185,174 +1185,174 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26
-; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: bitreverse_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v29, (a1)
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v12, (a1)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, zero, 56
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v29, a2
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v12, a2
; LMULMAX1-RV32-NEXT: addi a3, zero, 40
-; LMULMAX1-RV32-NEXT: vsrl.vx v27, v29, a3
+; LMULMAX1-RV32-NEXT: vsrl.vx v10, v12, a3
; LMULMAX1-RV32-NEXT: lui a4, 16
; LMULMAX1-RV32-NEXT: addi a4, a4, -256
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV32-NEXT: vor.vv v27, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v29, 24
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v12, 24
; LMULMAX1-RV32-NEXT: lui a6, 4080
-; LMULMAX1-RV32-NEXT: vand.vx v28, v26, a6
+; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a6
; LMULMAX1-RV32-NEXT: addi a5, zero, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.i v26, 0
+; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX1-RV32-NEXT: lui a5, 1044480
-; LMULMAX1-RV32-NEXT: vmerge.vxm v26, v26, a5, v0
+; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a5, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 8
-; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v26
-; LMULMAX1-RV32-NEXT: vor.vv v28, v30, v28
-; LMULMAX1-RV32-NEXT: vor.vv v30, v28, v27
+; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 8
+; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v9
+; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
+; LMULMAX1-RV32-NEXT: vor.vv v13, v11, v10
; LMULMAX1-RV32-NEXT: addi a5, zero, 255
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a5
-; LMULMAX1-RV32-NEXT: vmerge.vim v27, v27, 0, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5
+; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsll.vi v28, v29, 8
-; LMULMAX1-RV32-NEXT: vand.vv v31, v28, v27
+; LMULMAX1-RV32-NEXT: vsll.vi v11, v12, 8
+; LMULMAX1-RV32-NEXT: vand.vv v14, v11, v10
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v28, a4
-; LMULMAX1-RV32-NEXT: vmerge.vim v28, v28, 0, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v11, a4
+; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsll.vi v8, v29, 24
-; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v28
-; LMULMAX1-RV32-NEXT: vor.vv v31, v8, v31
-; LMULMAX1-RV32-NEXT: vsll.vx v8, v29, a3
+; LMULMAX1-RV32-NEXT: vsll.vi v15, v12, 24
+; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v11
+; LMULMAX1-RV32-NEXT: vor.vv v14, v15, v14
+; LMULMAX1-RV32-NEXT: vsll.vx v15, v12, a3
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v9, a6
-; LMULMAX1-RV32-NEXT: vmerge.vim v9, v9, 0, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v16, a6
+; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT: vsll.vx v29, v29, a2
-; LMULMAX1-RV32-NEXT: vor.vv v29, v29, v8
-; LMULMAX1-RV32-NEXT: vor.vv v29, v29, v31
-; LMULMAX1-RV32-NEXT: vor.vv v29, v29, v30
-; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 4
+; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16
+; LMULMAX1-RV32-NEXT: vsll.vx v12, v12, a2
+; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v15
+; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v14
+; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
+; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 4
; LMULMAX1-RV32-NEXT: lui a5, 61681
; LMULMAX1-RV32-NEXT: addi a5, a5, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v31, a5
+; LMULMAX1-RV32-NEXT: vmv.v.x v14, a5
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v31
-; LMULMAX1-RV32-NEXT: vand.vv v29, v29, v31
-; LMULMAX1-RV32-NEXT: vsll.vi v29, v29, 4
-; LMULMAX1-RV32-NEXT: vor.vv v29, v30, v29
-; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 2
+; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v14
+; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14
+; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 4
+; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
+; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 2
; LMULMAX1-RV32-NEXT: lui a5, 209715
; LMULMAX1-RV32-NEXT: addi a5, a5, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v8, a5
+; LMULMAX1-RV32-NEXT: vmv.v.x v15, a5
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v8
-; LMULMAX1-RV32-NEXT: vand.vv v29, v29, v8
-; LMULMAX1-RV32-NEXT: vsll.vi v29, v29, 2
-; LMULMAX1-RV32-NEXT: vor.vv v29, v30, v29
-; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 1
+; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v15
+; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v15
+; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 2
+; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
+; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 1
; LMULMAX1-RV32-NEXT: lui a5, 349525
; LMULMAX1-RV32-NEXT: addi a5, a5, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5
+; LMULMAX1-RV32-NEXT: vmv.v.x v17, a5
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v10
-; LMULMAX1-RV32-NEXT: vand.vv v29, v29, v10
-; LMULMAX1-RV32-NEXT: vadd.vv v29, v29, v29
-; LMULMAX1-RV32-NEXT: vor.vv v29, v30, v29
-; LMULMAX1-RV32-NEXT: vsrl.vx v30, v25, a2
-; LMULMAX1-RV32-NEXT: vsrl.vx v11, v25, a3
-; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
-; LMULMAX1-RV32-NEXT: vor.vv v30, v11, v30
-; LMULMAX1-RV32-NEXT: vsrl.vi v11, v25, 24
-; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6
-; LMULMAX1-RV32-NEXT: vsrl.vi v12, v25, 8
-; LMULMAX1-RV32-NEXT: vand.vv v26, v12, v26
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v11
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v30
-; LMULMAX1-RV32-NEXT: vsll.vi v30, v25, 8
-; LMULMAX1-RV32-NEXT: vand.vv v27, v30, v27
-; LMULMAX1-RV32-NEXT: vsll.vi v30, v25, 24
-; LMULMAX1-RV32-NEXT: vand.vv v28, v30, v28
-; LMULMAX1-RV32-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV32-NEXT: vsll.vx v28, v25, a3
-; LMULMAX1-RV32-NEXT: vand.vv v28, v28, v9
-; LMULMAX1-RV32-NEXT: vsll.vx v25, v25, a2
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v31
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v31
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v8
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v8
-; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v10
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v10
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v29, (a1)
+; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v17
+; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v17
+; LMULMAX1-RV32-NEXT: vadd.vv v12, v12, v12
+; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
+; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a2
+; LMULMAX1-RV32-NEXT: vsrl.vx v18, v8, a3
+; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a4
+; LMULMAX1-RV32-NEXT: vor.vv v13, v18, v13
+; LMULMAX1-RV32-NEXT: vsrl.vi v18, v8, 24
+; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a6
+; LMULMAX1-RV32-NEXT: vsrl.vi v19, v8, 8
+; LMULMAX1-RV32-NEXT: vand.vv v9, v19, v9
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v18
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13
+; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 8
+; LMULMAX1-RV32-NEXT: vand.vv v10, v13, v10
+; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 24
+; LMULMAX1-RV32-NEXT: vand.vv v11, v13, v11
+; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV32-NEXT: vsll.vx v11, v8, a3
+; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v16
+; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a2
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v14
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v14
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v15
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v15
+; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v17
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v17
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v12, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: bitreverse_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a7, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a7)
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a7)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi t0, zero, 56
-; LMULMAX1-RV64-NEXT: vsrl.vx v27, v26, t0
+; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, t0
; LMULMAX1-RV64-NEXT: addi t1, zero, 40
-; LMULMAX1-RV64-NEXT: vsrl.vx v28, v26, t1
+; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, t1
; LMULMAX1-RV64-NEXT: lui a1, 16
; LMULMAX1-RV64-NEXT: addiw t2, a1, -256
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t2
-; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v28, v26, 24
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2
+; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: lui a6, 4080
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6
-; LMULMAX1-RV64-NEXT: vsrl.vi v29, v26, 8
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
+; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV64-NEXT: addi a3, zero, 255
; LMULMAX1-RV64-NEXT: slli t3, a3, 24
-; LMULMAX1-RV64-NEXT: vand.vx v29, v29, t3
-; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28
-; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV64-NEXT: vsll.vi v28, v26, 8
+; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3
+; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
+; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV64-NEXT: slli t4, a3, 32
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t4
-; LMULMAX1-RV64-NEXT: vsll.vi v29, v26, 24
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4
+; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24
; LMULMAX1-RV64-NEXT: slli a2, a3, 40
-; LMULMAX1-RV64-NEXT: vand.vx v29, v29, a2
-; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28
-; LMULMAX1-RV64-NEXT: vsll.vx v29, v26, t0
-; LMULMAX1-RV64-NEXT: vsll.vx v26, v26, t1
+; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2
+; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
+; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, t0
+; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, t1
; LMULMAX1-RV64-NEXT: slli a3, a3, 48
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV64-NEXT: vor.vv v26, v29, v26
-; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v28
-; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
+; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
+; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: lui a4, 3855
; LMULMAX1-RV64-NEXT: addiw a4, a4, 241
; LMULMAX1-RV64-NEXT: slli a4, a4, 12
@@ -1361,11 +1361,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a4, a4, 241
; LMULMAX1-RV64-NEXT: slli a4, a4, 12
; LMULMAX1-RV64-NEXT: addi a4, a4, -241
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 4
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 2
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: lui a5, 13107
; LMULMAX1-RV64-NEXT: addiw a5, a5, 819
; LMULMAX1-RV64-NEXT: slli a5, a5, 12
@@ -1374,11 +1374,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a5, a5, 819
; LMULMAX1-RV64-NEXT: slli a5, a5, 12
; LMULMAX1-RV64-NEXT: addi a5, a5, 819
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a5
-; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 2
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
+; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: lui a1, 21845
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
@@ -1387,48 +1387,48 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a1
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v26
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vx v27, v25, t0
-; LMULMAX1-RV64-NEXT: vsrl.vx v28, v25, t1
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t2
-; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v28, v25, 24
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6
-; LMULMAX1-RV64-NEXT: vsrl.vi v29, v25, 8
-; LMULMAX1-RV64-NEXT: vand.vx v29, v29, t3
-; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28
-; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27
-; LMULMAX1-RV64-NEXT: vsll.vi v28, v25, 8
-; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t4
-; LMULMAX1-RV64-NEXT: vsll.vi v29, v25, 24
-; LMULMAX1-RV64-NEXT: vand.vx v29, v29, a2
-; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28
-; LMULMAX1-RV64-NEXT: vsll.vx v29, v25, t0
-; LMULMAX1-RV64-NEXT: vsll.vx v25, v25, t1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV64-NEXT: vor.vv v25, v29, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 2
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a5
-; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a1
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25
-; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a7)
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, t0
+; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, t1
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2
+; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
+; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
+; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3
+; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
+; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
+; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
+; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4
+; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24
+; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2
+; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
+; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, t0
+; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, t1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
+; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
+; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a7)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
index 16086b3272327..4178b0fc03ea2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
@@ -10,58 +10,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 30(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 26(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 22(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 20(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
@@ -69,8 +69,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: sh a1, 18(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -79,58 +79,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 30(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 26(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 22(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 20(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
@@ -138,8 +138,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: sh a1, 18(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -148,58 +148,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: or a1, a2, a1
; LMULMAX1-RV32-NEXT: sh a1, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: or a1, a2, a1
; LMULMAX1-RV32-NEXT: sh a1, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: or a1, a2, a1
; LMULMAX1-RV32-NEXT: sh a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: or a1, a2, a1
; LMULMAX1-RV32-NEXT: sh a1, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: or a1, a2, a1
; LMULMAX1-RV32-NEXT: sh a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: or a1, a2, a1
; LMULMAX1-RV32-NEXT: sh a1, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: or a1, a2, a1
; LMULMAX1-RV32-NEXT: sh a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: slli a2, a1, 8
; LMULMAX1-RV32-NEXT: slli a1, a1, 16
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
@@ -207,8 +207,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: sh a1, 18(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -217,58 +217,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: sh a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: sh a1, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: sh a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: sh a1, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: sh a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: sh a1, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: sh a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: slli a2, a1, 8
; LMULMAX1-RV64-NEXT: slli a1, a1, 48
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
@@ -276,8 +276,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: sh a1, 18(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
@@ -294,8 +294,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a2, a1, 8
; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256
@@ -310,8 +310,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a1, a1, a2
; LMULMAX2-RV32-NEXT: sw a1, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: srli a2, a1, 8
; LMULMAX2-RV32-NEXT: and a2, a2, a3
; LMULMAX2-RV32-NEXT: srli a4, a1, 24
@@ -322,8 +322,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a1, a1, a4
; LMULMAX2-RV32-NEXT: or a1, a1, a2
; LMULMAX2-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: srli a2, a1, 8
; LMULMAX2-RV32-NEXT: and a2, a2, a3
; LMULMAX2-RV32-NEXT: srli a4, a1, 24
@@ -334,8 +334,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a1, a1, a4
; LMULMAX2-RV32-NEXT: or a1, a1, a2
; LMULMAX2-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a2, a1, 8
; LMULMAX2-RV32-NEXT: and a2, a2, a3
; LMULMAX2-RV32-NEXT: srli a3, a1, 24
@@ -348,8 +348,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 20(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -358,8 +358,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srliw a2, a1, 8
; LMULMAX2-RV64-NEXT: lui a3, 16
; LMULMAX2-RV64-NEXT: addiw a3, a3, -256
@@ -374,8 +374,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: sw a1, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: srliw a2, a1, 8
; LMULMAX2-RV64-NEXT: and a2, a2, a3
; LMULMAX2-RV64-NEXT: srliw a4, a1, 24
@@ -386,8 +386,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a4
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: srliw a2, a1, 8
; LMULMAX2-RV64-NEXT: and a2, a2, a3
; LMULMAX2-RV64-NEXT: srliw a4, a1, 24
@@ -398,8 +398,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a4
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srliw a2, a1, 8
; LMULMAX2-RV64-NEXT: and a2, a2, a3
; LMULMAX2-RV64-NEXT: srliw a3, a1, 24
@@ -412,8 +412,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: sw a1, 20(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -422,8 +422,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 8
; LMULMAX1-RV32-NEXT: lui a3, 16
; LMULMAX1-RV32-NEXT: addi a3, a3, -256
@@ -438,8 +438,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 8
; LMULMAX1-RV32-NEXT: and a2, a2, a3
; LMULMAX1-RV32-NEXT: srli a4, a1, 24
@@ -450,8 +450,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 8
; LMULMAX1-RV32-NEXT: and a2, a2, a3
; LMULMAX1-RV32-NEXT: srli a4, a1, 24
@@ -462,8 +462,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 8
; LMULMAX1-RV32-NEXT: and a2, a2, a3
; LMULMAX1-RV32-NEXT: srli a3, a1, 24
@@ -476,8 +476,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -486,8 +486,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a2, a1, 8
; LMULMAX1-RV64-NEXT: lui a3, 16
; LMULMAX1-RV64-NEXT: addiw a3, a3, -256
@@ -502,8 +502,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: sw a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a2, a1, 8
; LMULMAX1-RV64-NEXT: and a2, a2, a3
; LMULMAX1-RV64-NEXT: srliw a4, a1, 24
@@ -514,8 +514,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a2, a1, 8
; LMULMAX1-RV64-NEXT: and a2, a2, a3
; LMULMAX1-RV64-NEXT: srliw a4, a1, 24
@@ -526,8 +526,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a2, a1, 8
; LMULMAX1-RV64-NEXT: and a2, a2, a3
; LMULMAX1-RV64-NEXT: srliw a3, a1, 24
@@ -540,8 +540,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: sw a1, 20(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
@@ -558,8 +558,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a2, a1, 8
; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256
@@ -574,8 +574,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a1, a1, a2
; LMULMAX2-RV32-NEXT: sw a1, 20(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: srli a2, a1, 8
; LMULMAX2-RV32-NEXT: and a2, a2, a3
; LMULMAX2-RV32-NEXT: srli a4, a1, 24
@@ -587,8 +587,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a1, a1, a2
; LMULMAX2-RV32-NEXT: sw a1, 28(sp)
; LMULMAX2-RV32-NEXT: addi a1, zero, 32
-; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: srli a4, a2, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a3
; LMULMAX2-RV32-NEXT: srli a5, a2, 24
@@ -599,8 +599,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a2, a2, a5
; LMULMAX2-RV32-NEXT: or a2, a2, a4
; LMULMAX2-RV32-NEXT: sw a2, 16(sp)
-; LMULMAX2-RV32-NEXT: vsrl.vx v25, v26, a1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v9, a1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a2, a1, 8
; LMULMAX2-RV32-NEXT: and a2, a2, a3
; LMULMAX2-RV32-NEXT: srli a3, a1, 24
@@ -613,19 +613,19 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 24(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: bswap_v2i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: srli a2, a1, 40
; LMULMAX2-RV64-NEXT: lui a3, 16
; LMULMAX2-RV64-NEXT: addiw a7, a3, -256
@@ -655,8 +655,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: or a1, a1, t1
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srli a2, a1, 24
; LMULMAX2-RV64-NEXT: and a2, a2, a6
; LMULMAX2-RV64-NEXT: srli a4, a1, 8
@@ -679,8 +679,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a3
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmv.s.x v9, a1
+; LMULMAX2-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: bswap_v2i64:
@@ -688,8 +688,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 8
; LMULMAX1-RV32-NEXT: lui a3, 16
; LMULMAX1-RV32-NEXT: addi a3, a3, -256
@@ -704,8 +704,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 8
; LMULMAX1-RV32-NEXT: and a2, a2, a3
; LMULMAX1-RV32-NEXT: srli a4, a1, 24
@@ -717,8 +717,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
; LMULMAX1-RV32-NEXT: addi a1, zero, 32
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: srli a4, a2, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a3
; LMULMAX1-RV32-NEXT: srli a5, a2, 24
@@ -729,8 +729,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a2, a2, a5
; LMULMAX1-RV32-NEXT: or a2, a2, a4
; LMULMAX1-RV32-NEXT: sw a2, 16(sp)
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v26, a1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v9, a1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 8
; LMULMAX1-RV32-NEXT: and a2, a2, a3
; LMULMAX1-RV32-NEXT: srli a3, a1, 24
@@ -743,19 +743,19 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: bswap_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srli a2, a1, 40
; LMULMAX1-RV64-NEXT: lui a3, 16
; LMULMAX1-RV64-NEXT: addiw a7, a3, -256
@@ -785,8 +785,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: or a1, a1, t1
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srli a2, a1, 24
; LMULMAX1-RV64-NEXT: and a2, a2, a6
; LMULMAX1-RV64-NEXT: srli a4, a1, 8
@@ -809,8 +809,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a3
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -833,114 +833,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 62(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 58(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 54(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 50(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 46(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 42(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 38(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: or a1, a2, a1
; LMULMAX2-RV32-NEXT: sh a1, 36(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: slli a2, a1, 8
; LMULMAX2-RV32-NEXT: slli a1, a1, 16
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
@@ -948,8 +948,8 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: sh a1, 34(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -968,114 +968,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 62(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 58(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 54(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 50(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 46(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 42(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 38(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: sh a1, 36(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: slli a2, a1, 8
; LMULMAX2-RV64-NEXT: slli a1, a1, 48
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
@@ -1083,8 +1083,8 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: sh a1, 34(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -1097,114 +1097,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 46(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 42(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 38(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 36(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 34(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: or a2, a3, a2
; LMULMAX1-RV32-NEXT: sh a2, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: slli a3, a2, 8
; LMULMAX1-RV32-NEXT: slli a2, a2, 16
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
@@ -1212,11 +1212,11 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: sh a2, 18(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a2, sp, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a2)
; LMULMAX1-RV32-NEXT: addi a2, sp, 32
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a1)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -1226,114 +1226,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 46(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 42(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 38(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 36(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 34(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 16(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: sh a2, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: slli a3, a2, 8
; LMULMAX1-RV64-NEXT: slli a2, a2, 48
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
@@ -1341,11 +1341,11 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: sh a2, 18(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a2, sp, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a2)
; LMULMAX1-RV64-NEXT: addi a2, sp, 32
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a1)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
@@ -1369,8 +1369,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v26
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8
; LMULMAX2-RV32-NEXT: srli a2, a3, 8
; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256
@@ -1385,8 +1385,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1397,8 +1397,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1409,8 +1409,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1421,8 +1421,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1433,8 +1433,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1445,8 +1445,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1457,8 +1457,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a1, a4, a1
; LMULMAX2-RV32-NEXT: srli a4, a3, 24
@@ -1471,8 +1471,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 36(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -1491,8 +1491,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v26
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v8
; LMULMAX2-RV64-NEXT: srliw a2, a3, 8
; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
@@ -1507,8 +1507,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a3, a3, a4
; LMULMAX2-RV64-NEXT: sw a3, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV64-NEXT: srliw a4, a3, 8
; LMULMAX2-RV64-NEXT: and a4, a4, a1
; LMULMAX2-RV64-NEXT: srliw a5, a3, 24
@@ -1519,8 +1519,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a3, a3, a5
; LMULMAX2-RV64-NEXT: or a3, a3, a4
; LMULMAX2-RV64-NEXT: sw a3, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV64-NEXT: srliw a4, a3, 8
; LMULMAX2-RV64-NEXT: and a4, a4, a1
; LMULMAX2-RV64-NEXT: srliw a5, a3, 24
@@ -1531,8 +1531,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a3, a3, a5
; LMULMAX2-RV64-NEXT: or a3, a3, a4
; LMULMAX2-RV64-NEXT: sw a3, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV64-NEXT: srliw a4, a3, 8
; LMULMAX2-RV64-NEXT: and a4, a4, a1
; LMULMAX2-RV64-NEXT: srliw a5, a3, 24
@@ -1543,8 +1543,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a3, a3, a5
; LMULMAX2-RV64-NEXT: or a3, a3, a4
; LMULMAX2-RV64-NEXT: sw a3, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV64-NEXT: srliw a4, a3, 8
; LMULMAX2-RV64-NEXT: and a4, a4, a1
; LMULMAX2-RV64-NEXT: srliw a5, a3, 24
@@ -1555,8 +1555,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a3, a3, a5
; LMULMAX2-RV64-NEXT: or a3, a3, a4
; LMULMAX2-RV64-NEXT: sw a3, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV64-NEXT: srliw a4, a3, 8
; LMULMAX2-RV64-NEXT: and a4, a4, a1
; LMULMAX2-RV64-NEXT: srliw a5, a3, 24
@@ -1567,8 +1567,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a3, a3, a5
; LMULMAX2-RV64-NEXT: or a3, a3, a4
; LMULMAX2-RV64-NEXT: sw a3, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV64-NEXT: srliw a4, a3, 8
; LMULMAX2-RV64-NEXT: and a4, a4, a1
; LMULMAX2-RV64-NEXT: srliw a5, a3, 24
@@ -1579,8 +1579,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: or a3, a3, a5
; LMULMAX2-RV64-NEXT: or a3, a3, a4
; LMULMAX2-RV64-NEXT: sw a3, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a3, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a3, v8
; LMULMAX2-RV64-NEXT: srliw a4, a3, 8
; LMULMAX2-RV64-NEXT: and a1, a4, a1
; LMULMAX2-RV64-NEXT: srliw a4, a3, 24
@@ -1593,8 +1593,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: sw a1, 36(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -1607,9 +1607,9 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a4, v26
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a4, v9
; LMULMAX1-RV32-NEXT: srli a3, a4, 8
; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256
@@ -1624,8 +1624,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: sw a1, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -1636,8 +1636,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -1648,8 +1648,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -1660,7 +1660,7 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 36(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -1671,8 +1671,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -1683,8 +1683,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -1695,8 +1695,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a2, a4, a2
; LMULMAX1-RV32-NEXT: srli a4, a1, 24
@@ -1709,11 +1709,11 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -1723,9 +1723,9 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a4, v26
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a4, v9
; LMULMAX1-RV64-NEXT: srliw a3, a4, 8
; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
@@ -1740,8 +1740,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: sw a1, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: srliw a4, a1, 8
; LMULMAX1-RV64-NEXT: and a4, a4, a2
; LMULMAX1-RV64-NEXT: srliw a5, a1, 24
@@ -1752,8 +1752,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: sw a1, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: srliw a4, a1, 8
; LMULMAX1-RV64-NEXT: and a4, a4, a2
; LMULMAX1-RV64-NEXT: srliw a5, a1, 24
@@ -1764,8 +1764,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: sw a1, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a4, a1, 8
; LMULMAX1-RV64-NEXT: and a4, a4, a2
; LMULMAX1-RV64-NEXT: srliw a5, a1, 24
@@ -1776,7 +1776,7 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: sw a1, 36(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a4, a1, 8
; LMULMAX1-RV64-NEXT: and a4, a4, a2
; LMULMAX1-RV64-NEXT: srliw a5, a1, 24
@@ -1787,8 +1787,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: sw a1, 16(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a4, a1, 8
; LMULMAX1-RV64-NEXT: and a4, a4, a2
; LMULMAX1-RV64-NEXT: srliw a5, a1, 24
@@ -1799,8 +1799,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a4, a1, 8
; LMULMAX1-RV64-NEXT: and a4, a4, a2
; LMULMAX1-RV64-NEXT: srliw a5, a1, 24
@@ -1811,8 +1811,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a4, a1, 8
; LMULMAX1-RV64-NEXT: and a2, a4, a2
; LMULMAX1-RV64-NEXT: srliw a4, a1, 24
@@ -1825,11 +1825,11 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: sw a1, 20(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, sp, 32
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a6)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
@@ -1853,8 +1853,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v26
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8
; LMULMAX2-RV32-NEXT: srli a2, a3, 8
; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256
@@ -1869,8 +1869,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 36(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1881,8 +1881,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v30, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v30
+; LMULMAX2-RV32-NEXT: vslidedown.vi v12, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v12
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1893,8 +1893,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a5
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8
+; LMULMAX2-RV32-NEXT: vslidedown.vi v14, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a3, v14
; LMULMAX2-RV32-NEXT: srli a4, a3, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a3, 24
@@ -1906,8 +1906,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a3, a3, a4
; LMULMAX2-RV32-NEXT: sw a3, 44(sp)
; LMULMAX2-RV32-NEXT: addi a3, zero, 32
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a3
-; LMULMAX2-RV32-NEXT: vmv.x.s a4, v26
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a3
+; LMULMAX2-RV32-NEXT: vmv.x.s a4, v8
; LMULMAX2-RV32-NEXT: srli a5, a4, 8
; LMULMAX2-RV32-NEXT: and a5, a5, a1
; LMULMAX2-RV32-NEXT: srli a2, a4, 24
@@ -1918,8 +1918,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a4, a4, a5
; LMULMAX2-RV32-NEXT: or a2, a4, a2
; LMULMAX2-RV32-NEXT: sw a2, 32(sp)
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v28, a3
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v10, a3
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: srli a4, a2, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a2, 24
@@ -1930,8 +1930,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a2, a2, a5
; LMULMAX2-RV32-NEXT: or a2, a2, a4
; LMULMAX2-RV32-NEXT: sw a2, 56(sp)
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v30, a3
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v12, a3
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: srli a4, a2, 8
; LMULMAX2-RV32-NEXT: and a4, a4, a1
; LMULMAX2-RV32-NEXT: srli a5, a2, 24
@@ -1942,8 +1942,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: or a2, a2, a5
; LMULMAX2-RV32-NEXT: or a2, a2, a4
; LMULMAX2-RV32-NEXT: sw a2, 48(sp)
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v8, a3
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v14, a3
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: srli a3, a2, 8
; LMULMAX2-RV32-NEXT: and a1, a3, a1
; LMULMAX2-RV32-NEXT: srli a3, a2, 24
@@ -1956,9 +1956,9 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 40(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -1977,8 +1977,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srli a2, a1, 24
; LMULMAX2-RV64-NEXT: lui a6, 4080
; LMULMAX2-RV64-NEXT: and a3, a2, a6
@@ -2009,8 +2009,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: sd a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srli a2, a1, 40
; LMULMAX2-RV64-NEXT: and a2, a2, a5
; LMULMAX2-RV64-NEXT: srli a3, a1, 56
@@ -2033,8 +2033,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a3
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: sd a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srli a2, a1, 40
; LMULMAX2-RV64-NEXT: and a2, a2, a5
; LMULMAX2-RV64-NEXT: srli a3, a1, 56
@@ -2057,8 +2057,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: or a1, a1, a3
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: sd a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srli a2, a1, 40
; LMULMAX2-RV64-NEXT: and a2, a2, a5
; LMULMAX2-RV64-NEXT: srli a3, a1, 56
@@ -2083,8 +2083,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: sd a1, 40(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -2097,9 +2097,9 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a4, v26
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a4, v9
; LMULMAX1-RV32-NEXT: srli a3, a4, 8
; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256
@@ -2114,8 +2114,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: sw a1, 36(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -2127,8 +2127,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 44(sp)
; LMULMAX1-RV32-NEXT: addi a7, zero, 32
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a5, a1, 8
; LMULMAX1-RV32-NEXT: and a5, a5, a2
; LMULMAX1-RV32-NEXT: srli a4, a1, 24
@@ -2139,8 +2139,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 32(sp)
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v27, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v10, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -2151,7 +2151,7 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 40(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -2162,8 +2162,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -2174,8 +2174,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a4, a4, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
@@ -2186,8 +2186,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: or a1, a1, a4
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v26, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v9, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a4, a1, 8
; LMULMAX1-RV32-NEXT: and a2, a4, a2
; LMULMAX1-RV32-NEXT: srli a4, a1, 24
@@ -2200,12 +2200,12 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -2213,11 +2213,11 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a6)
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a6)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v27, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a4, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v10, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a4, v9
; LMULMAX1-RV64-NEXT: srli a1, a4, 40
; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw t0, a2, -256
@@ -2247,8 +2247,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: or a3, a4, a3
; LMULMAX1-RV64-NEXT: or a2, a3, a2
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v26, a2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vmv.v.x v9, a2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: srli a3, a2, 24
; LMULMAX1-RV64-NEXT: and a3, a3, a7
; LMULMAX1-RV64-NEXT: srli a4, a2, 8
@@ -2271,10 +2271,10 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: or a2, a2, a4
; LMULMAX1-RV64-NEXT: or a2, a2, a3
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v26, a2
+; LMULMAX1-RV64-NEXT: vmv.s.x v9, a2
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: srli a3, a2, 40
; LMULMAX1-RV64-NEXT: and a3, a3, t0
; LMULMAX1-RV64-NEXT: srli a4, a2, 56
@@ -2297,8 +2297,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: or a2, a2, a4
; LMULMAX1-RV64-NEXT: or a2, a2, a3
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v27, a2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vmv.v.x v10, a2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: srli a3, a2, 24
; LMULMAX1-RV64-NEXT: and a3, a3, a7
; LMULMAX1-RV64-NEXT: srli a4, a2, 8
@@ -2321,9 +2321,9 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: or a1, a1, a3
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
-; LMULMAX1-RV64-NEXT: vse64.v v27, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vmv.s.x v10, a1
+; LMULMAX1-RV64-NEXT: vse64.v v10, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a6)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
index dafb9a179436f..bb84ddd0ca5ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
@@ -122,17 +122,17 @@ define fastcc <128 x i32> @ret_split_v128i32(<128 x i32>* %x) {
; LMULMAX4-LABEL: ret_split_v128i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (a1)
+; LMULMAX4-NEXT: vle32.v v8, (a1)
; LMULMAX4-NEXT: addi a2, a1, 64
-; LMULMAX4-NEXT: vle32.v v8, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 128
; LMULMAX4-NEXT: vle32.v v12, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 192
+; LMULMAX4-NEXT: addi a2, a1, 128
; LMULMAX4-NEXT: vle32.v v16, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 256
+; LMULMAX4-NEXT: addi a2, a1, 192
; LMULMAX4-NEXT: vle32.v v20, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 320
+; LMULMAX4-NEXT: addi a2, a1, 256
; LMULMAX4-NEXT: vle32.v v24, (a2)
+; LMULMAX4-NEXT: addi a2, a1, 320
+; LMULMAX4-NEXT: vle32.v v28, (a2)
; LMULMAX4-NEXT: addi a2, a1, 448
; LMULMAX4-NEXT: vle32.v v0, (a2)
; LMULMAX4-NEXT: addi a1, a1, 384
@@ -142,16 +142,16 @@ define fastcc <128 x i32> @ret_split_v128i32(<128 x i32>* %x) {
; LMULMAX4-NEXT: addi a1, a0, 384
; LMULMAX4-NEXT: vse32.v v4, (a1)
; LMULMAX4-NEXT: addi a1, a0, 320
-; LMULMAX4-NEXT: vse32.v v24, (a1)
+; LMULMAX4-NEXT: vse32.v v28, (a1)
; LMULMAX4-NEXT: addi a1, a0, 256
-; LMULMAX4-NEXT: vse32.v v20, (a1)
+; LMULMAX4-NEXT: vse32.v v24, (a1)
; LMULMAX4-NEXT: addi a1, a0, 192
-; LMULMAX4-NEXT: vse32.v v16, (a1)
+; LMULMAX4-NEXT: vse32.v v20, (a1)
; LMULMAX4-NEXT: addi a1, a0, 128
-; LMULMAX4-NEXT: vse32.v v12, (a1)
+; LMULMAX4-NEXT: vse32.v v16, (a1)
; LMULMAX4-NEXT: addi a1, a0, 64
-; LMULMAX4-NEXT: vse32.v v8, (a1)
-; LMULMAX4-NEXT: vse32.v v28, (a0)
+; LMULMAX4-NEXT: vse32.v v12, (a1)
+; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: ret
%v = load <128 x i32>, <128 x i32>* %x
ret <128 x i32> %v
@@ -223,14 +223,14 @@ define fastcc <32 x i32> @ret_v32i32_param_v32i32_v32i32_v32i32_i32(<32 x i32> %
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: addi a1, a0, 64
-; LMULMAX4-NEXT: vle32.v v28, (a1)
-; LMULMAX4-NEXT: vle32.v v24, (a0)
+; LMULMAX4-NEXT: vle32.v v24, (a1)
+; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: vadd.vv v8, v8, v16
; LMULMAX4-NEXT: vadd.vv v12, v12, v20
-; LMULMAX4-NEXT: vadd.vv v28, v12, v28
-; LMULMAX4-NEXT: vadd.vv v8, v8, v24
+; LMULMAX4-NEXT: vadd.vv v12, v12, v24
+; LMULMAX4-NEXT: vadd.vv v8, v8, v28
; LMULMAX4-NEXT: vadd.vx v8, v8, a2
-; LMULMAX4-NEXT: vadd.vx v12, v28, a2
+; LMULMAX4-NEXT: vadd.vx v12, v12, a2
; LMULMAX4-NEXT: ret
%r = add <32 x i32> %x, %y
%s = add <32 x i32> %r, %z
@@ -265,13 +265,13 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX4-NEXT: .cfi_def_cfa_offset 16
; LMULMAX4-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8
-; LMULMAX4-NEXT: vmv4r.v v28, v12
-; LMULMAX4-NEXT: vmv4r.v v24, v8
+; LMULMAX4-NEXT: vmv4r.v v24, v12
+; LMULMAX4-NEXT: vmv4r.v v28, v8
; LMULMAX4-NEXT: addi a1, zero, 2
; LMULMAX4-NEXT: vmv4r.v v8, v16
; LMULMAX4-NEXT: vmv4r.v v12, v20
-; LMULMAX4-NEXT: vmv4r.v v16, v24
-; LMULMAX4-NEXT: vmv4r.v v20, v28
+; LMULMAX4-NEXT: vmv4r.v v16, v28
+; LMULMAX4-NEXT: vmv4r.v v20, v24
; LMULMAX4-NEXT: call ext2 at plt
; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 16
@@ -319,17 +319,17 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (a0)
-; LMULMAX4-NEXT: addi a0, a0, 64
; LMULMAX4-NEXT: vle32.v v24, (a0)
+; LMULMAX4-NEXT: addi a0, a0, 64
+; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: addi a0, sp, 192
; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: addi a0, sp, 128
; LMULMAX4-NEXT: addi a3, zero, 42
; LMULMAX4-NEXT: addi a1, sp, 128
; LMULMAX4-NEXT: vse32.v v8, (a1)
-; LMULMAX4-NEXT: vmv4r.v v8, v28
-; LMULMAX4-NEXT: vmv4r.v v12, v24
+; LMULMAX4-NEXT: vmv4r.v v8, v24
+; LMULMAX4-NEXT: vmv4r.v v12, v28
; LMULMAX4-NEXT: call ext3 at plt
; LMULMAX4-NEXT: addi sp, s0, -384
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -356,10 +356,10 @@ define fastcc <32 x i32> @vector_arg_indirect_stack(i32 %0, i32 %1, i32 %2, i32
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi a0, t2, 64
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (t2)
-; LMULMAX4-NEXT: vle32.v v16, (a0)
-; LMULMAX4-NEXT: vadd.vv v8, v8, v28
-; LMULMAX4-NEXT: vadd.vv v12, v12, v16
+; LMULMAX4-NEXT: vle32.v v16, (t2)
+; LMULMAX4-NEXT: vle32.v v20, (a0)
+; LMULMAX4-NEXT: vadd.vv v8, v8, v16
+; LMULMAX4-NEXT: vadd.vv v12, v12, v20
; LMULMAX4-NEXT: ret
%s = add <32 x i32> %x, %z
ret <32 x i32> %s
@@ -462,13 +462,13 @@ define fastcc <32 x i32> @vector_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 %3
; LMULMAX4-NEXT: .cfi_def_cfa_offset 16
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: addi a0, sp, 24
-; LMULMAX4-NEXT: vle32.v v28, (a0)
-; LMULMAX4-NEXT: addi a0, sp, 88
; LMULMAX4-NEXT: vle32.v v24, (a0)
+; LMULMAX4-NEXT: addi a0, sp, 88
+; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: vadd.vv v12, v12, v20
; LMULMAX4-NEXT: vadd.vv v8, v8, v16
-; LMULMAX4-NEXT: vadd.vv v8, v8, v28
-; LMULMAX4-NEXT: vadd.vv v12, v12, v24
+; LMULMAX4-NEXT: vadd.vv v8, v8, v24
+; LMULMAX4-NEXT: vadd.vv v12, v12, v28
; LMULMAX4-NEXT: addi sp, sp, 16
; LMULMAX4-NEXT: ret
%s = add <32 x i32> %x, %y
@@ -561,8 +561,8 @@ define fastcc <4 x i1> @vector_mask_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 152
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vmxor.mm v0, v0, v25
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%r = xor <4 x i1> %m1, %m2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
index 35ab9360b8f20..fa1d7b756aecb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
@@ -254,17 +254,17 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) {
; LMULMAX4-LABEL: ret_split_v128i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (a1)
+; LMULMAX4-NEXT: vle32.v v8, (a1)
; LMULMAX4-NEXT: addi a2, a1, 64
-; LMULMAX4-NEXT: vle32.v v8, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 128
; LMULMAX4-NEXT: vle32.v v12, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 192
+; LMULMAX4-NEXT: addi a2, a1, 128
; LMULMAX4-NEXT: vle32.v v16, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 256
+; LMULMAX4-NEXT: addi a2, a1, 192
; LMULMAX4-NEXT: vle32.v v20, (a2)
-; LMULMAX4-NEXT: addi a2, a1, 320
+; LMULMAX4-NEXT: addi a2, a1, 256
; LMULMAX4-NEXT: vle32.v v24, (a2)
+; LMULMAX4-NEXT: addi a2, a1, 320
+; LMULMAX4-NEXT: vle32.v v28, (a2)
; LMULMAX4-NEXT: addi a2, a1, 448
; LMULMAX4-NEXT: vle32.v v0, (a2)
; LMULMAX4-NEXT: addi a1, a1, 384
@@ -274,44 +274,44 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) {
; LMULMAX4-NEXT: addi a1, a0, 384
; LMULMAX4-NEXT: vse32.v v4, (a1)
; LMULMAX4-NEXT: addi a1, a0, 320
-; LMULMAX4-NEXT: vse32.v v24, (a1)
+; LMULMAX4-NEXT: vse32.v v28, (a1)
; LMULMAX4-NEXT: addi a1, a0, 256
-; LMULMAX4-NEXT: vse32.v v20, (a1)
+; LMULMAX4-NEXT: vse32.v v24, (a1)
; LMULMAX4-NEXT: addi a1, a0, 192
-; LMULMAX4-NEXT: vse32.v v16, (a1)
+; LMULMAX4-NEXT: vse32.v v20, (a1)
; LMULMAX4-NEXT: addi a1, a0, 128
-; LMULMAX4-NEXT: vse32.v v12, (a1)
+; LMULMAX4-NEXT: vse32.v v16, (a1)
; LMULMAX4-NEXT: addi a1, a0, 64
-; LMULMAX4-NEXT: vse32.v v8, (a1)
-; LMULMAX4-NEXT: vse32.v v28, (a0)
+; LMULMAX4-NEXT: vse32.v v12, (a1)
+; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: ret
;
; LMULMAX2-LABEL: ret_split_v128i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a1)
+; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: addi a2, a1, 32
-; LMULMAX2-NEXT: vle32.v v28, (a2)
+; LMULMAX2-NEXT: vle32.v v10, (a2)
; LMULMAX2-NEXT: addi a2, a1, 64
-; LMULMAX2-NEXT: vle32.v v30, (a2)
+; LMULMAX2-NEXT: vle32.v v12, (a2)
; LMULMAX2-NEXT: addi a2, a1, 96
-; LMULMAX2-NEXT: vle32.v v8, (a2)
+; LMULMAX2-NEXT: vle32.v v14, (a2)
; LMULMAX2-NEXT: addi a2, a1, 128
-; LMULMAX2-NEXT: vle32.v v10, (a2)
+; LMULMAX2-NEXT: vle32.v v16, (a2)
; LMULMAX2-NEXT: addi a2, a1, 160
-; LMULMAX2-NEXT: vle32.v v12, (a2)
+; LMULMAX2-NEXT: vle32.v v18, (a2)
; LMULMAX2-NEXT: addi a2, a1, 192
-; LMULMAX2-NEXT: vle32.v v14, (a2)
+; LMULMAX2-NEXT: vle32.v v20, (a2)
; LMULMAX2-NEXT: addi a2, a1, 224
-; LMULMAX2-NEXT: vle32.v v16, (a2)
+; LMULMAX2-NEXT: vle32.v v22, (a2)
; LMULMAX2-NEXT: addi a2, a1, 256
-; LMULMAX2-NEXT: vle32.v v18, (a2)
+; LMULMAX2-NEXT: vle32.v v24, (a2)
; LMULMAX2-NEXT: addi a2, a1, 288
-; LMULMAX2-NEXT: vle32.v v20, (a2)
+; LMULMAX2-NEXT: vle32.v v26, (a2)
; LMULMAX2-NEXT: addi a2, a1, 320
-; LMULMAX2-NEXT: vle32.v v22, (a2)
+; LMULMAX2-NEXT: vle32.v v28, (a2)
; LMULMAX2-NEXT: addi a2, a1, 352
-; LMULMAX2-NEXT: vle32.v v24, (a2)
+; LMULMAX2-NEXT: vle32.v v30, (a2)
; LMULMAX2-NEXT: addi a2, a1, 384
; LMULMAX2-NEXT: vle32.v v0, (a2)
; LMULMAX2-NEXT: addi a2, a1, 416
@@ -329,80 +329,80 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) {
; LMULMAX2-NEXT: addi a1, a0, 384
; LMULMAX2-NEXT: vse32.v v0, (a1)
; LMULMAX2-NEXT: addi a1, a0, 352
-; LMULMAX2-NEXT: vse32.v v24, (a1)
+; LMULMAX2-NEXT: vse32.v v30, (a1)
; LMULMAX2-NEXT: addi a1, a0, 320
-; LMULMAX2-NEXT: vse32.v v22, (a1)
+; LMULMAX2-NEXT: vse32.v v28, (a1)
; LMULMAX2-NEXT: addi a1, a0, 288
-; LMULMAX2-NEXT: vse32.v v20, (a1)
+; LMULMAX2-NEXT: vse32.v v26, (a1)
; LMULMAX2-NEXT: addi a1, a0, 256
-; LMULMAX2-NEXT: vse32.v v18, (a1)
+; LMULMAX2-NEXT: vse32.v v24, (a1)
; LMULMAX2-NEXT: addi a1, a0, 224
-; LMULMAX2-NEXT: vse32.v v16, (a1)
+; LMULMAX2-NEXT: vse32.v v22, (a1)
; LMULMAX2-NEXT: addi a1, a0, 192
-; LMULMAX2-NEXT: vse32.v v14, (a1)
+; LMULMAX2-NEXT: vse32.v v20, (a1)
; LMULMAX2-NEXT: addi a1, a0, 160
-; LMULMAX2-NEXT: vse32.v v12, (a1)
+; LMULMAX2-NEXT: vse32.v v18, (a1)
; LMULMAX2-NEXT: addi a1, a0, 128
-; LMULMAX2-NEXT: vse32.v v10, (a1)
+; LMULMAX2-NEXT: vse32.v v16, (a1)
; LMULMAX2-NEXT: addi a1, a0, 96
-; LMULMAX2-NEXT: vse32.v v8, (a1)
+; LMULMAX2-NEXT: vse32.v v14, (a1)
; LMULMAX2-NEXT: addi a1, a0, 64
-; LMULMAX2-NEXT: vse32.v v30, (a1)
+; LMULMAX2-NEXT: vse32.v v12, (a1)
; LMULMAX2-NEXT: addi a1, a0, 32
-; LMULMAX2-NEXT: vse32.v v28, (a1)
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vse32.v v10, (a1)
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: ret_split_v128i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: addi a2, a1, 16
-; LMULMAX1-NEXT: vle32.v v26, (a2)
+; LMULMAX1-NEXT: vle32.v v9, (a2)
; LMULMAX1-NEXT: addi a2, a1, 32
-; LMULMAX1-NEXT: vle32.v v27, (a2)
+; LMULMAX1-NEXT: vle32.v v10, (a2)
; LMULMAX1-NEXT: addi a2, a1, 48
-; LMULMAX1-NEXT: vle32.v v28, (a2)
+; LMULMAX1-NEXT: vle32.v v11, (a2)
; LMULMAX1-NEXT: addi a2, a1, 64
-; LMULMAX1-NEXT: vle32.v v29, (a2)
+; LMULMAX1-NEXT: vle32.v v12, (a2)
; LMULMAX1-NEXT: addi a2, a1, 80
-; LMULMAX1-NEXT: vle32.v v30, (a2)
+; LMULMAX1-NEXT: vle32.v v13, (a2)
; LMULMAX1-NEXT: addi a2, a1, 96
-; LMULMAX1-NEXT: vle32.v v31, (a2)
+; LMULMAX1-NEXT: vle32.v v14, (a2)
; LMULMAX1-NEXT: addi a2, a1, 112
-; LMULMAX1-NEXT: vle32.v v8, (a2)
+; LMULMAX1-NEXT: vle32.v v15, (a2)
; LMULMAX1-NEXT: addi a2, a1, 128
-; LMULMAX1-NEXT: vle32.v v9, (a2)
+; LMULMAX1-NEXT: vle32.v v16, (a2)
; LMULMAX1-NEXT: addi a2, a1, 144
-; LMULMAX1-NEXT: vle32.v v10, (a2)
+; LMULMAX1-NEXT: vle32.v v17, (a2)
; LMULMAX1-NEXT: addi a2, a1, 160
-; LMULMAX1-NEXT: vle32.v v11, (a2)
+; LMULMAX1-NEXT: vle32.v v18, (a2)
; LMULMAX1-NEXT: addi a2, a1, 176
-; LMULMAX1-NEXT: vle32.v v12, (a2)
+; LMULMAX1-NEXT: vle32.v v19, (a2)
; LMULMAX1-NEXT: addi a2, a1, 192
-; LMULMAX1-NEXT: vle32.v v13, (a2)
+; LMULMAX1-NEXT: vle32.v v20, (a2)
; LMULMAX1-NEXT: addi a2, a1, 208
-; LMULMAX1-NEXT: vle32.v v14, (a2)
+; LMULMAX1-NEXT: vle32.v v21, (a2)
; LMULMAX1-NEXT: addi a2, a1, 224
-; LMULMAX1-NEXT: vle32.v v15, (a2)
+; LMULMAX1-NEXT: vle32.v v22, (a2)
; LMULMAX1-NEXT: addi a2, a1, 240
-; LMULMAX1-NEXT: vle32.v v16, (a2)
+; LMULMAX1-NEXT: vle32.v v23, (a2)
; LMULMAX1-NEXT: addi a2, a1, 256
-; LMULMAX1-NEXT: vle32.v v17, (a2)
+; LMULMAX1-NEXT: vle32.v v24, (a2)
; LMULMAX1-NEXT: addi a2, a1, 272
-; LMULMAX1-NEXT: vle32.v v18, (a2)
+; LMULMAX1-NEXT: vle32.v v25, (a2)
; LMULMAX1-NEXT: addi a2, a1, 288
-; LMULMAX1-NEXT: vle32.v v19, (a2)
+; LMULMAX1-NEXT: vle32.v v26, (a2)
; LMULMAX1-NEXT: addi a2, a1, 304
-; LMULMAX1-NEXT: vle32.v v20, (a2)
+; LMULMAX1-NEXT: vle32.v v27, (a2)
; LMULMAX1-NEXT: addi a2, a1, 320
-; LMULMAX1-NEXT: vle32.v v21, (a2)
+; LMULMAX1-NEXT: vle32.v v28, (a2)
; LMULMAX1-NEXT: addi a2, a1, 336
-; LMULMAX1-NEXT: vle32.v v22, (a2)
+; LMULMAX1-NEXT: vle32.v v29, (a2)
; LMULMAX1-NEXT: addi a2, a1, 352
-; LMULMAX1-NEXT: vle32.v v23, (a2)
+; LMULMAX1-NEXT: vle32.v v30, (a2)
; LMULMAX1-NEXT: addi a2, a1, 368
-; LMULMAX1-NEXT: vle32.v v24, (a2)
+; LMULMAX1-NEXT: vle32.v v31, (a2)
; LMULMAX1-NEXT: addi a2, a1, 384
; LMULMAX1-NEXT: vle32.v v0, (a2)
; LMULMAX1-NEXT: addi a2, a1, 400
@@ -436,52 +436,52 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) {
; LMULMAX1-NEXT: addi a1, a0, 384
; LMULMAX1-NEXT: vse32.v v0, (a1)
; LMULMAX1-NEXT: addi a1, a0, 368
-; LMULMAX1-NEXT: vse32.v v24, (a1)
+; LMULMAX1-NEXT: vse32.v v31, (a1)
; LMULMAX1-NEXT: addi a1, a0, 352
-; LMULMAX1-NEXT: vse32.v v23, (a1)
+; LMULMAX1-NEXT: vse32.v v30, (a1)
; LMULMAX1-NEXT: addi a1, a0, 336
-; LMULMAX1-NEXT: vse32.v v22, (a1)
+; LMULMAX1-NEXT: vse32.v v29, (a1)
; LMULMAX1-NEXT: addi a1, a0, 320
-; LMULMAX1-NEXT: vse32.v v21, (a1)
+; LMULMAX1-NEXT: vse32.v v28, (a1)
; LMULMAX1-NEXT: addi a1, a0, 304
-; LMULMAX1-NEXT: vse32.v v20, (a1)
+; LMULMAX1-NEXT: vse32.v v27, (a1)
; LMULMAX1-NEXT: addi a1, a0, 288
-; LMULMAX1-NEXT: vse32.v v19, (a1)
+; LMULMAX1-NEXT: vse32.v v26, (a1)
; LMULMAX1-NEXT: addi a1, a0, 272
-; LMULMAX1-NEXT: vse32.v v18, (a1)
+; LMULMAX1-NEXT: vse32.v v25, (a1)
; LMULMAX1-NEXT: addi a1, a0, 256
-; LMULMAX1-NEXT: vse32.v v17, (a1)
+; LMULMAX1-NEXT: vse32.v v24, (a1)
; LMULMAX1-NEXT: addi a1, a0, 240
-; LMULMAX1-NEXT: vse32.v v16, (a1)
+; LMULMAX1-NEXT: vse32.v v23, (a1)
; LMULMAX1-NEXT: addi a1, a0, 224
-; LMULMAX1-NEXT: vse32.v v15, (a1)
+; LMULMAX1-NEXT: vse32.v v22, (a1)
; LMULMAX1-NEXT: addi a1, a0, 208
-; LMULMAX1-NEXT: vse32.v v14, (a1)
+; LMULMAX1-NEXT: vse32.v v21, (a1)
; LMULMAX1-NEXT: addi a1, a0, 192
-; LMULMAX1-NEXT: vse32.v v13, (a1)
+; LMULMAX1-NEXT: vse32.v v20, (a1)
; LMULMAX1-NEXT: addi a1, a0, 176
-; LMULMAX1-NEXT: vse32.v v12, (a1)
+; LMULMAX1-NEXT: vse32.v v19, (a1)
; LMULMAX1-NEXT: addi a1, a0, 160
-; LMULMAX1-NEXT: vse32.v v11, (a1)
+; LMULMAX1-NEXT: vse32.v v18, (a1)
; LMULMAX1-NEXT: addi a1, a0, 144
-; LMULMAX1-NEXT: vse32.v v10, (a1)
+; LMULMAX1-NEXT: vse32.v v17, (a1)
; LMULMAX1-NEXT: addi a1, a0, 128
-; LMULMAX1-NEXT: vse32.v v9, (a1)
+; LMULMAX1-NEXT: vse32.v v16, (a1)
; LMULMAX1-NEXT: addi a1, a0, 112
-; LMULMAX1-NEXT: vse32.v v8, (a1)
+; LMULMAX1-NEXT: vse32.v v15, (a1)
; LMULMAX1-NEXT: addi a1, a0, 96
-; LMULMAX1-NEXT: vse32.v v31, (a1)
+; LMULMAX1-NEXT: vse32.v v14, (a1)
; LMULMAX1-NEXT: addi a1, a0, 80
-; LMULMAX1-NEXT: vse32.v v30, (a1)
+; LMULMAX1-NEXT: vse32.v v13, (a1)
; LMULMAX1-NEXT: addi a1, a0, 64
-; LMULMAX1-NEXT: vse32.v v29, (a1)
+; LMULMAX1-NEXT: vse32.v v12, (a1)
; LMULMAX1-NEXT: addi a1, a0, 48
-; LMULMAX1-NEXT: vse32.v v28, (a1)
+; LMULMAX1-NEXT: vse32.v v11, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
-; LMULMAX1-NEXT: vse32.v v27, (a1)
+; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse32.v v26, (a1)
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v9, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%v = load <128 x i32>, <128 x i32>* %x
ret <128 x i32> %v
@@ -593,58 +593,58 @@ define <32 x i32> @ret_v32i32_param_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: addi a1, a0, 64
-; LMULMAX4-NEXT: vle32.v v28, (a1)
-; LMULMAX4-NEXT: vle32.v v24, (a0)
+; LMULMAX4-NEXT: vle32.v v24, (a1)
+; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: vadd.vv v8, v8, v16
; LMULMAX4-NEXT: vadd.vv v12, v12, v20
-; LMULMAX4-NEXT: vadd.vv v28, v12, v28
-; LMULMAX4-NEXT: vadd.vv v8, v8, v24
+; LMULMAX4-NEXT: vadd.vv v12, v12, v24
+; LMULMAX4-NEXT: vadd.vv v8, v8, v28
; LMULMAX4-NEXT: vadd.vx v8, v8, a2
-; LMULMAX4-NEXT: vadd.vx v12, v28, a2
+; LMULMAX4-NEXT: vadd.vx v12, v12, a2
; LMULMAX4-NEXT: ret
;
; LMULMAX2-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v24, (a0)
; LMULMAX2-NEXT: addi a1, a0, 32
-; LMULMAX2-NEXT: vle32.v v28, (a1)
+; LMULMAX2-NEXT: vle32.v v26, (a1)
; LMULMAX2-NEXT: addi a1, a0, 64
-; LMULMAX2-NEXT: vle32.v v30, (a1)
+; LMULMAX2-NEXT: vle32.v v28, (a1)
; LMULMAX2-NEXT: addi a0, a0, 96
-; LMULMAX2-NEXT: vle32.v v24, (a0)
+; LMULMAX2-NEXT: vle32.v v30, (a0)
; LMULMAX2-NEXT: vadd.vv v8, v8, v16
; LMULMAX2-NEXT: vadd.vv v10, v10, v18
; LMULMAX2-NEXT: vadd.vv v12, v12, v20
; LMULMAX2-NEXT: vadd.vv v14, v14, v22
-; LMULMAX2-NEXT: vadd.vv v14, v14, v24
-; LMULMAX2-NEXT: vadd.vv v30, v12, v30
-; LMULMAX2-NEXT: vadd.vv v28, v10, v28
-; LMULMAX2-NEXT: vadd.vv v26, v8, v26
-; LMULMAX2-NEXT: vadd.vx v8, v26, a4
-; LMULMAX2-NEXT: vadd.vx v10, v28, a4
-; LMULMAX2-NEXT: vadd.vx v12, v30, a4
+; LMULMAX2-NEXT: vadd.vv v14, v14, v30
+; LMULMAX2-NEXT: vadd.vv v12, v12, v28
+; LMULMAX2-NEXT: vadd.vv v10, v10, v26
+; LMULMAX2-NEXT: vadd.vv v8, v8, v24
+; LMULMAX2-NEXT: vadd.vx v8, v8, a4
+; LMULMAX2-NEXT: vadd.vx v10, v10, a4
+; LMULMAX2-NEXT: vadd.vx v12, v12, a4
; LMULMAX2-NEXT: vadd.vx v14, v14, a4
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v24, (a0)
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle32.v v26, (a1)
+; LMULMAX1-NEXT: vle32.v v25, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
-; LMULMAX1-NEXT: vle32.v v27, (a1)
+; LMULMAX1-NEXT: vle32.v v26, (a1)
; LMULMAX1-NEXT: addi a1, a0, 48
-; LMULMAX1-NEXT: vle32.v v28, (a1)
+; LMULMAX1-NEXT: vle32.v v27, (a1)
; LMULMAX1-NEXT: addi a1, a0, 64
-; LMULMAX1-NEXT: vle32.v v29, (a1)
+; LMULMAX1-NEXT: vle32.v v28, (a1)
; LMULMAX1-NEXT: addi a1, a0, 80
-; LMULMAX1-NEXT: vle32.v v30, (a1)
+; LMULMAX1-NEXT: vle32.v v29, (a1)
; LMULMAX1-NEXT: addi a1, a0, 96
-; LMULMAX1-NEXT: vle32.v v31, (a1)
+; LMULMAX1-NEXT: vle32.v v30, (a1)
; LMULMAX1-NEXT: addi a0, a0, 112
-; LMULMAX1-NEXT: vle32.v v24, (a0)
+; LMULMAX1-NEXT: vle32.v v31, (a0)
; LMULMAX1-NEXT: lw a0, 0(sp)
; LMULMAX1-NEXT: vadd.vv v8, v8, v16
; LMULMAX1-NEXT: vadd.vv v9, v9, v17
@@ -654,21 +654,21 @@ define <32 x i32> @ret_v32i32_param_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32
; LMULMAX1-NEXT: vadd.vv v13, v13, v21
; LMULMAX1-NEXT: vadd.vv v14, v14, v22
; LMULMAX1-NEXT: vadd.vv v15, v15, v23
-; LMULMAX1-NEXT: vadd.vv v15, v15, v24
-; LMULMAX1-NEXT: vadd.vv v31, v14, v31
-; LMULMAX1-NEXT: vadd.vv v30, v13, v30
-; LMULMAX1-NEXT: vadd.vv v29, v12, v29
-; LMULMAX1-NEXT: vadd.vv v28, v11, v28
-; LMULMAX1-NEXT: vadd.vv v27, v10, v27
-; LMULMAX1-NEXT: vadd.vv v26, v9, v26
-; LMULMAX1-NEXT: vadd.vv v25, v8, v25
-; LMULMAX1-NEXT: vadd.vx v8, v25, a0
-; LMULMAX1-NEXT: vadd.vx v9, v26, a0
-; LMULMAX1-NEXT: vadd.vx v10, v27, a0
-; LMULMAX1-NEXT: vadd.vx v11, v28, a0
-; LMULMAX1-NEXT: vadd.vx v12, v29, a0
-; LMULMAX1-NEXT: vadd.vx v13, v30, a0
-; LMULMAX1-NEXT: vadd.vx v14, v31, a0
+; LMULMAX1-NEXT: vadd.vv v15, v15, v31
+; LMULMAX1-NEXT: vadd.vv v14, v14, v30
+; LMULMAX1-NEXT: vadd.vv v13, v13, v29
+; LMULMAX1-NEXT: vadd.vv v12, v12, v28
+; LMULMAX1-NEXT: vadd.vv v11, v11, v27
+; LMULMAX1-NEXT: vadd.vv v10, v10, v26
+; LMULMAX1-NEXT: vadd.vv v9, v9, v25
+; LMULMAX1-NEXT: vadd.vv v8, v8, v24
+; LMULMAX1-NEXT: vadd.vx v8, v8, a0
+; LMULMAX1-NEXT: vadd.vx v9, v9, a0
+; LMULMAX1-NEXT: vadd.vx v10, v10, a0
+; LMULMAX1-NEXT: vadd.vx v11, v11, a0
+; LMULMAX1-NEXT: vadd.vx v12, v12, a0
+; LMULMAX1-NEXT: vadd.vx v13, v13, a0
+; LMULMAX1-NEXT: vadd.vx v14, v14, a0
; LMULMAX1-NEXT: vadd.vx v15, v15, a0
; LMULMAX1-NEXT: ret
%r = add <32 x i32> %x, %y
@@ -704,13 +704,13 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %
; LMULMAX4-NEXT: .cfi_def_cfa_offset 16
; LMULMAX4-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8
-; LMULMAX4-NEXT: vmv4r.v v28, v12
-; LMULMAX4-NEXT: vmv4r.v v24, v8
+; LMULMAX4-NEXT: vmv4r.v v24, v12
+; LMULMAX4-NEXT: vmv4r.v v28, v8
; LMULMAX4-NEXT: addi a1, zero, 2
; LMULMAX4-NEXT: vmv4r.v v8, v16
; LMULMAX4-NEXT: vmv4r.v v12, v20
-; LMULMAX4-NEXT: vmv4r.v v16, v24
-; LMULMAX4-NEXT: vmv4r.v v20, v28
+; LMULMAX4-NEXT: vmv4r.v v16, v28
+; LMULMAX4-NEXT: vmv4r.v v20, v24
; LMULMAX4-NEXT: call ext2 at plt
; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 16
@@ -722,19 +722,19 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %
; LMULMAX2-NEXT: .cfi_def_cfa_offset 16
; LMULMAX2-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LMULMAX2-NEXT: .cfi_offset ra, -8
-; LMULMAX2-NEXT: vmv2r.v v26, v14
-; LMULMAX2-NEXT: vmv2r.v v28, v12
-; LMULMAX2-NEXT: vmv2r.v v30, v10
-; LMULMAX2-NEXT: vmv2r.v v24, v8
+; LMULMAX2-NEXT: vmv2r.v v24, v14
+; LMULMAX2-NEXT: vmv2r.v v26, v12
+; LMULMAX2-NEXT: vmv2r.v v28, v10
+; LMULMAX2-NEXT: vmv2r.v v30, v8
; LMULMAX2-NEXT: addi a1, zero, 2
; LMULMAX2-NEXT: vmv2r.v v8, v16
; LMULMAX2-NEXT: vmv2r.v v10, v18
; LMULMAX2-NEXT: vmv2r.v v12, v20
; LMULMAX2-NEXT: vmv2r.v v14, v22
-; LMULMAX2-NEXT: vmv2r.v v16, v24
-; LMULMAX2-NEXT: vmv2r.v v18, v30
-; LMULMAX2-NEXT: vmv2r.v v20, v28
-; LMULMAX2-NEXT: vmv2r.v v22, v26
+; LMULMAX2-NEXT: vmv2r.v v16, v30
+; LMULMAX2-NEXT: vmv2r.v v18, v28
+; LMULMAX2-NEXT: vmv2r.v v20, v26
+; LMULMAX2-NEXT: vmv2r.v v22, v24
; LMULMAX2-NEXT: call ext2 at plt
; LMULMAX2-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: addi sp, sp, 16
@@ -746,14 +746,14 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %
; LMULMAX1-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; LMULMAX1-NEXT: .cfi_offset ra, -8
-; LMULMAX1-NEXT: vmv1r.v v25, v15
-; LMULMAX1-NEXT: vmv1r.v v26, v14
-; LMULMAX1-NEXT: vmv1r.v v27, v13
-; LMULMAX1-NEXT: vmv1r.v v28, v12
-; LMULMAX1-NEXT: vmv1r.v v29, v11
-; LMULMAX1-NEXT: vmv1r.v v30, v10
-; LMULMAX1-NEXT: vmv1r.v v31, v9
-; LMULMAX1-NEXT: vmv1r.v v24, v8
+; LMULMAX1-NEXT: vmv1r.v v24, v15
+; LMULMAX1-NEXT: vmv1r.v v25, v14
+; LMULMAX1-NEXT: vmv1r.v v26, v13
+; LMULMAX1-NEXT: vmv1r.v v27, v12
+; LMULMAX1-NEXT: vmv1r.v v28, v11
+; LMULMAX1-NEXT: vmv1r.v v29, v10
+; LMULMAX1-NEXT: vmv1r.v v30, v9
+; LMULMAX1-NEXT: vmv1r.v v31, v8
; LMULMAX1-NEXT: addi a1, zero, 2
; LMULMAX1-NEXT: vmv1r.v v8, v16
; LMULMAX1-NEXT: vmv1r.v v9, v17
@@ -763,14 +763,14 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %
; LMULMAX1-NEXT: vmv1r.v v13, v21
; LMULMAX1-NEXT: vmv1r.v v14, v22
; LMULMAX1-NEXT: vmv1r.v v15, v23
-; LMULMAX1-NEXT: vmv1r.v v16, v24
-; LMULMAX1-NEXT: vmv1r.v v17, v31
-; LMULMAX1-NEXT: vmv1r.v v18, v30
-; LMULMAX1-NEXT: vmv1r.v v19, v29
-; LMULMAX1-NEXT: vmv1r.v v20, v28
-; LMULMAX1-NEXT: vmv1r.v v21, v27
-; LMULMAX1-NEXT: vmv1r.v v22, v26
-; LMULMAX1-NEXT: vmv1r.v v23, v25
+; LMULMAX1-NEXT: vmv1r.v v16, v31
+; LMULMAX1-NEXT: vmv1r.v v17, v30
+; LMULMAX1-NEXT: vmv1r.v v18, v29
+; LMULMAX1-NEXT: vmv1r.v v19, v28
+; LMULMAX1-NEXT: vmv1r.v v20, v27
+; LMULMAX1-NEXT: vmv1r.v v21, v26
+; LMULMAX1-NEXT: vmv1r.v v22, v25
+; LMULMAX1-NEXT: vmv1r.v v23, v24
; LMULMAX1-NEXT: call ext2 at plt
; LMULMAX1-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: addi sp, sp, 16
@@ -818,17 +818,17 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (a0)
-; LMULMAX4-NEXT: addi a0, a0, 64
; LMULMAX4-NEXT: vle32.v v24, (a0)
+; LMULMAX4-NEXT: addi a0, a0, 64
+; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: addi a0, sp, 192
; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: addi a0, sp, 128
; LMULMAX4-NEXT: addi a3, zero, 42
; LMULMAX4-NEXT: addi a1, sp, 128
; LMULMAX4-NEXT: vse32.v v8, (a1)
-; LMULMAX4-NEXT: vmv4r.v v8, v28
-; LMULMAX4-NEXT: vmv4r.v v12, v24
+; LMULMAX4-NEXT: vmv4r.v v8, v24
+; LMULMAX4-NEXT: vmv4r.v v12, v28
; LMULMAX4-NEXT: call ext3 at plt
; LMULMAX4-NEXT: addi sp, s0, -384
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -848,13 +848,13 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX2-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-NEXT: andi sp, sp, -128
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v24, (a0)
; LMULMAX2-NEXT: addi a1, a0, 32
-; LMULMAX2-NEXT: vle32.v v28, (a1)
+; LMULMAX2-NEXT: vle32.v v26, (a1)
; LMULMAX2-NEXT: addi a1, a0, 64
-; LMULMAX2-NEXT: vle32.v v30, (a1)
+; LMULMAX2-NEXT: vle32.v v28, (a1)
; LMULMAX2-NEXT: addi a0, a0, 96
-; LMULMAX2-NEXT: vle32.v v24, (a0)
+; LMULMAX2-NEXT: vle32.v v30, (a0)
; LMULMAX2-NEXT: addi a0, sp, 224
; LMULMAX2-NEXT: vse32.v v14, (a0)
; LMULMAX2-NEXT: addi a0, sp, 192
@@ -865,10 +865,10 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX2-NEXT: addi a5, zero, 42
; LMULMAX2-NEXT: addi a1, sp, 128
; LMULMAX2-NEXT: vse32.v v8, (a1)
-; LMULMAX2-NEXT: vmv2r.v v8, v26
-; LMULMAX2-NEXT: vmv2r.v v10, v28
-; LMULMAX2-NEXT: vmv2r.v v12, v30
-; LMULMAX2-NEXT: vmv2r.v v14, v24
+; LMULMAX2-NEXT: vmv2r.v v8, v24
+; LMULMAX2-NEXT: vmv2r.v v10, v26
+; LMULMAX2-NEXT: vmv2r.v v12, v28
+; LMULMAX2-NEXT: vmv2r.v v14, v30
; LMULMAX2-NEXT: call ext3 at plt
; LMULMAX2-NEXT: addi sp, s0, -384
; LMULMAX2-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -888,21 +888,21 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX1-NEXT: .cfi_def_cfa s0, 0
; LMULMAX1-NEXT: andi sp, sp, -128
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v24, (a0)
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle32.v v26, (a1)
+; LMULMAX1-NEXT: vle32.v v25, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
-; LMULMAX1-NEXT: vle32.v v27, (a1)
+; LMULMAX1-NEXT: vle32.v v26, (a1)
; LMULMAX1-NEXT: addi a1, a0, 48
-; LMULMAX1-NEXT: vle32.v v28, (a1)
+; LMULMAX1-NEXT: vle32.v v27, (a1)
; LMULMAX1-NEXT: addi a1, a0, 64
-; LMULMAX1-NEXT: vle32.v v29, (a1)
+; LMULMAX1-NEXT: vle32.v v28, (a1)
; LMULMAX1-NEXT: addi a1, a0, 80
-; LMULMAX1-NEXT: vle32.v v30, (a1)
+; LMULMAX1-NEXT: vle32.v v29, (a1)
; LMULMAX1-NEXT: addi a1, a0, 96
-; LMULMAX1-NEXT: vle32.v v31, (a1)
+; LMULMAX1-NEXT: vle32.v v30, (a1)
; LMULMAX1-NEXT: addi a0, a0, 112
-; LMULMAX1-NEXT: vle32.v v24, (a0)
+; LMULMAX1-NEXT: vle32.v v31, (a0)
; LMULMAX1-NEXT: ld a0, 0(s0)
; LMULMAX1-NEXT: addi a1, sp, 240
; LMULMAX1-NEXT: vse32.v v15, (a1)
@@ -924,14 +924,14 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX1-NEXT: addi a0, sp, 128
; LMULMAX1-NEXT: addi a1, sp, 128
; LMULMAX1-NEXT: vse32.v v8, (a1)
-; LMULMAX1-NEXT: vmv1r.v v8, v25
-; LMULMAX1-NEXT: vmv1r.v v9, v26
-; LMULMAX1-NEXT: vmv1r.v v10, v27
-; LMULMAX1-NEXT: vmv1r.v v11, v28
-; LMULMAX1-NEXT: vmv1r.v v12, v29
-; LMULMAX1-NEXT: vmv1r.v v13, v30
-; LMULMAX1-NEXT: vmv1r.v v14, v31
-; LMULMAX1-NEXT: vmv1r.v v15, v24
+; LMULMAX1-NEXT: vmv1r.v v8, v24
+; LMULMAX1-NEXT: vmv1r.v v9, v25
+; LMULMAX1-NEXT: vmv1r.v v10, v26
+; LMULMAX1-NEXT: vmv1r.v v11, v27
+; LMULMAX1-NEXT: vmv1r.v v12, v28
+; LMULMAX1-NEXT: vmv1r.v v13, v29
+; LMULMAX1-NEXT: vmv1r.v v14, v30
+; LMULMAX1-NEXT: vmv1r.v v15, v31
; LMULMAX1-NEXT: call ext3 at plt
; LMULMAX1-NEXT: addi sp, s0, -384
; LMULMAX1-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -968,9 +968,9 @@ define <32 x i32> @split_vector_args(<2 x i32>,<2 x i32>,<2 x i32>,<2 x i32>,<2
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi a1, a0, 64
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (a0)
+; LMULMAX4-NEXT: vle32.v v8, (a0)
; LMULMAX4-NEXT: vle32.v v12, (a1)
-; LMULMAX4-NEXT: vadd.vv v8, v16, v28
+; LMULMAX4-NEXT: vadd.vv v8, v16, v8
; LMULMAX4-NEXT: vadd.vv v12, v20, v12
; LMULMAX4-NEXT: ret
;
@@ -978,36 +978,36 @@ define <32 x i32> @split_vector_args(<2 x i32>,<2 x i32>,<2 x i32>,<2 x i32>,<2
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, a0, 64
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a0)
; LMULMAX2-NEXT: addi a0, a0, 32
-; LMULMAX2-NEXT: vle32.v v28, (a0)
-; LMULMAX2-NEXT: vle32.v v30, (a1)
+; LMULMAX2-NEXT: vle32.v v12, (a0)
+; LMULMAX2-NEXT: vle32.v v24, (a1)
; LMULMAX2-NEXT: vadd.vv v8, v14, v22
-; LMULMAX2-NEXT: vadd.vv v10, v16, v26
-; LMULMAX2-NEXT: vadd.vv v12, v18, v28
-; LMULMAX2-NEXT: vadd.vv v14, v20, v30
+; LMULMAX2-NEXT: vadd.vv v10, v16, v10
+; LMULMAX2-NEXT: vadd.vv v12, v18, v12
+; LMULMAX2-NEXT: vadd.vv v14, v20, v24
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: split_vector_args:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 64
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v24, (a1)
; LMULMAX1-NEXT: addi a1, a0, 48
-; LMULMAX1-NEXT: vle32.v v26, (a1)
+; LMULMAX1-NEXT: vle32.v v25, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
-; LMULMAX1-NEXT: vle32.v v27, (a1)
+; LMULMAX1-NEXT: vle32.v v26, (a1)
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle32.v v28, (a1)
-; LMULMAX1-NEXT: vle32.v v29, (a0)
+; LMULMAX1-NEXT: vle32.v v12, (a1)
+; LMULMAX1-NEXT: vle32.v v11, (a0)
; LMULMAX1-NEXT: vadd.vv v8, v13, v21
; LMULMAX1-NEXT: vadd.vv v9, v14, v22
; LMULMAX1-NEXT: vadd.vv v10, v15, v23
-; LMULMAX1-NEXT: vadd.vv v11, v16, v29
-; LMULMAX1-NEXT: vadd.vv v12, v17, v28
-; LMULMAX1-NEXT: vadd.vv v13, v18, v27
-; LMULMAX1-NEXT: vadd.vv v14, v19, v26
-; LMULMAX1-NEXT: vadd.vv v15, v20, v25
+; LMULMAX1-NEXT: vadd.vv v11, v16, v11
+; LMULMAX1-NEXT: vadd.vv v12, v17, v12
+; LMULMAX1-NEXT: vadd.vv v13, v18, v26
+; LMULMAX1-NEXT: vadd.vv v14, v19, v25
+; LMULMAX1-NEXT: vadd.vv v15, v20, v24
; LMULMAX1-NEXT: ret
%v0 = add <32 x i32> %y, %z
ret <32 x i32> %v0
@@ -1197,11 +1197,11 @@ define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4,
; LMULMAX4-NEXT: .cfi_def_cfa_offset 16
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: addi a0, sp, 16
-; LMULMAX4-NEXT: vle32.v v28, (a0)
-; LMULMAX4-NEXT: addi a0, sp, 80
; LMULMAX4-NEXT: vle32.v v16, (a0)
-; LMULMAX4-NEXT: vadd.vv v8, v8, v28
-; LMULMAX4-NEXT: vadd.vv v12, v12, v16
+; LMULMAX4-NEXT: addi a0, sp, 80
+; LMULMAX4-NEXT: vle32.v v20, (a0)
+; LMULMAX4-NEXT: vadd.vv v8, v8, v16
+; LMULMAX4-NEXT: vadd.vv v12, v12, v20
; LMULMAX4-NEXT: addi sp, sp, 16
; LMULMAX4-NEXT: ret
;
@@ -1211,17 +1211,17 @@ define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4,
; LMULMAX2-NEXT: .cfi_def_cfa_offset 16
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: addi a0, sp, 16
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v16, (a0)
; LMULMAX2-NEXT: addi a0, sp, 48
-; LMULMAX2-NEXT: vle32.v v28, (a0)
+; LMULMAX2-NEXT: vle32.v v18, (a0)
; LMULMAX2-NEXT: addi a0, sp, 80
-; LMULMAX2-NEXT: vle32.v v30, (a0)
+; LMULMAX2-NEXT: vle32.v v20, (a0)
; LMULMAX2-NEXT: addi a0, sp, 112
-; LMULMAX2-NEXT: vle32.v v16, (a0)
-; LMULMAX2-NEXT: vadd.vv v8, v8, v26
-; LMULMAX2-NEXT: vadd.vv v10, v10, v28
-; LMULMAX2-NEXT: vadd.vv v12, v12, v30
-; LMULMAX2-NEXT: vadd.vv v14, v14, v16
+; LMULMAX2-NEXT: vle32.v v22, (a0)
+; LMULMAX2-NEXT: vadd.vv v8, v8, v16
+; LMULMAX2-NEXT: vadd.vv v10, v10, v18
+; LMULMAX2-NEXT: vadd.vv v12, v12, v20
+; LMULMAX2-NEXT: vadd.vv v14, v14, v22
; LMULMAX2-NEXT: addi sp, sp, 16
; LMULMAX2-NEXT: ret
;
@@ -1231,29 +1231,29 @@ define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4,
; LMULMAX1-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a0, sp, 128
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: addi a0, sp, 112
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v17, (a0)
; LMULMAX1-NEXT: addi a0, sp, 96
-; LMULMAX1-NEXT: vle32.v v27, (a0)
+; LMULMAX1-NEXT: vle32.v v18, (a0)
; LMULMAX1-NEXT: addi a0, sp, 80
-; LMULMAX1-NEXT: vle32.v v28, (a0)
+; LMULMAX1-NEXT: vle32.v v19, (a0)
; LMULMAX1-NEXT: addi a0, sp, 16
-; LMULMAX1-NEXT: vle32.v v29, (a0)
+; LMULMAX1-NEXT: vle32.v v20, (a0)
; LMULMAX1-NEXT: addi a0, sp, 32
-; LMULMAX1-NEXT: vle32.v v30, (a0)
+; LMULMAX1-NEXT: vle32.v v21, (a0)
; LMULMAX1-NEXT: addi a0, sp, 48
-; LMULMAX1-NEXT: vle32.v v31, (a0)
+; LMULMAX1-NEXT: vle32.v v22, (a0)
; LMULMAX1-NEXT: addi a0, sp, 64
-; LMULMAX1-NEXT: vle32.v v16, (a0)
-; LMULMAX1-NEXT: vadd.vv v8, v8, v29
-; LMULMAX1-NEXT: vadd.vv v9, v9, v30
-; LMULMAX1-NEXT: vadd.vv v10, v10, v31
-; LMULMAX1-NEXT: vadd.vv v11, v11, v16
-; LMULMAX1-NEXT: vadd.vv v12, v12, v28
-; LMULMAX1-NEXT: vadd.vv v13, v13, v27
-; LMULMAX1-NEXT: vadd.vv v14, v14, v26
-; LMULMAX1-NEXT: vadd.vv v15, v15, v25
+; LMULMAX1-NEXT: vle32.v v23, (a0)
+; LMULMAX1-NEXT: vadd.vv v8, v8, v20
+; LMULMAX1-NEXT: vadd.vv v9, v9, v21
+; LMULMAX1-NEXT: vadd.vv v10, v10, v22
+; LMULMAX1-NEXT: vadd.vv v11, v11, v23
+; LMULMAX1-NEXT: vadd.vv v12, v12, v19
+; LMULMAX1-NEXT: vadd.vv v13, v13, v18
+; LMULMAX1-NEXT: vadd.vv v14, v14, v17
+; LMULMAX1-NEXT: vadd.vv v15, v15, v16
; LMULMAX1-NEXT: addi sp, sp, 16
; LMULMAX1-NEXT: ret
%s = add <32 x i32> %x, %z
@@ -1441,19 +1441,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX8-NEXT: addi a0, zero, 8
; LMULMAX8-NEXT: sd a0, 128(sp)
; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v25, 0
-; LMULMAX8-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX8-NEXT: vmv.v.i v16, 0
+; LMULMAX8-NEXT: vmerge.vim v16, v16, 1, v0
; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, 0
+; LMULMAX8-NEXT: vmv.v.i v17, 0
; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX8-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX8-NEXT: vslideup.vi v17, v16, 0
; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX8-NEXT: vmsne.vi v25, v26, 0
+; LMULMAX8-NEXT: vmsne.vi v16, v17, 0
; LMULMAX8-NEXT: addi a0, sp, 136
; LMULMAX8-NEXT: addi a5, zero, 5
; LMULMAX8-NEXT: addi a6, zero, 6
; LMULMAX8-NEXT: addi a7, zero, 7
-; LMULMAX8-NEXT: vsm.v v25, (a0)
+; LMULMAX8-NEXT: vsm.v v16, (a0)
; LMULMAX8-NEXT: mv a0, zero
; LMULMAX8-NEXT: mv a1, zero
; LMULMAX8-NEXT: mv a2, zero
@@ -1479,19 +1479,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX4-NEXT: vmv.v.i v25, 0
-; LMULMAX4-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX4-NEXT: vmv.v.i v12, 0
+; LMULMAX4-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vmv.v.i v26, 0
+; LMULMAX4-NEXT: vmv.v.i v13, 0
; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX4-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX4-NEXT: vslideup.vi v13, v12, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vmsne.vi v25, v26, 0
+; LMULMAX4-NEXT: vmsne.vi v12, v13, 0
; LMULMAX4-NEXT: addi a0, sp, 136
; LMULMAX4-NEXT: addi a5, zero, 5
; LMULMAX4-NEXT: addi a6, zero, 6
; LMULMAX4-NEXT: addi a7, zero, 7
-; LMULMAX4-NEXT: vsm.v v25, (a0)
+; LMULMAX4-NEXT: vsm.v v12, (a0)
; LMULMAX4-NEXT: mv a0, zero
; LMULMAX4-NEXT: mv a1, zero
; LMULMAX4-NEXT: mv a2, zero
@@ -1523,19 +1523,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX2-NEXT: addi a0, sp, 32
; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v25, 0
-; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX2-NEXT: vmv.v.i v10, 0
+; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
+; LMULMAX2-NEXT: vmv.v.i v11, 0
; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX2-NEXT: vslideup.vi v11, v10, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
+; LMULMAX2-NEXT: vmsne.vi v10, v11, 0
; LMULMAX2-NEXT: addi a0, sp, 136
; LMULMAX2-NEXT: addi a5, zero, 5
; LMULMAX2-NEXT: addi a6, zero, 6
; LMULMAX2-NEXT: addi a7, zero, 7
-; LMULMAX2-NEXT: vsm.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v10, (a0)
; LMULMAX2-NEXT: mv a0, zero
; LMULMAX2-NEXT: mv a1, zero
; LMULMAX2-NEXT: mv a2, zero
@@ -1579,19 +1579,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v9, 0
+; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
+; LMULMAX1-NEXT: vmsne.vi v9, v10, 0
; LMULMAX1-NEXT: addi a0, sp, 136
; LMULMAX1-NEXT: addi a5, zero, 5
; LMULMAX1-NEXT: addi a6, zero, 6
; LMULMAX1-NEXT: addi a7, zero, 7
-; LMULMAX1-NEXT: vsm.v v25, (a0)
+; LMULMAX1-NEXT: vsm.v v9, (a0)
; LMULMAX1-NEXT: mv a0, zero
; LMULMAX1-NEXT: mv a1, zero
; LMULMAX1-NEXT: mv a2, zero
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index f063bf0836ec2..6cf58c8b0e7b0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -10,8 +10,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle8.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -47,8 +47,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: addi a5, a5, -24
; LMULMAX2-RV32-NEXT: sb a5, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX2-RV32-NEXT: andi a5, a5, 255
; LMULMAX2-RV32-NEXT: srli a1, a5, 1
; LMULMAX2-RV32-NEXT: or a1, a5, a1
@@ -75,8 +75,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 31(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -103,8 +103,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 30(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -131,8 +131,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 29(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -159,8 +159,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -187,8 +187,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 27(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -215,8 +215,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 26(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -243,8 +243,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 25(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -271,8 +271,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -299,8 +299,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 23(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -327,8 +327,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 22(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -355,8 +355,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 21(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -383,8 +383,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 20(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -411,8 +411,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 19(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -439,8 +439,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 18(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
@@ -469,8 +469,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: sb a1, 17(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle8.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse8.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -479,8 +479,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle8.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -540,8 +540,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: addiw a5, a5, -56
; LMULMAX2-RV64-NEXT: sb a5, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX2-RV64-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX2-RV64-NEXT: vmv.x.s a5, v9
; LMULMAX2-RV64-NEXT: andi a5, a5, 255
; LMULMAX2-RV64-NEXT: srli a1, a5, 1
; LMULMAX2-RV64-NEXT: or a1, a5, a1
@@ -570,8 +570,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 31(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -600,8 +600,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 30(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -630,8 +630,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 29(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -660,8 +660,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -690,8 +690,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 27(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -720,8 +720,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 26(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -750,8 +750,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 25(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -780,8 +780,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -810,8 +810,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 23(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -840,8 +840,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 22(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -870,8 +870,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 21(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -900,8 +900,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 20(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -930,8 +930,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 19(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -960,8 +960,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 18(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
@@ -992,8 +992,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: sb a1, 17(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle8.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse8.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -1002,8 +1002,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -1039,8 +1039,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: addi a5, a5, -24
; LMULMAX1-RV32-NEXT: sb a5, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX1-RV32-NEXT: andi a5, a5, 255
; LMULMAX1-RV32-NEXT: srli a1, a5, 1
; LMULMAX1-RV32-NEXT: or a1, a5, a1
@@ -1067,8 +1067,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 31(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1095,8 +1095,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1123,8 +1123,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1151,8 +1151,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1179,8 +1179,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1207,8 +1207,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1235,8 +1235,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1263,8 +1263,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1291,8 +1291,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1319,8 +1319,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1347,8 +1347,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1375,8 +1375,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1403,8 +1403,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1431,8 +1431,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
@@ -1461,8 +1461,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: sb a1, 17(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -1471,8 +1471,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -1532,8 +1532,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: addiw a5, a5, -56
; LMULMAX1-RV64-NEXT: sb a5, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV64-NEXT: vmv.x.s a5, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV64-NEXT: vmv.x.s a5, v9
; LMULMAX1-RV64-NEXT: andi a5, a5, 255
; LMULMAX1-RV64-NEXT: srli a1, a5, 1
; LMULMAX1-RV64-NEXT: or a1, a5, a1
@@ -1562,8 +1562,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 31(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1592,8 +1592,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1622,8 +1622,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1652,8 +1652,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1682,8 +1682,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1712,8 +1712,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1742,8 +1742,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1772,8 +1772,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1802,8 +1802,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1832,8 +1832,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1862,8 +1862,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1892,8 +1892,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1922,8 +1922,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1952,8 +1952,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a5, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a5
@@ -1984,8 +1984,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: sb a1, 17(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
@@ -2002,8 +2002,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a6, a1, -1
; LMULMAX2-RV32-NEXT: and a2, a2, a6
@@ -2041,8 +2041,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -2069,8 +2069,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 30(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -2097,8 +2097,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -2125,8 +2125,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 26(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -2153,8 +2153,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -2181,8 +2181,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 22(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -2209,8 +2209,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 20(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -2239,8 +2239,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: sh a1, 18(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -2249,8 +2249,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a6, a1, -1
; LMULMAX2-RV64-NEXT: and a2, a2, a6
@@ -2312,8 +2312,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -2342,8 +2342,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 30(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -2372,8 +2372,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -2402,8 +2402,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 26(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -2432,8 +2432,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -2462,8 +2462,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 22(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -2492,8 +2492,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 20(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -2524,8 +2524,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: sh a1, 18(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -2534,8 +2534,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: lui a1, 16
; LMULMAX1-RV32-NEXT: addi a6, a1, -1
; LMULMAX1-RV32-NEXT: and a2, a2, a6
@@ -2573,8 +2573,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: addi a1, a1, -16
; LMULMAX1-RV32-NEXT: sh a1, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: and a1, a1, a6
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -2601,8 +2601,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -16
; LMULMAX1-RV32-NEXT: sh a1, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: and a1, a1, a6
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -2629,8 +2629,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -16
; LMULMAX1-RV32-NEXT: sh a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: and a1, a1, a6
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -2657,8 +2657,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -16
; LMULMAX1-RV32-NEXT: sh a1, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: and a1, a1, a6
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -2685,8 +2685,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -16
; LMULMAX1-RV32-NEXT: sh a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: and a1, a1, a6
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -2713,8 +2713,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -16
; LMULMAX1-RV32-NEXT: sh a1, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: and a1, a1, a6
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -2741,8 +2741,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -16
; LMULMAX1-RV32-NEXT: sh a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: and a1, a1, a6
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -2771,8 +2771,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: sh a1, 18(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -2781,8 +2781,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: lui a1, 16
; LMULMAX1-RV64-NEXT: addiw a6, a1, -1
; LMULMAX1-RV64-NEXT: and a2, a2, a6
@@ -2844,8 +2844,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: and a1, a1, a6
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -2874,8 +2874,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: and a1, a1, a6
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -2904,8 +2904,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: and a1, a1, a6
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -2934,8 +2934,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: and a1, a1, a6
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -2964,8 +2964,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: and a1, a1, a6
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -2994,8 +2994,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: and a1, a1, a6
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -3024,8 +3024,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -48
; LMULMAX1-RV64-NEXT: sh a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: and a1, a1, a6
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -3056,8 +3056,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: sh a1, 18(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
@@ -3074,8 +3074,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a2, a1, 2
@@ -3109,8 +3109,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: srli a5, a5, 24
; LMULMAX2-RV32-NEXT: sw a5, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX2-RV32-NEXT: srli a1, a5, 1
; LMULMAX2-RV32-NEXT: or a1, a5, a1
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -3135,8 +3135,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -3161,8 +3161,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -3189,8 +3189,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 20(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -3199,8 +3199,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srliw a2, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -3261,8 +3261,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: addiw a5, a5, -32
; LMULMAX2-RV64-NEXT: sw a5, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a5, v9
; LMULMAX2-RV64-NEXT: srliw a1, a5, 1
; LMULMAX2-RV64-NEXT: slli a5, a5, 32
; LMULMAX2-RV64-NEXT: srli a5, a5, 32
@@ -3292,8 +3292,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -3323,8 +3323,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -3356,8 +3356,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: sw a1, 20(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -3366,8 +3366,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -3401,8 +3401,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: srli a5, a5, 24
; LMULMAX1-RV32-NEXT: sw a5, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX1-RV32-NEXT: srli a1, a5, 1
; LMULMAX1-RV32-NEXT: or a1, a5, a1
; LMULMAX1-RV32-NEXT: srli a5, a1, 2
@@ -3427,8 +3427,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a5, a1, 2
@@ -3453,8 +3453,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a5, a1, 2
@@ -3481,8 +3481,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -3491,8 +3491,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -3553,8 +3553,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: addiw a5, a5, -32
; LMULMAX1-RV64-NEXT: sw a5, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a5, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a5, v9
; LMULMAX1-RV64-NEXT: srliw a1, a5, 1
; LMULMAX1-RV64-NEXT: slli a5, a5, 32
; LMULMAX1-RV64-NEXT: srli a5, a5, 32
@@ -3584,8 +3584,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a5, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -3615,8 +3615,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a5, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -3648,8 +3648,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: sw a1, 20(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
@@ -3666,13 +3666,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: sw zero, 28(sp)
; LMULMAX2-RV32-NEXT: sw zero, 20(sp)
; LMULMAX2-RV32-NEXT: addi a6, zero, 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a4, a1, 1365
; LMULMAX2-RV32-NEXT: lui a1, 209715
@@ -3683,7 +3683,7 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: addi a2, a1, 257
; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_2
; LMULMAX2-RV32-NEXT: # %bb.1:
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -3734,13 +3734,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
; LMULMAX2-RV32-NEXT: .LBB3_3:
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: sw a5, 16(sp)
; LMULMAX2-RV32-NEXT: bnez a1, .LBB3_5
; LMULMAX2-RV32-NEXT: # %bb.4:
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -3794,19 +3794,19 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 24(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: ctlz_v2i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: srli a2, a1, 2
@@ -3863,8 +3863,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srli a3, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a3
; LMULMAX2-RV64-NEXT: srli a3, a1, 2
@@ -3891,8 +3891,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmv.s.x v9, a1
+; LMULMAX2-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ctlz_v2i64:
@@ -3900,13 +3900,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: sw zero, 28(sp)
; LMULMAX1-RV32-NEXT: sw zero, 20(sp)
; LMULMAX1-RV32-NEXT: addi a6, zero, 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX1-RV32-NEXT: lui a1, 349525
; LMULMAX1-RV32-NEXT: addi a4, a1, 1365
; LMULMAX1-RV32-NEXT: lui a1, 209715
@@ -3917,7 +3917,7 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi a2, a1, 257
; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_2
; LMULMAX1-RV32-NEXT: # %bb.1:
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a5, a1, 2
@@ -3968,13 +3968,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
; LMULMAX1-RV32-NEXT: .LBB3_3:
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: sw a5, 16(sp)
; LMULMAX1-RV32-NEXT: bnez a1, .LBB3_5
; LMULMAX1-RV32-NEXT: # %bb.4:
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a5, a1, 2
@@ -4028,19 +4028,19 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ctlz_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: srli a2, a1, 2
@@ -4097,8 +4097,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srli a3, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a3
; LMULMAX1-RV64-NEXT: srli a3, a1, 2
@@ -4125,8 +4125,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -4150,8 +4150,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: addi a6, zero, 32
; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle8.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: andi a2, a2, 255
; LMULMAX2-RV32-NEXT: srli a3, a2, 1
; LMULMAX2-RV32-NEXT: or a2, a2, a3
@@ -4187,8 +4187,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 31
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 31
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4215,8 +4215,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 63(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 30
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 30
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4243,8 +4243,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 62(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 29
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 29
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4271,8 +4271,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 61(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 28
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 28
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4299,8 +4299,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 27
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 27
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4327,8 +4327,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 59(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 26
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 26
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4355,8 +4355,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 58(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 25
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 25
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4383,8 +4383,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 57(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 24
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 24
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4411,8 +4411,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 23
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 23
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4439,8 +4439,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 55(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 22
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 22
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4467,8 +4467,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 54(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 21
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 21
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4495,8 +4495,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 53(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 20
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 20
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4523,8 +4523,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 19
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 19
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4551,8 +4551,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 51(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 18
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 18
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4579,8 +4579,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 50(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 17
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 17
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4607,8 +4607,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 49(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 16
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 16
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4635,8 +4635,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4663,8 +4663,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 47(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4691,8 +4691,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 46(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4719,8 +4719,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 45(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4747,8 +4747,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4775,8 +4775,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 43(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4803,8 +4803,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 42(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4831,8 +4831,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 41(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4859,8 +4859,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4887,8 +4887,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 39(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4915,8 +4915,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 38(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4943,8 +4943,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 37(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4971,8 +4971,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 36(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -4999,8 +4999,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 35(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -5027,8 +5027,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -24
; LMULMAX2-RV32-NEXT: sb a1, 34(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: andi a1, a1, 255
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -5057,8 +5057,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: sb a1, 33(sp)
; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle8.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -5078,8 +5078,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: addi a6, zero, 32
; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle8.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV64-NEXT: andi a2, a2, 255
; LMULMAX2-RV64-NEXT: srli a3, a2, 1
; LMULMAX2-RV64-NEXT: or a2, a2, a3
@@ -5139,8 +5139,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 31
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 31
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5169,8 +5169,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 63(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 30
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 30
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5199,8 +5199,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 62(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 29
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 29
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5229,8 +5229,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 61(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 28
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 28
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5259,8 +5259,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 27
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 27
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5289,8 +5289,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 59(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 26
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 26
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5319,8 +5319,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 58(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 25
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 25
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5349,8 +5349,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 57(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 24
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 24
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5379,8 +5379,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 23
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 23
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5409,8 +5409,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 55(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 22
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 22
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5439,8 +5439,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 54(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 21
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 21
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5469,8 +5469,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 53(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 20
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 20
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5499,8 +5499,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 19
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 19
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5529,8 +5529,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 51(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 18
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 18
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5559,8 +5559,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 50(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 17
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 17
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5589,8 +5589,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 49(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 16
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 16
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5619,8 +5619,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5649,8 +5649,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 47(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5679,8 +5679,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 46(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5709,8 +5709,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 45(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5739,8 +5739,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5769,8 +5769,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 43(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5799,8 +5799,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 42(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5829,8 +5829,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 41(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5859,8 +5859,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5889,8 +5889,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 39(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5919,8 +5919,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 38(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5949,8 +5949,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 37(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -5979,8 +5979,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 36(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -6009,8 +6009,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 35(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -6039,8 +6039,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -56
; LMULMAX2-RV64-NEXT: sb a1, 34(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: andi a1, a1, 255
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -6071,8 +6071,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: sb a1, 33(sp)
; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle8.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -6085,9 +6085,9 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: andi a2, a2, 255
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -6123,8 +6123,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 15
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 15
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6151,8 +6151,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 47(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 14
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 14
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6179,8 +6179,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 46(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 13
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 13
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6207,8 +6207,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 45(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 12
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 12
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6235,8 +6235,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 11
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 11
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6263,8 +6263,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 43(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 10
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 10
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6291,8 +6291,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 42(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 9
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 9
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6319,8 +6319,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 41(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 8
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 8
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6347,8 +6347,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6375,8 +6375,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 39(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6403,8 +6403,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 38(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6431,8 +6431,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 37(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6459,8 +6459,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 36(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6487,8 +6487,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 35(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6515,8 +6515,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 34(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6543,7 +6543,7 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 33(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6570,8 +6570,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6598,8 +6598,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 31(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6626,8 +6626,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6654,8 +6654,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6682,8 +6682,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6710,8 +6710,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6738,8 +6738,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6766,8 +6766,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6794,8 +6794,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6822,8 +6822,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6850,8 +6850,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6878,8 +6878,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6906,8 +6906,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6934,8 +6934,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6962,8 +6962,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: addi a1, a1, -24
; LMULMAX1-RV32-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: andi a1, a1, 255
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
@@ -6992,11 +6992,11 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: sb a1, 17(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -7006,9 +7006,9 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: andi a2, a2, 255
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -7068,8 +7068,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 15
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 15
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7098,8 +7098,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 47(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 14
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 14
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7128,8 +7128,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 46(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 13
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 13
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7158,8 +7158,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 45(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 12
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 12
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7188,8 +7188,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 11
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 11
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7218,8 +7218,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 43(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 10
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 10
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7248,8 +7248,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 42(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 9
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 9
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7278,8 +7278,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 41(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 8
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 8
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7308,8 +7308,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7338,8 +7338,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 39(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7368,8 +7368,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 38(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7398,8 +7398,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 37(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7428,8 +7428,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 36(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7458,8 +7458,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 35(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7488,8 +7488,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 34(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7518,7 +7518,7 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 33(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7547,8 +7547,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 16(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7577,8 +7577,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 31(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7607,8 +7607,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7637,8 +7637,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7667,8 +7667,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7697,8 +7697,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7727,8 +7727,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7757,8 +7757,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7787,8 +7787,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7817,8 +7817,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7847,8 +7847,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7877,8 +7877,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7907,8 +7907,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7937,8 +7937,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7967,8 +7967,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -56
; LMULMAX1-RV64-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: andi a1, a1, 255
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
@@ -7999,11 +7999,11 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: sb a1, 17(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, sp, 32
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a6)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
@@ -8027,8 +8027,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a6, a1, -1
; LMULMAX2-RV32-NEXT: and a2, a2, a6
@@ -8066,8 +8066,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8094,8 +8094,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 62(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8122,8 +8122,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8150,8 +8150,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 58(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8178,8 +8178,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8206,8 +8206,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 54(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8234,8 +8234,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8262,8 +8262,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 50(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8290,8 +8290,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8318,8 +8318,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 46(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8346,8 +8346,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8374,8 +8374,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 42(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8402,8 +8402,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8430,8 +8430,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 38(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8458,8 +8458,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: addi a1, a1, -16
; LMULMAX2-RV32-NEXT: sh a1, 36(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: and a1, a1, a6
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
@@ -8488,8 +8488,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: sh a1, 34(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -8508,8 +8508,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a6, a1, -1
; LMULMAX2-RV64-NEXT: and a2, a2, a6
@@ -8571,8 +8571,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8601,8 +8601,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 62(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8631,8 +8631,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8661,8 +8661,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 58(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8691,8 +8691,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8721,8 +8721,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 54(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8751,8 +8751,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8781,8 +8781,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 50(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8811,8 +8811,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8841,8 +8841,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 46(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8871,8 +8871,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8901,8 +8901,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 42(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8931,8 +8931,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8961,8 +8961,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 38(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -8991,8 +8991,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -48
; LMULMAX2-RV64-NEXT: sh a1, 36(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: and a1, a1, a6
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
@@ -9023,8 +9023,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: sh a1, 34(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -9037,9 +9037,9 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a7, a2, -1
; LMULMAX1-RV32-NEXT: and a1, a1, a7
@@ -9077,8 +9077,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9105,8 +9105,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 46(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9133,8 +9133,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9161,8 +9161,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 42(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9189,8 +9189,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9217,8 +9217,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 38(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9245,8 +9245,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 36(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9273,7 +9273,7 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 34(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9300,8 +9300,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9328,8 +9328,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9356,8 +9356,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9384,8 +9384,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9412,8 +9412,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9440,8 +9440,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9468,8 +9468,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: addi a2, a2, -16
; LMULMAX1-RV32-NEXT: sh a2, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: and a2, a2, a7
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
@@ -9498,11 +9498,11 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: sh a1, 18(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -9512,9 +9512,9 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a7, a2, -1
; LMULMAX1-RV64-NEXT: and a1, a1, a7
@@ -9576,8 +9576,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9606,8 +9606,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 46(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9636,8 +9636,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9666,8 +9666,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 42(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9696,8 +9696,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9726,8 +9726,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 38(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9756,8 +9756,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 36(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9786,7 +9786,7 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 34(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9815,8 +9815,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 16(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9845,8 +9845,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9875,8 +9875,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9905,8 +9905,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9935,8 +9935,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9965,8 +9965,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -9995,8 +9995,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: addiw a2, a2, -48
; LMULMAX1-RV64-NEXT: sh a2, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: and a2, a2, a7
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
@@ -10027,11 +10027,11 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: sh a1, 18(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, sp, 32
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a6)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
@@ -10055,8 +10055,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a2, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a2, a1, 2
@@ -10090,8 +10090,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: srli a5, a5, 24
; LMULMAX2-RV32-NEXT: sw a5, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10
; LMULMAX2-RV32-NEXT: srli a1, a5, 1
; LMULMAX2-RV32-NEXT: or a1, a5, a1
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -10116,8 +10116,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -10142,8 +10142,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -10168,8 +10168,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -10194,8 +10194,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -10220,8 +10220,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -10246,8 +10246,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -10274,8 +10274,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 36(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -10294,8 +10294,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srliw a2, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -10356,8 +10356,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: addiw a5, a5, -32
; LMULMAX2-RV64-NEXT: sw a5, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a5, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a5, v10
; LMULMAX2-RV64-NEXT: srliw a1, a5, 1
; LMULMAX2-RV64-NEXT: slli a5, a5, 32
; LMULMAX2-RV64-NEXT: srli a5, a5, 32
@@ -10387,8 +10387,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -10418,8 +10418,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -10449,8 +10449,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -10480,8 +10480,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -10511,8 +10511,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -10542,8 +10542,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: addiw a1, a1, -32
; LMULMAX2-RV64-NEXT: sw a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srliw a5, a1, 1
; LMULMAX2-RV64-NEXT: slli a1, a1, 32
; LMULMAX2-RV64-NEXT: srli a1, a1, 32
@@ -10575,8 +10575,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: sw a1, 36(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -10589,9 +10589,9 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: srli a3, a2, 1
; LMULMAX1-RV32-NEXT: or a2, a2, a3
; LMULMAX1-RV32-NEXT: srli a3, a2, 2
@@ -10625,8 +10625,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -10651,8 +10651,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -10677,8 +10677,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -10703,7 +10703,7 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 36(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -10728,8 +10728,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -10754,8 +10754,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -10780,8 +10780,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -10808,11 +10808,11 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -10822,9 +10822,9 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: srliw a3, a2, 1
; LMULMAX1-RV64-NEXT: slli a2, a2, 32
; LMULMAX1-RV64-NEXT: srli a2, a2, 32
@@ -10885,8 +10885,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -10916,8 +10916,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -10947,8 +10947,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -10978,7 +10978,7 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 36(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -11008,8 +11008,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 16(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -11039,8 +11039,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -11070,8 +11070,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: addiw a1, a1, -32
; LMULMAX1-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srliw a2, a1, 1
; LMULMAX1-RV64-NEXT: slli a1, a1, 32
; LMULMAX1-RV64-NEXT: srli a1, a1, 32
@@ -11103,11 +11103,11 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: sw a1, 20(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, sp, 32
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a6)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
@@ -11131,15 +11131,15 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: sw zero, 60(sp)
; LMULMAX2-RV32-NEXT: sw zero, 52(sp)
; LMULMAX2-RV32-NEXT: sw zero, 44(sp)
; LMULMAX2-RV32-NEXT: sw zero, 36(sp)
; LMULMAX2-RV32-NEXT: addi a6, zero, 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28
+; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a4, a1, 1365
; LMULMAX2-RV32-NEXT: lui a1, 209715
@@ -11150,7 +11150,7 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: addi a2, a1, 257
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_2
; LMULMAX2-RV32-NEXT: # %bb.1:
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -11201,13 +11201,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
; LMULMAX2-RV32-NEXT: .LBB7_3:
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vsrl.vx v30, v28, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v30
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vsrl.vx v12, v10, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v12
; LMULMAX2-RV32-NEXT: sw a5, 32(sp)
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_5
; LMULMAX2-RV32-NEXT: # %bb.4:
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -11258,13 +11258,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
; LMULMAX2-RV32-NEXT: .LBB7_6:
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vsrl.vx v30, v28, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v30
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vsrl.vx v12, v10, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v12
; LMULMAX2-RV32-NEXT: sw a5, 56(sp)
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_8
; LMULMAX2-RV32-NEXT: # %bb.7:
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -11315,13 +11315,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
; LMULMAX2-RV32-NEXT: .LBB7_9:
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: sw a5, 48(sp)
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_11
; LMULMAX2-RV32-NEXT: # %bb.10:
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
; LMULMAX2-RV32-NEXT: or a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
@@ -11375,9 +11375,9 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 40(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -11396,8 +11396,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srli a2, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: srli a2, a1, 2
@@ -11455,8 +11455,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: srli a5, a5, 56
; LMULMAX2-RV64-NEXT: sd a5, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a5, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a5, v10
; LMULMAX2-RV64-NEXT: srli a1, a5, 1
; LMULMAX2-RV64-NEXT: or a1, a5, a1
; LMULMAX2-RV64-NEXT: srli a5, a1, 2
@@ -11483,8 +11483,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sd a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a5, a1, 2
@@ -11511,8 +11511,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sd a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: srli a5, a1, 1
; LMULMAX2-RV64-NEXT: or a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a5, a1, 2
@@ -11541,8 +11541,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: sd a1, 40(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -11554,15 +11554,15 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -48
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a6)
; LMULMAX1-RV32-NEXT: sw zero, 44(sp)
; LMULMAX1-RV32-NEXT: sw zero, 36(sp)
; LMULMAX1-RV32-NEXT: addi a7, zero, 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsrl.vx v27, v26, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: lui a2, 349525
; LMULMAX1-RV32-NEXT: addi a5, a2, 1365
; LMULMAX1-RV32-NEXT: lui a2, 209715
@@ -11573,7 +11573,7 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi a3, a2, 257
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_2
; LMULMAX1-RV32-NEXT: # %bb.1:
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -11624,13 +11624,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a3
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: .LBB7_3:
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vsrl.vx v27, v26, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: sw a1, 32(sp)
; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_5
; LMULMAX1-RV32-NEXT: # %bb.4:
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -11683,12 +11683,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: .LBB7_6:
; LMULMAX1-RV32-NEXT: sw a1, 40(sp)
; LMULMAX1-RV32-NEXT: sw zero, 28(sp)
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: sw zero, 20(sp)
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_8
; LMULMAX1-RV32-NEXT: # %bb.7:
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -11739,13 +11739,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a3
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: .LBB7_9:
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_11
; LMULMAX1-RV32-NEXT: # %bb.10:
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
; LMULMAX1-RV32-NEXT: or a1, a1, a2
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
@@ -11799,12 +11799,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -11812,11 +11812,11 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a6)
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a6)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v27, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v10, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: srli a3, a2, 1
; LMULMAX1-RV64-NEXT: or a2, a2, a3
; LMULMAX1-RV64-NEXT: srli a3, a2, 2
@@ -11873,8 +11873,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: srli a2, a1, 2
@@ -11901,10 +11901,10 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
+; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: srli a2, a1, 2
@@ -11931,8 +11931,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v27, a1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.v.x v10, a1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: srli a2, a1, 2
@@ -11959,9 +11959,9 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
-; LMULMAX1-RV64-NEXT: vse64.v v27, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vmv.s.x v10, a1
+; LMULMAX1-RV64-NEXT: vse64.v v10, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a6)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
index 1412d6a54d6d2..3a337724d35ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
@@ -8,20 +8,20 @@ define void @ctpop_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: ctpop_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsrl.vi v26, v25, 1
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsrl.vi v9, v8, 1
; CHECK-NEXT: addi a1, zero, 85
-; CHECK-NEXT: vand.vx v26, v26, a1
-; CHECK-NEXT: vsub.vv v25, v25, v26
+; CHECK-NEXT: vand.vx v9, v9, a1
+; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: addi a1, zero, 51
-; CHECK-NEXT: vand.vx v26, v25, a1
-; CHECK-NEXT: vsrl.vi v25, v25, 2
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vadd.vv v25, v26, v25
-; CHECK-NEXT: vsrl.vi v26, v25, 4
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vand.vi v25, v25, 15
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vand.vx v9, v8, a1
+; CHECK-NEXT: vsrl.vi v8, v8, 2
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vadd.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 4
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -35,105 +35,105 @@ define void @ctpop_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-LABEL: ctpop_v8i16:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 5
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsub.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 3
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v26, v25, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vand.vx v9, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 1
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV32-NEXT: addi a1, zero, 257
-; LMULMAX2-RV32-NEXT: vmul.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 8
-; LMULMAX2-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: ctpop_v8i16:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 5
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsub.vv v25, v25, v26
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v9
; LMULMAX2-RV64-NEXT: lui a1, 3
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v26, v25, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v26
+; LMULMAX2-RV64-NEXT: vand.vx v9, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v9
; LMULMAX2-RV64-NEXT: lui a1, 1
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: addi a1, zero, 257
-; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 8
-; LMULMAX2-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ctpop_v8i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: lui a1, 5
; LMULMAX1-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 3
; LMULMAX1-RV32-NEXT: addi a1, a1, 819
-; LMULMAX1-RV32-NEXT: vand.vx v26, v25, a1
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vand.vx v9, v8, a1
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 1
; LMULMAX1-RV32-NEXT: addi a1, a1, -241
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
; LMULMAX1-RV32-NEXT: addi a1, zero, 257
-; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 8
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ctpop_v8i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV64-NEXT: lui a1, 5
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: lui a1, 3
; LMULMAX1-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX1-RV64-NEXT: vand.vx v26, v25, a1
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
+; LMULMAX1-RV64-NEXT: vand.vx v9, v8, a1
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: lui a1, 1
; LMULMAX1-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX1-RV64-NEXT: addi a1, zero, 257
-; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 8
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -147,109 +147,109 @@ define void @ctpop_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-LABEL: ctpop_v4i32:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsub.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v26, v25, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v26, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vand.vx v9, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v9, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV32-NEXT: lui a1, 4112
; LMULMAX2-RV32-NEXT: addi a1, a1, 257
-; LMULMAX2-RV32-NEXT: vmul.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 24
-; LMULMAX2-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: ctpop_v4i32:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 349525
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsub.vv v25, v25, v26
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v9
; LMULMAX2-RV64-NEXT: lui a1, 209715
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v26, v25, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v26
+; LMULMAX2-RV64-NEXT: vand.vx v9, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v9
; LMULMAX2-RV64-NEXT: lui a1, 61681
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: lui a1, 4112
; LMULMAX2-RV64-NEXT: addiw a1, a1, 257
-; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 24
-; LMULMAX2-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ctpop_v4i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: lui a1, 349525
; LMULMAX1-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 209715
; LMULMAX1-RV32-NEXT: addi a1, a1, 819
-; LMULMAX1-RV32-NEXT: vand.vx v26, v25, a1
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v26, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vand.vx v9, v8, a1
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v9, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 61681
; LMULMAX1-RV32-NEXT: addi a1, a1, -241
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1
; LMULMAX1-RV32-NEXT: lui a1, 4112
; LMULMAX1-RV32-NEXT: addi a1, a1, 257
-; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 24
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ctpop_v4i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV64-NEXT: lui a1, 349525
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: lui a1, 209715
; LMULMAX1-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX1-RV64-NEXT: vand.vx v26, v25, a1
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
+; LMULMAX1-RV64-NEXT: vand.vx v9, v8, a1
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: lui a1, 61681
; LMULMAX1-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX1-RV64-NEXT: lui a1, 4112
; LMULMAX1-RV64-NEXT: addiw a1, a1, 257
-; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 24
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -263,48 +263,48 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-LABEL: ctpop_v2i64:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX2-RV32-NEXT: vsub.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v26, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v27, v25, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v26
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v27, v25
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vand.vv v10, v8, v9
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v9
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v26, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: lui a1, 4112
; LMULMAX2-RV32-NEXT: addi a1, a1, 257
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v26, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vmul.vv v25, v25, v26
+; LMULMAX2-RV32-NEXT: vmul.vv v8, v8, v9
; LMULMAX2-RV32-NEXT: addi a1, zero, 56
-; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a1
-; LMULMAX2-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: ctpop_v2i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v25, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 21845
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -313,8 +313,8 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsub.vv v25, v25, v26
+; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v9
; LMULMAX2-RV64-NEXT: lui a1, 13107
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -323,12 +323,12 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v26, v25, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v26, v25
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v26
+; LMULMAX2-RV64-NEXT: vand.vx v9, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v9, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v9
; LMULMAX2-RV64-NEXT: lui a1, 3855
; LMULMAX2-RV64-NEXT: addiw a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -337,64 +337,64 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: lui a1, 4112
; LMULMAX2-RV64-NEXT: addiw a1, a1, 257
; LMULMAX2-RV64-NEXT: slli a1, a1, 16
; LMULMAX2-RV64-NEXT: addi a1, a1, 257
; LMULMAX2-RV64-NEXT: slli a1, a1, 16
; LMULMAX2-RV64-NEXT: addi a1, a1, 257
-; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1
+; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: addi a1, zero, 56
-; LMULMAX2-RV64-NEXT: vsrl.vx v25, v25, a1
-; LMULMAX2-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ctpop_v2i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: lui a1, 349525
; LMULMAX1-RV32-NEXT: addi a1, a1, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 209715
; LMULMAX1-RV32-NEXT: addi a1, a1, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v26, a1
+; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v27, v25, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v26
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vand.vv v10, v8, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v9
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 61681
; LMULMAX1-RV32-NEXT: addi a1, a1, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v26, a1
+; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: lui a1, 4112
; LMULMAX1-RV32-NEXT: addi a1, a1, 257
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v26, a1
+; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v26
+; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: addi a1, zero, 56
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a1
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ctpop_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV64-NEXT: lui a1, 21845
; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
@@ -403,8 +403,8 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: lui a1, 13107
; LMULMAX1-RV64-NEXT: addiw a1, a1, 819
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
@@ -413,12 +413,12 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a1, a1, 819
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, 819
-; LMULMAX1-RV64-NEXT: vand.vx v26, v25, a1
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v26, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26
+; LMULMAX1-RV64-NEXT: vand.vx v9, v8, a1
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v9, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: lui a1, 3855
; LMULMAX1-RV64-NEXT: addiw a1, a1, 241
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
@@ -427,17 +427,17 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a1, a1, 241
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -241
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX1-RV64-NEXT: lui a1, 4112
; LMULMAX1-RV64-NEXT: addiw a1, a1, 257
; LMULMAX1-RV64-NEXT: slli a1, a1, 16
; LMULMAX1-RV64-NEXT: addi a1, a1, 257
; LMULMAX1-RV64-NEXT: slli a1, a1, 16
; LMULMAX1-RV64-NEXT: addi a1, a1, 257
-; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1
+; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a1
; LMULMAX1-RV64-NEXT: addi a1, zero, 56
-; LMULMAX1-RV64-NEXT: vsrl.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -452,52 +452,52 @@ define void @ctpop_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-NEXT: addi a1, zero, 85
-; LMULMAX2-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-NEXT: addi a1, zero, 51
-; LMULMAX2-NEXT: vand.vx v28, v26, a1
-; LMULMAX2-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX2-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-NEXT: vsrl.vi v28, v26, 4
-; LMULMAX2-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vand.vi v26, v26, 15
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vand.vx v10, v8, a1
+; LMULMAX2-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX2-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vand.vi v8, v8, 15
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: ctpop_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle8.v v25, (a1)
-; LMULMAX1-NEXT: vle8.v v26, (a0)
-; LMULMAX1-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-NEXT: vle8.v v8, (a1)
+; LMULMAX1-NEXT: vle8.v v9, (a0)
+; LMULMAX1-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-NEXT: addi a2, zero, 85
-; LMULMAX1-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-NEXT: vsub.vv v25, v25, v27
+; LMULMAX1-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-NEXT: addi a3, zero, 51
-; LMULMAX1-NEXT: vand.vx v27, v25, a3
-; LMULMAX1-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-NEXT: vsrl.vi v27, v25, 4
-; LMULMAX1-NEXT: vadd.vv v25, v25, v27
-; LMULMAX1-NEXT: vand.vi v25, v25, 15
-; LMULMAX1-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-NEXT: vand.vx v27, v26, a3
-; LMULMAX1-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX1-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-NEXT: vand.vi v26, v26, 15
-; LMULMAX1-NEXT: vse8.v v26, (a0)
-; LMULMAX1-NEXT: vse8.v v25, (a1)
+; LMULMAX1-NEXT: vand.vx v10, v8, a3
+; LMULMAX1-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX1-NEXT: vadd.vv v8, v8, v10
+; LMULMAX1-NEXT: vand.vi v8, v8, 15
+; LMULMAX1-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-NEXT: vand.vx v10, v9, a3
+; LMULMAX1-NEXT: vsrl.vi v9, v9, 2
+; LMULMAX1-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-NEXT: vand.vi v9, v9, 15
+; LMULMAX1-NEXT: vse8.v v9, (a0)
+; LMULMAX1-NEXT: vse8.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -511,135 +511,135 @@ define void @ctpop_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-LABEL: ctpop_v16i16:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 5
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 3
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v28, v26, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vand.vx v10, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 1
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV32-NEXT: addi a1, zero, 257
-; LMULMAX2-RV32-NEXT: vmul.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 8
-; LMULMAX2-RV32-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: ctpop_v16i16:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 5
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, 3
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v28, v26, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vand.vx v10, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, 1
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: addi a1, zero, 257
-; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 8
-; LMULMAX2-RV64-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ctpop_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a2, 5
; LMULMAX1-RV32-NEXT: addi a2, a2, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a3, 3
; LMULMAX1-RV32-NEXT: addi a3, a3, 819
-; LMULMAX1-RV32-NEXT: vand.vx v27, v25, a3
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27
+; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a3
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a4, 1
; LMULMAX1-RV32-NEXT: addi a4, a4, -241
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV32-NEXT: addi a5, zero, 257
-; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a5
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 8
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vx v27, v26, a3
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV32-NEXT: vmul.vx v26, v26, a5
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 8
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a5
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a3
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a5
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 8
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ctpop_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a2, 5
; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a3, 3
; LMULMAX1-RV64-NEXT: addiw a3, a3, 819
-; LMULMAX1-RV64-NEXT: vand.vx v27, v25, a3
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a3
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a4, 1
; LMULMAX1-RV64-NEXT: addiw a4, a4, -241
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: addi a5, zero, 257
-; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a5
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 8
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vand.vx v27, v26, a3
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV64-NEXT: vmul.vx v26, v26, a5
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 8
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a5
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a3
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a5
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 8
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -653,139 +653,139 @@ define void @ctpop_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-LABEL: ctpop_v8i32:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
-; LMULMAX2-RV32-NEXT: vand.vx v28, v26, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vand.vx v10, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
-; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1
+; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV32-NEXT: lui a1, 4112
; LMULMAX2-RV32-NEXT: addi a1, a1, 257
-; LMULMAX2-RV32-NEXT: vmul.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 24
-; LMULMAX2-RV32-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: ctpop_v8i32:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 349525
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, 209715
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v28, v26, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vand.vx v10, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, 61681
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: lui a1, 4112
; LMULMAX2-RV64-NEXT: addiw a1, a1, 257
-; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 24
-; LMULMAX2-RV64-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ctpop_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a2, 349525
; LMULMAX1-RV32-NEXT: addi a2, a2, 1365
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a3, 209715
; LMULMAX1-RV32-NEXT: addi a3, a3, 819
-; LMULMAX1-RV32-NEXT: vand.vx v27, v25, a3
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27
+; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a3
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a4, 61681
; LMULMAX1-RV32-NEXT: addi a4, a4, -241
-; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4
+; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV32-NEXT: lui a5, 4112
; LMULMAX1-RV32-NEXT: addi a5, a5, 257
-; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a5
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 24
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vx v27, v26, a3
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV32-NEXT: vmul.vx v26, v26, a5
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 24
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a5
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a3
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a5
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 24
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ctpop_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a2, 349525
; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a3, 209715
; LMULMAX1-RV64-NEXT: addiw a3, a3, 819
-; LMULMAX1-RV64-NEXT: vand.vx v27, v25, a3
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a3
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a4, 61681
; LMULMAX1-RV64-NEXT: addiw a4, a4, -241
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: lui a5, 4112
; LMULMAX1-RV64-NEXT: addiw a5, a5, 257
-; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a5
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 24
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vand.vx v27, v26, a3
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV64-NEXT: vmul.vx v26, v26, a5
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 24
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a5
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 24
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a3
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a5
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 24
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -799,48 +799,48 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-LABEL: ctpop_v4i64:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a1, a1, 1365
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30
-; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 209715
; LMULMAX2-RV32-NEXT: addi a1, a1, 819
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v30, v26, v28
-; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v30, v26
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vand.vv v12, v8, v10
+; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v12, v8
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 4112
; LMULMAX2-RV32-NEXT: addi a1, a1, 257
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmul.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vmul.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: addi a1, zero, 56
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a1
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: ctpop_v4i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX2-RV64-NEXT: lui a1, 21845
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -849,8 +849,8 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
-; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, 13107
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -859,12 +859,12 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, 819
-; LMULMAX2-RV64-NEXT: vand.vx v28, v26, a1
-; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vand.vx v10, v8, a1
+; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, 3855
; LMULMAX2-RV64-NEXT: addiw a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -873,81 +873,81 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 241
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a1, a1, -241
-; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1
+; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: lui a1, 4112
; LMULMAX2-RV64-NEXT: addiw a1, a1, 257
; LMULMAX2-RV64-NEXT: slli a1, a1, 16
; LMULMAX2-RV64-NEXT: addi a1, a1, 257
; LMULMAX2-RV64-NEXT: slli a1, a1, 16
; LMULMAX2-RV64-NEXT: addi a1, a1, 257
-; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1
+; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: addi a1, zero, 56
-; LMULMAX2-RV64-NEXT: vsrl.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ctpop_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a2, 349525
; LMULMAX1-RV32-NEXT: addi a2, a2, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v28, a2
+; LMULMAX1-RV32-NEXT: vmv.v.x v11, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v27, v27, v28
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27
+; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v11
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a2, 209715
; LMULMAX1-RV32-NEXT: addi a2, a2, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a2
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v29, v25, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v29, v25
-; LMULMAX1-RV32-NEXT: vsrl.vi v29, v25, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v29
+; LMULMAX1-RV32-NEXT: vand.vv v12, v8, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v12, v8
+; LMULMAX1-RV32-NEXT: vsrl.vi v12, v8, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: lui a2, 61681
; LMULMAX1-RV32-NEXT: addi a2, a2, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v29, a2
+; LMULMAX1-RV32-NEXT: vmv.v.x v12, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v29
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: lui a2, 4112
; LMULMAX1-RV32-NEXT: addi a2, a2, 257
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v30, a2
+; LMULMAX1-RV32-NEXT: vmv.v.x v13, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v30
+; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v13
; LMULMAX1-RV32-NEXT: addi a2, zero, 56
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a2
-; LMULMAX1-RV32-NEXT: vsrl.vi v31, v26, 1
-; LMULMAX1-RV32-NEXT: vand.vv v28, v31, v28
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v28
-; LMULMAX1-RV32-NEXT: vand.vv v28, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v28, v26
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v29
-; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v30
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a2
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a2
+; LMULMAX1-RV32-NEXT: vsrl.vi v14, v9, 1
+; LMULMAX1-RV32-NEXT: vand.vv v11, v14, v11
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v11
+; LMULMAX1-RV32-NEXT: vand.vv v11, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v11, v9
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12
+; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v13
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a2
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ctpop_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a6)
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a6)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a2, 21845
; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
@@ -956,8 +956,8 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 1365
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a3, 13107
; LMULMAX1-RV64-NEXT: addiw a3, a3, 819
; LMULMAX1-RV64-NEXT: slli a3, a3, 12
@@ -966,12 +966,12 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a3, a3, 819
; LMULMAX1-RV64-NEXT: slli a3, a3, 12
; LMULMAX1-RV64-NEXT: addi a3, a3, 819
-; LMULMAX1-RV64-NEXT: vand.vx v27, v25, a3
-; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27
+; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a3
+; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a4, 3855
; LMULMAX1-RV64-NEXT: addiw a4, a4, 241
; LMULMAX1-RV64-NEXT: slli a4, a4, 12
@@ -980,30 +980,30 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: addi a4, a4, 241
; LMULMAX1-RV64-NEXT: slli a4, a4, 12
; LMULMAX1-RV64-NEXT: addi a4, a4, -241
-; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4
+; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: lui a5, 4112
; LMULMAX1-RV64-NEXT: addiw a5, a5, 257
; LMULMAX1-RV64-NEXT: slli a5, a5, 16
; LMULMAX1-RV64-NEXT: addi a5, a5, 257
; LMULMAX1-RV64-NEXT: slli a5, a5, 16
; LMULMAX1-RV64-NEXT: addi a5, a5, 257
-; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a5
+; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: addi a1, zero, 56
-; LMULMAX1-RV64-NEXT: vsrl.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1
-; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vand.vx v27, v26, a3
-; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 2
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4
-; LMULMAX1-RV64-NEXT: vmul.vx v26, v26, a5
-; LMULMAX1-RV64-NEXT: vsrl.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a6)
+; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a1
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
+; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a3
+; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
+; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a5
+; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a1
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a6)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index b1eab3df6c90a..24d74463d298d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -10,8 +10,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle8.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -38,8 +38,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a5, a5, 24
; LMULMAX2-RV32-NEXT: sb a5, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX2-RV32-NEXT: ori a5, a5, 256
; LMULMAX2-RV32-NEXT: addi a1, a5, -1
; LMULMAX2-RV32-NEXT: not a5, a5
@@ -57,8 +57,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 31(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -76,8 +76,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 30(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -95,8 +95,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 29(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -114,8 +114,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -133,8 +133,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 27(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -152,8 +152,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 26(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -171,8 +171,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 25(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -190,8 +190,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -209,8 +209,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 23(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -228,8 +228,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 22(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -247,8 +247,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 21(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -266,8 +266,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 20(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -285,8 +285,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 19(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -304,8 +304,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 18(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -325,8 +325,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV32-NEXT: sb a1, 17(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle8.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse8.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -335,10 +335,10 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -386,8 +386,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a5, a5, a4
; LMULMAX2-RV64-NEXT: srli a5, a5, 56
; LMULMAX2-RV64-NEXT: sb a5, 31(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX2-RV64-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX2-RV64-NEXT: vmv.x.s a5, v9
; LMULMAX2-RV64-NEXT: ori a5, a5, 256
; LMULMAX2-RV64-NEXT: addi a1, a5, -1
; LMULMAX2-RV64-NEXT: not a5, a5
@@ -405,8 +405,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 30(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -424,8 +424,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 29(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -443,8 +443,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -462,8 +462,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 27(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -481,8 +481,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 26(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -500,8 +500,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 25(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -519,8 +519,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -538,8 +538,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 23(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -557,8 +557,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 22(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -576,8 +576,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 21(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -595,8 +595,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 20(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -614,8 +614,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 19(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -633,8 +633,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 18(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -652,7 +652,7 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a4
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 17(sp)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a5, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -672,8 +672,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX2-RV64-NEXT: sb a1, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle8.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse8.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -682,8 +682,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -710,8 +710,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a5, a5, 24
; LMULMAX1-RV32-NEXT: sb a5, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9
; LMULMAX1-RV32-NEXT: ori a5, a5, 256
; LMULMAX1-RV32-NEXT: addi a1, a5, -1
; LMULMAX1-RV32-NEXT: not a5, a5
@@ -729,8 +729,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 31(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -748,8 +748,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -767,8 +767,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -786,8 +786,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -805,8 +805,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -824,8 +824,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -843,8 +843,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -862,8 +862,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -881,8 +881,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -900,8 +900,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -919,8 +919,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -938,8 +938,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -957,8 +957,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -976,8 +976,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a4
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -997,8 +997,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV32-NEXT: sb a1, 17(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -1007,10 +1007,10 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1058,8 +1058,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a5, a5, a4
; LMULMAX1-RV64-NEXT: srli a5, a5, 56
; LMULMAX1-RV64-NEXT: sb a5, 31(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV64-NEXT: vmv.x.s a5, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV64-NEXT: vmv.x.s a5, v9
; LMULMAX1-RV64-NEXT: ori a5, a5, 256
; LMULMAX1-RV64-NEXT: addi a1, a5, -1
; LMULMAX1-RV64-NEXT: not a5, a5
@@ -1077,8 +1077,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1096,8 +1096,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1115,8 +1115,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1134,8 +1134,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1153,8 +1153,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1172,8 +1172,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1191,8 +1191,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1210,8 +1210,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1229,8 +1229,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1248,8 +1248,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1267,8 +1267,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1286,8 +1286,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1305,8 +1305,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1324,7 +1324,7 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a4
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 17(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a5, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1344,8 +1344,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; LMULMAX1-RV64-NEXT: sb a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
@@ -1362,8 +1362,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: lui a6, 16
; LMULMAX2-RV32-NEXT: or a2, a2, a6
; LMULMAX2-RV32-NEXT: addi a3, a2, -1
@@ -1391,8 +1391,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -1410,8 +1410,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 30(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -1429,8 +1429,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -1448,8 +1448,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 26(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -1467,8 +1467,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -1486,8 +1486,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 22(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -1505,8 +1505,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 20(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -1526,8 +1526,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV32-NEXT: sh a1, 18(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -1536,10 +1536,10 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX2-RV64-NEXT: lui a6, 16
; LMULMAX2-RV64-NEXT: or a2, a2, a6
; LMULMAX2-RV64-NEXT: addi a3, a2, -1
@@ -1588,8 +1588,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 30(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -1607,8 +1607,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -1626,8 +1626,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 26(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -1645,8 +1645,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -1664,8 +1664,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 22(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -1683,8 +1683,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 20(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -1702,7 +1702,7 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 18(sp)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -1722,8 +1722,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX2-RV64-NEXT: sh a1, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -1732,8 +1732,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: lui a6, 16
; LMULMAX1-RV32-NEXT: or a2, a2, a6
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
@@ -1761,8 +1761,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sh a1, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: or a1, a1, a6
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -1780,8 +1780,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sh a1, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: or a1, a1, a6
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -1799,8 +1799,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sh a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: or a1, a1, a6
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -1818,8 +1818,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sh a1, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: or a1, a1, a6
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -1837,8 +1837,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sh a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: or a1, a1, a6
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -1856,8 +1856,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sh a1, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: or a1, a1, a6
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -1875,8 +1875,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sh a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: or a1, a1, a6
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -1896,8 +1896,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV32-NEXT: sh a1, 18(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -1906,10 +1906,10 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: lui a6, 16
; LMULMAX1-RV64-NEXT: or a2, a2, a6
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
@@ -1958,8 +1958,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sh a1, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1977,8 +1977,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sh a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -1996,8 +1996,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sh a1, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2015,8 +2015,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sh a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2034,8 +2034,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sh a1, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2053,8 +2053,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sh a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2072,7 +2072,7 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sh a1, 18(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2092,8 +2092,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; LMULMAX1-RV64-NEXT: sh a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
@@ -2110,8 +2110,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a2, a1, a2
@@ -2137,8 +2137,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: srli a4, a4, 24
; LMULMAX2-RV32-NEXT: sw a4, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a4, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a4, v9
; LMULMAX2-RV32-NEXT: addi a1, a4, -1
; LMULMAX2-RV32-NEXT: not a4, a4
; LMULMAX2-RV32-NEXT: and a1, a4, a1
@@ -2155,8 +2155,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: addi a4, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a4
@@ -2173,8 +2173,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: addi a4, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a4
@@ -2193,8 +2193,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 20(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX2-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
@@ -2203,10 +2203,10 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: addi sp, sp, -32
; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX2-RV64-NEXT: addi a1, zero, 1
; LMULMAX2-RV64-NEXT: slli a6, a1, 32
; LMULMAX2-RV64-NEXT: or a2, a2, a6
@@ -2256,8 +2256,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -2275,8 +2275,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -2294,7 +2294,7 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 20(sp)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -2314,8 +2314,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX2-RV64-NEXT: sw a1, 16(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 16
-; LMULMAX2-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX2-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, sp, 32
; LMULMAX2-RV64-NEXT: ret
;
@@ -2324,8 +2324,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a2, a1, a2
@@ -2351,8 +2351,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: srli a4, a4, 24
; LMULMAX1-RV32-NEXT: sw a4, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a4, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a4, v9
; LMULMAX1-RV32-NEXT: addi a1, a4, -1
; LMULMAX1-RV32-NEXT: not a4, a4
; LMULMAX1-RV32-NEXT: and a1, a4, a1
@@ -2369,8 +2369,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a4, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a4
@@ -2387,8 +2387,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: addi a4, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a4
@@ -2407,8 +2407,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
@@ -2417,10 +2417,10 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: addi sp, sp, -32
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: addi a1, zero, 1
; LMULMAX1-RV64-NEXT: slli a6, a1, 32
; LMULMAX1-RV64-NEXT: or a2, a2, a6
@@ -2470,8 +2470,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2489,8 +2489,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2508,7 +2508,7 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sw a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: or a1, a1, a6
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -2528,8 +2528,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; LMULMAX1-RV64-NEXT: sw a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi sp, sp, 32
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
@@ -2546,7 +2546,7 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: addi sp, sp, -32
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: sw zero, 28(sp)
; LMULMAX2-RV32-NEXT: sw zero, 20(sp)
; LMULMAX2-RV32-NEXT: addi a6, zero, 32
@@ -2557,13 +2557,13 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a7, a1, -241
; LMULMAX2-RV32-NEXT: lui a2, 4112
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v25
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v8
; LMULMAX2-RV32-NEXT: addi a2, a2, 257
; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_2
; LMULMAX2-RV32-NEXT: # %bb.1:
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -2600,12 +2600,12 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: .LBB3_3:
; LMULMAX2-RV32-NEXT: sw a5, 16(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v25
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v8
; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_5
; LMULMAX2-RV32-NEXT: # %bb.4:
-; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -2643,19 +2643,19 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 24(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 16
-; LMULMAX2-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 32
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: cttz_v2i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
; LMULMAX2-RV64-NEXT: and a1, a1, a2
@@ -2702,8 +2702,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX2-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: addi a3, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
; LMULMAX2-RV64-NEXT: and a1, a1, a3
@@ -2720,8 +2720,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmv.s.x v9, a1
+; LMULMAX2-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: cttz_v2i64:
@@ -2729,7 +2729,7 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: sw zero, 28(sp)
; LMULMAX1-RV32-NEXT: sw zero, 20(sp)
; LMULMAX1-RV32-NEXT: addi a6, zero, 32
@@ -2740,13 +2740,13 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: lui a1, 61681
; LMULMAX1-RV32-NEXT: addi a7, a1, -241
; LMULMAX1-RV32-NEXT: lui a2, 4112
-; LMULMAX1-RV32-NEXT: vmv.x.s a5, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a5, v8
; LMULMAX1-RV32-NEXT: addi a2, a2, 257
; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_2
; LMULMAX1-RV32-NEXT: # %bb.1:
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a5
@@ -2783,12 +2783,12 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: .LBB3_3:
; LMULMAX1-RV32-NEXT: sw a5, 16(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a5, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a5, v8
; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_5
; LMULMAX1-RV32-NEXT: # %bb.4:
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a5
@@ -2826,19 +2826,19 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 32
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: cttz_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
; LMULMAX1-RV64-NEXT: and a1, a1, a2
@@ -2885,8 +2885,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: addi a3, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
; LMULMAX1-RV64-NEXT: and a1, a1, a3
@@ -2903,8 +2903,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -2928,8 +2928,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: addi a6, zero, 32
; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle8.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: ori a2, a2, 256
; LMULMAX2-RV32-NEXT: addi a3, a2, -1
; LMULMAX2-RV32-NEXT: not a2, a2
@@ -2956,8 +2956,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 31
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 31
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -2975,8 +2975,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 63(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 30
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 30
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -2994,8 +2994,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 62(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 29
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 29
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3013,8 +3013,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 61(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 28
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 28
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3032,8 +3032,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 27
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 27
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3051,8 +3051,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 59(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 26
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 26
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3070,8 +3070,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 58(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 25
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 25
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3089,8 +3089,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 57(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 24
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 24
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3108,8 +3108,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 23
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 23
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3127,8 +3127,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 55(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 22
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 22
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3146,8 +3146,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 54(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 21
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 21
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3165,8 +3165,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 53(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 20
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 20
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3184,8 +3184,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 19
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 19
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3203,8 +3203,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 51(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 18
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 18
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3222,8 +3222,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 50(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 17
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 17
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3241,8 +3241,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 49(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 16
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 16
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3260,8 +3260,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3279,8 +3279,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 47(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3298,8 +3298,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 46(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3317,8 +3317,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 45(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3336,8 +3336,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3355,8 +3355,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 43(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3374,8 +3374,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 42(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3393,8 +3393,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 41(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3412,8 +3412,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3431,8 +3431,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 39(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3450,8 +3450,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 38(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3469,8 +3469,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 37(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3488,8 +3488,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 36(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3507,8 +3507,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 35(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3526,8 +3526,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sb a1, 34(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: ori a1, a1, 256
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -3547,8 +3547,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV32-NEXT: sb a1, 33(sp)
; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle8.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -3568,10 +3568,10 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: addi a6, zero, 32
; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle8.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 31
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 31
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX2-RV64-NEXT: ori a2, a2, 256
; LMULMAX2-RV64-NEXT: addi a3, a2, -1
; LMULMAX2-RV64-NEXT: not a2, a2
@@ -3619,8 +3619,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 63(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 30
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 30
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3638,8 +3638,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 62(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 29
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 29
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3657,8 +3657,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 61(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 28
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 28
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3676,8 +3676,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 27
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 27
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3695,8 +3695,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 59(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 26
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 26
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3714,8 +3714,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 58(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 25
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 25
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3733,8 +3733,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 57(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 24
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 24
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3752,8 +3752,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 23
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 23
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3771,8 +3771,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 55(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 22
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 22
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3790,8 +3790,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 54(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 21
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 21
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3809,8 +3809,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 53(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 20
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 20
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3828,8 +3828,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 19
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 19
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3847,8 +3847,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 51(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 18
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 18
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3866,8 +3866,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 50(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 17
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 17
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3885,8 +3885,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 49(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 16
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 16
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3904,8 +3904,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3923,8 +3923,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 47(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3942,8 +3942,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 46(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3961,8 +3961,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 45(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3980,8 +3980,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -3999,8 +3999,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 43(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4018,8 +4018,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 42(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4037,8 +4037,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 41(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4056,8 +4056,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4075,8 +4075,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 39(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4094,8 +4094,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 38(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4113,8 +4113,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 37(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4132,8 +4132,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 36(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4151,8 +4151,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 35(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4170,8 +4170,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 34(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4189,7 +4189,7 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sb a1, 33(sp)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: ori a1, a1, 256
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -4209,8 +4209,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2-RV64-NEXT: sb a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle8.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -4223,9 +4223,9 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: ori a2, a2, 256
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -4252,8 +4252,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 15
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 15
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4271,8 +4271,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 47(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 14
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 14
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4290,8 +4290,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 46(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 13
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 13
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4309,8 +4309,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 45(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 12
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 12
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4328,8 +4328,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 11
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 11
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4347,8 +4347,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 43(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 10
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 10
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4366,8 +4366,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 42(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 9
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 9
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4385,8 +4385,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 41(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 8
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 8
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4404,8 +4404,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4423,8 +4423,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 39(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4442,8 +4442,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 38(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4461,8 +4461,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 37(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4480,8 +4480,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 36(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4499,8 +4499,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 35(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4518,8 +4518,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 34(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4537,7 +4537,7 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 33(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4555,8 +4555,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4574,8 +4574,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 31(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4593,8 +4593,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4612,8 +4612,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4631,8 +4631,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4650,8 +4650,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4669,8 +4669,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4688,8 +4688,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4707,8 +4707,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4726,8 +4726,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4745,8 +4745,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4764,8 +4764,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4783,8 +4783,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4802,8 +4802,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4821,8 +4821,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: ori a1, a1, 256
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
@@ -4842,11 +4842,11 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV32-NEXT: sb a1, 17(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -4856,9 +4856,9 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: ori a2, a2, 256
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -4907,8 +4907,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 15
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 15
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -4926,8 +4926,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 47(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 14
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 14
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -4945,8 +4945,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 46(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 13
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 13
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -4964,8 +4964,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 45(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 12
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 12
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -4983,8 +4983,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 11
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 11
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5002,8 +5002,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 43(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 10
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 10
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5021,8 +5021,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 42(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 9
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 9
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5040,8 +5040,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 41(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 8
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 8
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5059,8 +5059,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5078,8 +5078,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 39(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5097,8 +5097,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 38(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5116,8 +5116,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 37(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5135,8 +5135,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 36(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5154,8 +5154,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 35(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5173,8 +5173,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 34(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5192,8 +5192,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 33(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5211,8 +5211,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 31(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5230,8 +5230,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5249,8 +5249,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 29(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5268,8 +5268,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5287,8 +5287,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 27(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5306,8 +5306,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5325,8 +5325,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 25(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5344,8 +5344,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5363,8 +5363,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 23(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5382,8 +5382,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5401,8 +5401,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 21(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5420,8 +5420,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5439,8 +5439,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 19(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5458,8 +5458,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 18(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5477,7 +5477,7 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: sb a1, 17(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: ori a1, a1, 256
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
@@ -5497,11 +5497,11 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX1-RV64-NEXT: sb a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, sp, 32
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a6)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
@@ -5525,8 +5525,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX2-RV32-NEXT: lui a6, 16
; LMULMAX2-RV32-NEXT: or a2, a2, a6
; LMULMAX2-RV32-NEXT: addi a3, a2, -1
@@ -5554,8 +5554,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5573,8 +5573,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 62(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5592,8 +5592,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5611,8 +5611,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 58(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5630,8 +5630,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5649,8 +5649,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 54(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5668,8 +5668,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5687,8 +5687,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 50(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5706,8 +5706,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5725,8 +5725,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 46(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5744,8 +5744,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5763,8 +5763,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 42(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5782,8 +5782,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5801,8 +5801,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 38(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5820,8 +5820,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a5
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sh a1, 36(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: or a1, a1, a6
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
@@ -5841,8 +5841,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV32-NEXT: sh a1, 34(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -5861,10 +5861,10 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX2-RV64-NEXT: lui a6, 16
; LMULMAX2-RV64-NEXT: or a2, a2, a6
; LMULMAX2-RV64-NEXT: addi a3, a2, -1
@@ -5913,8 +5913,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 62(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -5932,8 +5932,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -5951,8 +5951,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 58(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -5970,8 +5970,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -5989,8 +5989,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 54(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6008,8 +6008,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6027,8 +6027,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 50(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6046,8 +6046,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6065,8 +6065,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 46(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6084,8 +6084,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6103,8 +6103,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 42(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6122,8 +6122,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6141,8 +6141,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 38(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6160,8 +6160,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 36(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6179,7 +6179,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sh a1, 34(sp)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -6199,8 +6199,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-RV64-NEXT: sh a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -6213,9 +6213,9 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: lui a7, 16
; LMULMAX1-RV32-NEXT: or a1, a1, a7
; LMULMAX1-RV32-NEXT: addi a3, a1, -1
@@ -6243,8 +6243,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6262,8 +6262,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 46(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6281,8 +6281,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6300,8 +6300,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 42(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6319,8 +6319,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6338,8 +6338,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 38(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6357,8 +6357,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 36(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6376,7 +6376,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 34(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6394,8 +6394,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6413,8 +6413,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 30(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6432,8 +6432,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6451,8 +6451,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 26(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6470,8 +6470,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6489,8 +6489,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 22(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6508,8 +6508,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: mul a2, a2, a1
; LMULMAX1-RV32-NEXT: srli a2, a2, 24
; LMULMAX1-RV32-NEXT: sh a2, 20(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: or a2, a2, a7
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
@@ -6529,11 +6529,11 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV32-NEXT: sh a1, 18(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -6543,9 +6543,9 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: lui a7, 16
; LMULMAX1-RV64-NEXT: or a1, a1, a7
; LMULMAX1-RV64-NEXT: addi a3, a1, -1
@@ -6595,8 +6595,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6614,8 +6614,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 46(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6633,8 +6633,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6652,8 +6652,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 42(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6671,8 +6671,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6690,8 +6690,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 38(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6709,8 +6709,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 36(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6728,8 +6728,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 34(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6747,8 +6747,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 30(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6766,8 +6766,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6785,8 +6785,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 26(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6804,8 +6804,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6823,8 +6823,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 22(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6842,8 +6842,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 20(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6861,7 +6861,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sh a2, 18(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -6881,11 +6881,11 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX1-RV64-NEXT: sh a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, sp, 32
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a6)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
@@ -6909,8 +6909,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a0)
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: addi a2, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a2, a1, a2
@@ -6936,8 +6936,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: srli a5, a5, 24
; LMULMAX2-RV32-NEXT: sw a5, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10
; LMULMAX2-RV32-NEXT: addi a1, a5, -1
; LMULMAX2-RV32-NEXT: not a5, a5
; LMULMAX2-RV32-NEXT: and a1, a5, a1
@@ -6954,8 +6954,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 60(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -6972,8 +6972,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 56(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -6990,8 +6990,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 52(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7008,8 +7008,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 48(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7026,8 +7026,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 44(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7044,8 +7044,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a4
; LMULMAX2-RV32-NEXT: srli a1, a1, 24
; LMULMAX2-RV32-NEXT: sw a1, 40(sp)
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7064,8 +7064,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 36(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a1)
-; LMULMAX2-RV32-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -7084,10 +7084,10 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7
-; LMULMAX2-RV64-NEXT: vmv.x.s a2, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7
+; LMULMAX2-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX2-RV64-NEXT: addi a1, zero, 1
; LMULMAX2-RV64-NEXT: slli a6, a1, 32
; LMULMAX2-RV64-NEXT: or a2, a2, a6
@@ -7137,8 +7137,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 60(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -7156,8 +7156,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -7175,8 +7175,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 52(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -7194,8 +7194,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -7213,8 +7213,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 44(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -7232,8 +7232,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -7251,7 +7251,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sw a1, 36(sp)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: or a1, a1, a6
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
@@ -7271,8 +7271,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-RV64-NEXT: sw a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -7285,9 +7285,9 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a6, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a6)
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a6)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV32-NEXT: addi a3, a2, -1
; LMULMAX1-RV32-NEXT: not a2, a2
; LMULMAX1-RV32-NEXT: and a3, a2, a3
@@ -7313,8 +7313,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -7331,8 +7331,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 44(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -7349,8 +7349,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 40(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -7367,7 +7367,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 36(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -7384,8 +7384,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -7402,8 +7402,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 28(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -7420,8 +7420,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a5
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -7440,11 +7440,11 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 20(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a6)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a6)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -7454,9 +7454,9 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: addi a2, zero, 1
; LMULMAX1-RV64-NEXT: slli a7, a2, 32
; LMULMAX1-RV64-NEXT: or a1, a1, a7
@@ -7507,8 +7507,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sw a2, 32(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -7526,8 +7526,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sw a2, 44(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -7545,8 +7545,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sw a2, 40(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -7564,8 +7564,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sw a2, 36(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -7583,8 +7583,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sw a2, 28(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -7602,8 +7602,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sw a2, 24(sp)
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -7621,7 +7621,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: sw a2, 20(sp)
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV64-NEXT: or a2, a2, a7
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
@@ -7641,11 +7641,11 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: sw a1, 16(sp)
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, sp, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, sp, 32
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a6)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a6)
; LMULMAX1-RV64-NEXT: addi sp, sp, 48
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
@@ -7669,7 +7669,7 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV32-NEXT: andi sp, sp, -32
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: sw zero, 60(sp)
; LMULMAX2-RV32-NEXT: sw zero, 52(sp)
; LMULMAX2-RV32-NEXT: sw zero, 44(sp)
@@ -7682,13 +7682,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a7, a1, -241
; LMULMAX2-RV32-NEXT: lui a1, 4112
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v8
; LMULMAX2-RV32-NEXT: addi a2, a1, 257
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_2
; LMULMAX2-RV32-NEXT: # %bb.1:
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7725,12 +7725,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: .LBB7_3:
; LMULMAX2-RV32-NEXT: sw a5, 32(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_5
; LMULMAX2-RV32-NEXT: # %bb.4:
-; LMULMAX2-RV32-NEXT: vsrl.vx v28, v28, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vsrl.vx v10, v10, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7765,13 +7765,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
; LMULMAX2-RV32-NEXT: .LBB7_6:
-; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: sw a5, 56(sp)
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_8
; LMULMAX2-RV32-NEXT: # %bb.7:
-; LMULMAX2-RV32-NEXT: vsrl.vx v28, v28, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV32-NEXT: vsrl.vx v10, v10, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7806,13 +7806,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
; LMULMAX2-RV32-NEXT: .LBB7_9:
-; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: sw a5, 48(sp)
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_11
; LMULMAX2-RV32-NEXT: # %bb.10:
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a6
-; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a6
+; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
; LMULMAX2-RV32-NEXT: not a1, a1
; LMULMAX2-RV32-NEXT: and a1, a1, a5
@@ -7850,9 +7850,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: sw a1, 40(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 32
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, s0, -96
; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
@@ -7871,10 +7871,10 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-RV64-NEXT: andi sp, sp, -32
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: addi a2, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
; LMULMAX2-RV64-NEXT: and a2, a1, a2
@@ -7921,8 +7921,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a4, a4, a5
; LMULMAX2-RV64-NEXT: srli a4, a4, 56
; LMULMAX2-RV64-NEXT: sd a4, 56(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2
-; LMULMAX2-RV64-NEXT: vmv.x.s a4, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2
+; LMULMAX2-RV64-NEXT: vmv.x.s a4, v10
; LMULMAX2-RV64-NEXT: addi a1, a4, -1
; LMULMAX2-RV64-NEXT: not a4, a4
; LMULMAX2-RV64-NEXT: and a1, a4, a1
@@ -7939,8 +7939,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sd a1, 48(sp)
-; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28
+; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10
; LMULMAX2-RV64-NEXT: addi a4, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
; LMULMAX2-RV64-NEXT: and a1, a1, a4
@@ -7957,7 +7957,7 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: sd a1, 40(sp)
-; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX2-RV64-NEXT: addi a4, a1, -1
; LMULMAX2-RV64-NEXT: not a1, a1
; LMULMAX2-RV64-NEXT: and a1, a1, a4
@@ -7976,8 +7976,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV64-NEXT: sd a1, 32(sp)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a1, sp, 32
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a1)
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi sp, s0, -96
; LMULMAX2-RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; LMULMAX2-RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
@@ -7989,9 +7989,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi sp, sp, -48
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a7, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a7)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a7)
; LMULMAX1-RV32-NEXT: sw zero, 44(sp)
; LMULMAX1-RV32-NEXT: sw zero, 36(sp)
; LMULMAX1-RV32-NEXT: addi a6, zero, 32
@@ -8002,13 +8002,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: lui a1, 61681
; LMULMAX1-RV32-NEXT: addi t0, a1, -241
; LMULMAX1-RV32-NEXT: lui a2, 4112
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a3, a2, 257
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_2
; LMULMAX1-RV32-NEXT: # %bb.1:
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsrl.vx v27, v26, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
+; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -8045,12 +8045,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: .LBB7_3:
; LMULMAX1-RV32-NEXT: sw a1, 32(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_5
; LMULMAX1-RV32-NEXT: # %bb.4:
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -8087,12 +8087,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: .LBB7_6:
; LMULMAX1-RV32-NEXT: sw a1, 40(sp)
; LMULMAX1-RV32-NEXT: sw zero, 28(sp)
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: sw zero, 20(sp)
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_8
; LMULMAX1-RV32-NEXT: # %bb.7:
-; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -8127,13 +8127,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: mul a1, a1, a3
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
; LMULMAX1-RV32-NEXT: .LBB7_9:
-; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
+; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_11
; LMULMAX1-RV32-NEXT: # %bb.10:
-; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a6
-; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a6
+; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
; LMULMAX1-RV32-NEXT: not a1, a1
; LMULMAX1-RV32-NEXT: and a1, a1, a2
@@ -8171,12 +8171,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 16
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, sp, 32
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a7)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a7)
; LMULMAX1-RV32-NEXT: addi sp, sp, 48
; LMULMAX1-RV32-NEXT: ret
;
@@ -8184,11 +8184,11 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a6, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a6)
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a6)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27
+; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10
; LMULMAX1-RV64-NEXT: addi a3, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2
; LMULMAX1-RV64-NEXT: and a3, a2, a3
@@ -8235,8 +8235,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v27, a1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vmv.v.x v10, a1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
; LMULMAX1-RV64-NEXT: and a1, a1, a2
@@ -8253,10 +8253,10 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
+; LMULMAX1-RV64-NEXT: vmv.s.x v10, a1
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26
+; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
; LMULMAX1-RV64-NEXT: and a1, a1, a2
@@ -8273,8 +8273,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
+; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1
+; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8
; LMULMAX1-RV64-NEXT: addi a2, a1, -1
; LMULMAX1-RV64-NEXT: not a1, a1
; LMULMAX1-RV64-NEXT: and a1, a1, a2
@@ -8291,9 +8291,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v27, (a6)
+; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v10, (a6)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
index 8e78e89f1fb90..9e6da01784589 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
@@ -10,10 +10,10 @@ define void @add_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: add_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -71,10 +71,10 @@ define void @add_v2i32(<2 x i32>* %x, <2 x i32>* %y) {
; CHECK-LABEL: add_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load <2 x i32>, <2 x i32>* %y
@@ -118,10 +118,10 @@ define void @fadd_v4f32(<4 x float>* %x, <4 x float>* %y) {
; CHECK-LABEL: fadd_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfadd.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -155,10 +155,10 @@ define void @fadd_v2f32(<2 x float>* %x, <2 x float>* %y) {
; CHECK-LABEL: fadd_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfadd.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%b = load <2 x float>, <2 x float>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
index f332e0bc94191..ab55b58c77e8a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
@@ -10,8 +10,8 @@ define <2 x i16> @sextload_v2i1_v2i16(<2 x i1>* %x) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%y = load <2 x i1>, <2 x i1>* %x
%z = sext <2 x i1> %y to <2 x i16>
@@ -22,9 +22,9 @@ define <2 x i16> @sextload_v2i8_v2i16(<2 x i8>* %x) {
; CHECK-LABEL: sextload_v2i8_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i8>, <2 x i8>* %x
%z = sext <2 x i8> %y to <2 x i16>
@@ -35,9 +35,9 @@ define <2 x i16> @zextload_v2i8_v2i16(<2 x i8>* %x) {
; CHECK-LABEL: zextload_v2i8_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i8>, <2 x i8>* %x
%z = zext <2 x i8> %y to <2 x i16>
@@ -48,9 +48,9 @@ define <2 x i32> @sextload_v2i8_v2i32(<2 x i8>* %x) {
; CHECK-LABEL: sextload_v2i8_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i8>, <2 x i8>* %x
%z = sext <2 x i8> %y to <2 x i32>
@@ -61,9 +61,9 @@ define <2 x i32> @zextload_v2i8_v2i32(<2 x i8>* %x) {
; CHECK-LABEL: zextload_v2i8_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i8>, <2 x i8>* %x
%z = zext <2 x i8> %y to <2 x i32>
@@ -74,9 +74,9 @@ define <2 x i64> @sextload_v2i8_v2i64(<2 x i8>* %x) {
; CHECK-LABEL: sextload_v2i8_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf8 v8, v25
+; CHECK-NEXT: vsext.vf8 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i8>, <2 x i8>* %x
%z = sext <2 x i8> %y to <2 x i64>
@@ -87,9 +87,9 @@ define <2 x i64> @zextload_v2i8_v2i64(<2 x i8>* %x) {
; CHECK-LABEL: zextload_v2i8_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf8 v8, v25
+; CHECK-NEXT: vzext.vf8 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i8>, <2 x i8>* %x
%z = zext <2 x i8> %y to <2 x i64>
@@ -100,9 +100,9 @@ define <4 x i16> @sextload_v4i8_v4i16(<4 x i8>* %x) {
; CHECK-LABEL: sextload_v4i8_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <4 x i8>, <4 x i8>* %x
%z = sext <4 x i8> %y to <4 x i16>
@@ -113,9 +113,9 @@ define <4 x i16> @zextload_v4i8_v4i16(<4 x i8>* %x) {
; CHECK-LABEL: zextload_v4i8_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <4 x i8>, <4 x i8>* %x
%z = zext <4 x i8> %y to <4 x i16>
@@ -126,9 +126,9 @@ define <4 x i32> @sextload_v4i8_v4i32(<4 x i8>* %x) {
; CHECK-LABEL: sextload_v4i8_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <4 x i8>, <4 x i8>* %x
%z = sext <4 x i8> %y to <4 x i32>
@@ -139,9 +139,9 @@ define <4 x i32> @zextload_v4i8_v4i32(<4 x i8>* %x) {
; CHECK-LABEL: zextload_v4i8_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <4 x i8>, <4 x i8>* %x
%z = zext <4 x i8> %y to <4 x i32>
@@ -152,20 +152,20 @@ define <4 x i64> @sextload_v4i8_v4i64(<4 x i8>* %x) {
; LMULMAX1-LABEL: sextload_v4i8_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v9, v26
-; LMULMAX1-NEXT: vsext.vf8 v8, v25
+; LMULMAX1-NEXT: vsext.vf8 v9, v8
+; LMULMAX1-NEXT: vsext.vf8 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v4i8_v4i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; LMULMAX4-NEXT: vsext.vf8 v8, v25
+; LMULMAX4-NEXT: vsext.vf8 v8, v10
; LMULMAX4-NEXT: ret
%y = load <4 x i8>, <4 x i8>* %x
%z = sext <4 x i8> %y to <4 x i64>
@@ -176,20 +176,20 @@ define <4 x i64> @zextload_v4i8_v4i64(<4 x i8>* %x) {
; LMULMAX1-LABEL: zextload_v4i8_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v9, v26
-; LMULMAX1-NEXT: vzext.vf8 v8, v25
+; LMULMAX1-NEXT: vzext.vf8 v9, v8
+; LMULMAX1-NEXT: vzext.vf8 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v4i8_v4i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; LMULMAX4-NEXT: vzext.vf8 v8, v25
+; LMULMAX4-NEXT: vzext.vf8 v8, v10
; LMULMAX4-NEXT: ret
%y = load <4 x i8>, <4 x i8>* %x
%z = zext <4 x i8> %y to <4 x i64>
@@ -200,9 +200,9 @@ define <8 x i16> @sextload_v8i8_v8i16(<8 x i8>* %x) {
; CHECK-LABEL: sextload_v8i8_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <8 x i8>, <8 x i8>* %x
%z = sext <8 x i8> %y to <8 x i16>
@@ -213,9 +213,9 @@ define <8 x i16> @zextload_v8i8_v8i16(<8 x i8>* %x) {
; CHECK-LABEL: zextload_v8i8_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <8 x i8>, <8 x i8>* %x
%z = zext <8 x i8> %y to <8 x i16>
@@ -226,20 +226,20 @@ define <8 x i32> @sextload_v8i8_v8i32(<8 x i8>* %x) {
; LMULMAX1-LABEL: sextload_v8i8_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v9, v26
-; LMULMAX1-NEXT: vsext.vf4 v8, v25
+; LMULMAX1-NEXT: vsext.vf4 v9, v8
+; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i8_v8i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX4-NEXT: vsext.vf4 v8, v25
+; LMULMAX4-NEXT: vsext.vf4 v8, v10
; LMULMAX4-NEXT: ret
%y = load <8 x i8>, <8 x i8>* %x
%z = sext <8 x i8> %y to <8 x i32>
@@ -250,20 +250,20 @@ define <8 x i32> @zextload_v8i8_v8i32(<8 x i8>* %x) {
; LMULMAX1-LABEL: zextload_v8i8_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v9, v26
-; LMULMAX1-NEXT: vzext.vf4 v8, v25
+; LMULMAX1-NEXT: vzext.vf4 v9, v8
+; LMULMAX1-NEXT: vzext.vf4 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i8_v8i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX4-NEXT: vzext.vf4 v8, v25
+; LMULMAX4-NEXT: vzext.vf4 v8, v10
; LMULMAX4-NEXT: ret
%y = load <8 x i8>, <8 x i8>* %x
%z = zext <8 x i8> %y to <8 x i32>
@@ -274,28 +274,28 @@ define <8 x i64> @sextload_v8i8_v8i64(<8 x i8>* %x) {
; LMULMAX1-LABEL: sextload_v8i8_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v10, v26
+; LMULMAX1-NEXT: vsext.vf8 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v9, v27
+; LMULMAX1-NEXT: vsext.vf8 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v11, v26
-; LMULMAX1-NEXT: vsext.vf8 v8, v25
+; LMULMAX1-NEXT: vsext.vf8 v11, v8
+; LMULMAX1-NEXT: vsext.vf8 v8, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i8_v8i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX4-NEXT: vsext.vf8 v8, v25
+; LMULMAX4-NEXT: vsext.vf8 v8, v12
; LMULMAX4-NEXT: ret
%y = load <8 x i8>, <8 x i8>* %x
%z = sext <8 x i8> %y to <8 x i64>
@@ -306,28 +306,28 @@ define <8 x i64> @zextload_v8i8_v8i64(<8 x i8>* %x) {
; LMULMAX1-LABEL: zextload_v8i8_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v10, v26
+; LMULMAX1-NEXT: vzext.vf8 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v9, v27
+; LMULMAX1-NEXT: vzext.vf8 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v11, v26
-; LMULMAX1-NEXT: vzext.vf8 v8, v25
+; LMULMAX1-NEXT: vzext.vf8 v11, v8
+; LMULMAX1-NEXT: vzext.vf8 v8, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i8_v8i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX4-NEXT: vzext.vf8 v8, v25
+; LMULMAX4-NEXT: vzext.vf8 v8, v12
; LMULMAX4-NEXT: ret
%y = load <8 x i8>, <8 x i8>* %x
%z = zext <8 x i8> %y to <8 x i64>
@@ -338,20 +338,20 @@ define <16 x i16> @sextload_v16i8_v16i16(<16 x i8>* %x) {
; LMULMAX1-LABEL: sextload_v16i8_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v9, v26
-; LMULMAX1-NEXT: vsext.vf2 v8, v25
+; LMULMAX1-NEXT: vsext.vf2 v9, v8
+; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i8_v16i16:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; LMULMAX4-NEXT: vsext.vf2 v8, v25
+; LMULMAX4-NEXT: vsext.vf2 v8, v10
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, <16 x i8>* %x
%z = sext <16 x i8> %y to <16 x i16>
@@ -362,20 +362,20 @@ define <16 x i16> @zextload_v16i8_v16i16(<16 x i8>* %x) {
; LMULMAX1-LABEL: zextload_v16i8_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v9, v26
-; LMULMAX1-NEXT: vzext.vf2 v8, v25
+; LMULMAX1-NEXT: vzext.vf2 v9, v8
+; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i8_v16i16:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; LMULMAX4-NEXT: vzext.vf2 v8, v25
+; LMULMAX4-NEXT: vzext.vf2 v8, v10
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, <16 x i8>* %x
%z = zext <16 x i8> %y to <16 x i16>
@@ -386,28 +386,28 @@ define <16 x i32> @sextload_v16i8_v16i32(<16 x i8>* %x) {
; LMULMAX1-LABEL: sextload_v16i8_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v10, v26
+; LMULMAX1-NEXT: vsext.vf4 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v9, v27
+; LMULMAX1-NEXT: vsext.vf4 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v11, v26
-; LMULMAX1-NEXT: vsext.vf4 v8, v25
+; LMULMAX1-NEXT: vsext.vf4 v11, v8
+; LMULMAX1-NEXT: vsext.vf4 v8, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i8_v16i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; LMULMAX4-NEXT: vsext.vf4 v8, v25
+; LMULMAX4-NEXT: vsext.vf4 v8, v12
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, <16 x i8>* %x
%z = sext <16 x i8> %y to <16 x i32>
@@ -418,28 +418,28 @@ define <16 x i32> @zextload_v16i8_v16i32(<16 x i8>* %x) {
; LMULMAX1-LABEL: zextload_v16i8_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v10, v26
+; LMULMAX1-NEXT: vzext.vf4 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v9, v27
+; LMULMAX1-NEXT: vzext.vf4 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v11, v26
-; LMULMAX1-NEXT: vzext.vf4 v8, v25
+; LMULMAX1-NEXT: vzext.vf4 v11, v8
+; LMULMAX1-NEXT: vzext.vf4 v8, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i8_v16i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; LMULMAX4-NEXT: vzext.vf4 v8, v25
+; LMULMAX4-NEXT: vzext.vf4 v8, v12
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, <16 x i8>* %x
%z = zext <16 x i8> %y to <16 x i32>
@@ -450,47 +450,47 @@ define <16 x i64> @sextload_v16i8_v16i64(<16 x i8>* %x) {
; LMULMAX1-LABEL: sextload_v16i8_v16i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX1-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v12, v26
+; LMULMAX1-NEXT: vsext.vf8 v12, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v9, v27
+; LMULMAX1-NEXT: vsext.vf8 v9, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v11, v16, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v10, v27
+; LMULMAX1-NEXT: vsext.vf8 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v14, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v13, v28
+; LMULMAX1-NEXT: vsext.vf8 v13, v14
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v14, v26
+; LMULMAX1-NEXT: vsext.vf8 v14, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v15, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v11, v27
+; LMULMAX1-NEXT: vsext.vf8 v11, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf8 v15, v26
-; LMULMAX1-NEXT: vsext.vf8 v8, v25
+; LMULMAX1-NEXT: vsext.vf8 v15, v8
+; LMULMAX1-NEXT: vsext.vf8 v8, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i8_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX4-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX4-NEXT: vsext.vf8 v12, v26
-; LMULMAX4-NEXT: vsext.vf8 v8, v25
+; LMULMAX4-NEXT: vsext.vf8 v12, v8
+; LMULMAX4-NEXT: vsext.vf8 v8, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, <16 x i8>* %x
%z = sext <16 x i8> %y to <16 x i64>
@@ -501,47 +501,47 @@ define <16 x i64> @zextload_v16i8_v16i64(<16 x i8>* %x) {
; LMULMAX1-LABEL: zextload_v16i8_v16i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX1-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v12, v26
+; LMULMAX1-NEXT: vzext.vf8 v12, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v9, v27
+; LMULMAX1-NEXT: vzext.vf8 v9, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v11, v16, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v10, v27
+; LMULMAX1-NEXT: vzext.vf8 v10, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v14, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v13, v28
+; LMULMAX1-NEXT: vzext.vf8 v13, v14
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v14, v26
+; LMULMAX1-NEXT: vzext.vf8 v14, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v15, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v11, v27
+; LMULMAX1-NEXT: vzext.vf8 v11, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf8 v15, v26
-; LMULMAX1-NEXT: vzext.vf8 v8, v25
+; LMULMAX1-NEXT: vzext.vf8 v15, v8
+; LMULMAX1-NEXT: vzext.vf8 v8, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i8_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vle8.v v25, (a0)
+; LMULMAX4-NEXT: vle8.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX4-NEXT: vslidedown.vi v26, v25, 8
+; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX4-NEXT: vzext.vf8 v12, v26
-; LMULMAX4-NEXT: vzext.vf8 v8, v25
+; LMULMAX4-NEXT: vzext.vf8 v12, v8
+; LMULMAX4-NEXT: vzext.vf8 v8, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i8>, <16 x i8>* %x
%z = zext <16 x i8> %y to <16 x i64>
@@ -552,17 +552,17 @@ define void @truncstore_v2i8_v2i1(<2 x i8> %x, <2 x i1>* %z) {
; CHECK-LABEL: truncstore_v2i8_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i8> %x to <2 x i1>
store <2 x i1> %y, <2 x i1>* %z
@@ -573,8 +573,8 @@ define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) {
; CHECK-LABEL: truncstore_v2i16_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i16> %x to <2 x i8>
store <2 x i8> %y, <2 x i8>* %z
@@ -585,9 +585,9 @@ define <2 x i32> @sextload_v2i16_v2i32(<2 x i16>* %x) {
; CHECK-LABEL: sextload_v2i16_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i16>, <2 x i16>* %x
%z = sext <2 x i16> %y to <2 x i32>
@@ -598,9 +598,9 @@ define <2 x i32> @zextload_v2i16_v2i32(<2 x i16>* %x) {
; CHECK-LABEL: zextload_v2i16_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i16>, <2 x i16>* %x
%z = zext <2 x i16> %y to <2 x i32>
@@ -611,9 +611,9 @@ define <2 x i64> @sextload_v2i16_v2i64(<2 x i16>* %x) {
; CHECK-LABEL: sextload_v2i16_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v8, v25
+; CHECK-NEXT: vsext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i16>, <2 x i16>* %x
%z = sext <2 x i16> %y to <2 x i64>
@@ -624,9 +624,9 @@ define <2 x i64> @zextload_v2i16_v2i64(<2 x i16>* %x) {
; CHECK-LABEL: zextload_v2i16_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v8, v25
+; CHECK-NEXT: vzext.vf4 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i16>, <2 x i16>* %x
%z = zext <2 x i16> %y to <2 x i64>
@@ -637,8 +637,8 @@ define void @truncstore_v4i16_v4i8(<4 x i16> %x, <4 x i8>* %z) {
; CHECK-LABEL: truncstore_v4i16_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <4 x i16> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z
@@ -649,9 +649,9 @@ define <4 x i32> @sextload_v4i16_v4i32(<4 x i16>* %x) {
; CHECK-LABEL: sextload_v4i16_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <4 x i16>, <4 x i16>* %x
%z = sext <4 x i16> %y to <4 x i32>
@@ -662,9 +662,9 @@ define <4 x i32> @zextload_v4i16_v4i32(<4 x i16>* %x) {
; CHECK-LABEL: zextload_v4i16_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <4 x i16>, <4 x i16>* %x
%z = zext <4 x i16> %y to <4 x i32>
@@ -675,20 +675,20 @@ define <4 x i64> @sextload_v4i16_v4i64(<4 x i16>* %x) {
; LMULMAX1-LABEL: sextload_v4i16_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v9, v26
-; LMULMAX1-NEXT: vsext.vf4 v8, v25
+; LMULMAX1-NEXT: vsext.vf4 v9, v8
+; LMULMAX1-NEXT: vsext.vf4 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v4i16_v4i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX4-NEXT: vle16.v v25, (a0)
+; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; LMULMAX4-NEXT: vsext.vf4 v8, v25
+; LMULMAX4-NEXT: vsext.vf4 v8, v10
; LMULMAX4-NEXT: ret
%y = load <4 x i16>, <4 x i16>* %x
%z = sext <4 x i16> %y to <4 x i64>
@@ -699,20 +699,20 @@ define <4 x i64> @zextload_v4i16_v4i64(<4 x i16>* %x) {
; LMULMAX1-LABEL: zextload_v4i16_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v9, v26
-; LMULMAX1-NEXT: vzext.vf4 v8, v25
+; LMULMAX1-NEXT: vzext.vf4 v9, v8
+; LMULMAX1-NEXT: vzext.vf4 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v4i16_v4i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX4-NEXT: vle16.v v25, (a0)
+; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; LMULMAX4-NEXT: vzext.vf4 v8, v25
+; LMULMAX4-NEXT: vzext.vf4 v8, v10
; LMULMAX4-NEXT: ret
%y = load <4 x i16>, <4 x i16>* %x
%z = zext <4 x i16> %y to <4 x i64>
@@ -723,8 +723,8 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %z) {
; CHECK-LABEL: truncstore_v8i16_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <8 x i16> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z
@@ -735,20 +735,20 @@ define <8 x i32> @sextload_v8i16_v8i32(<8 x i16>* %x) {
; LMULMAX1-LABEL: sextload_v8i16_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v9, v26
-; LMULMAX1-NEXT: vsext.vf2 v8, v25
+; LMULMAX1-NEXT: vsext.vf2 v9, v8
+; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i16_v8i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX4-NEXT: vle16.v v25, (a0)
+; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX4-NEXT: vsext.vf2 v8, v25
+; LMULMAX4-NEXT: vsext.vf2 v8, v10
; LMULMAX4-NEXT: ret
%y = load <8 x i16>, <8 x i16>* %x
%z = sext <8 x i16> %y to <8 x i32>
@@ -759,20 +759,20 @@ define <8 x i32> @zextload_v8i16_v8i32(<8 x i16>* %x) {
; LMULMAX1-LABEL: zextload_v8i16_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v9, v26
-; LMULMAX1-NEXT: vzext.vf2 v8, v25
+; LMULMAX1-NEXT: vzext.vf2 v9, v8
+; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i16_v8i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX4-NEXT: vle16.v v25, (a0)
+; LMULMAX4-NEXT: vle16.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX4-NEXT: vzext.vf2 v8, v25
+; LMULMAX4-NEXT: vzext.vf2 v8, v10
; LMULMAX4-NEXT: ret
%y = load <8 x i16>, <8 x i16>* %x
%z = zext <8 x i16> %y to <8 x i32>
@@ -783,28 +783,28 @@ define <8 x i64> @sextload_v8i16_v8i64(<8 x i16>* %x) {
; LMULMAX1-LABEL: sextload_v8i16_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v10, v26
+; LMULMAX1-NEXT: vsext.vf4 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v9, v27
+; LMULMAX1-NEXT: vsext.vf4 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v11, v26
-; LMULMAX1-NEXT: vsext.vf4 v8, v25
+; LMULMAX1-NEXT: vsext.vf4 v11, v8
+; LMULMAX1-NEXT: vsext.vf4 v8, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i16_v8i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX4-NEXT: vle16.v v25, (a0)
+; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX4-NEXT: vsext.vf4 v8, v25
+; LMULMAX4-NEXT: vsext.vf4 v8, v12
; LMULMAX4-NEXT: ret
%y = load <8 x i16>, <8 x i16>* %x
%z = sext <8 x i16> %y to <8 x i64>
@@ -815,28 +815,28 @@ define <8 x i64> @zextload_v8i16_v8i64(<8 x i16>* %x) {
; LMULMAX1-LABEL: zextload_v8i16_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v10, v26
+; LMULMAX1-NEXT: vzext.vf4 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v9, v27
+; LMULMAX1-NEXT: vzext.vf4 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v11, v26
-; LMULMAX1-NEXT: vzext.vf4 v8, v25
+; LMULMAX1-NEXT: vzext.vf4 v11, v8
+; LMULMAX1-NEXT: vzext.vf4 v8, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i16_v8i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX4-NEXT: vle16.v v25, (a0)
+; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX4-NEXT: vzext.vf4 v8, v25
+; LMULMAX4-NEXT: vzext.vf4 v8, v12
; LMULMAX4-NEXT: ret
%y = load <8 x i16>, <8 x i16>* %x
%z = zext <8 x i16> %y to <8 x i64>
@@ -847,23 +847,23 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i16_v16i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 8
-; LMULMAX1-NEXT: vse8.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 8
+; LMULMAX1-NEXT: vse8.v v10, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i16_v16i8:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
-; LMULMAX4-NEXT: vse8.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
+; LMULMAX4-NEXT: vse8.v v10, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <16 x i16> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z
@@ -874,27 +874,27 @@ define <16 x i32> @sextload_v16i16_v16i32(<16 x i16>* %x) {
; LMULMAX1-LABEL: sextload_v16i16_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle16.v v26, (a0)
+; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v9, v27
+; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v11, v27
-; LMULMAX1-NEXT: vsext.vf2 v8, v25
-; LMULMAX1-NEXT: vsext.vf2 v10, v26
+; LMULMAX1-NEXT: vsext.vf2 v11, v8
+; LMULMAX1-NEXT: vsext.vf2 v8, v10
+; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i16_v16i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX4-NEXT: vle16.v v26, (a0)
+; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; LMULMAX4-NEXT: vsext.vf2 v8, v26
+; LMULMAX4-NEXT: vsext.vf2 v8, v12
; LMULMAX4-NEXT: ret
%y = load <16 x i16>, <16 x i16>* %x
%z = sext <16 x i16> %y to <16 x i32>
@@ -905,27 +905,27 @@ define <16 x i32> @zextload_v16i16_v16i32(<16 x i16>* %x) {
; LMULMAX1-LABEL: zextload_v16i16_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle16.v v26, (a0)
+; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v9, v27
+; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v11, v27
-; LMULMAX1-NEXT: vzext.vf2 v8, v25
-; LMULMAX1-NEXT: vzext.vf2 v10, v26
+; LMULMAX1-NEXT: vzext.vf2 v11, v8
+; LMULMAX1-NEXT: vzext.vf2 v8, v10
+; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i16_v16i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX4-NEXT: vle16.v v26, (a0)
+; LMULMAX4-NEXT: vle16.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; LMULMAX4-NEXT: vzext.vf2 v8, v26
+; LMULMAX4-NEXT: vzext.vf2 v8, v12
; LMULMAX4-NEXT: ret
%y = load <16 x i16>, <16 x i16>* %x
%z = zext <16 x i16> %y to <16 x i32>
@@ -936,46 +936,46 @@ define <16 x i64> @sextload_v16i16_v16i64(<16 x i16>* %x) {
; LMULMAX1-LABEL: sextload_v16i16_v16i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle16.v v26, (a0)
+; LMULMAX1-NEXT: vle16.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v10, v27
+; LMULMAX1-NEXT: vsext.vf4 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v15, v16, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v14, v28
+; LMULMAX1-NEXT: vsext.vf4 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v9, v29
+; LMULMAX1-NEXT: vsext.vf4 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v11, v27
+; LMULMAX1-NEXT: vsext.vf4 v11, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v13, v27
+; LMULMAX1-NEXT: vsext.vf4 v13, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v28, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v15, v27
-; LMULMAX1-NEXT: vsext.vf4 v8, v25
-; LMULMAX1-NEXT: vsext.vf4 v12, v26
+; LMULMAX1-NEXT: vsext.vf4 v15, v8
+; LMULMAX1-NEXT: vsext.vf4 v8, v12
+; LMULMAX1-NEXT: vsext.vf4 v12, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i16_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX4-NEXT: vle16.v v26, (a0)
+; LMULMAX4-NEXT: vle16.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; LMULMAX4-NEXT: vslidedown.vi v28, v26, 8
+; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX4-NEXT: vsext.vf4 v12, v28
-; LMULMAX4-NEXT: vsext.vf4 v8, v26
+; LMULMAX4-NEXT: vsext.vf4 v12, v8
+; LMULMAX4-NEXT: vsext.vf4 v8, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i16>, <16 x i16>* %x
%z = sext <16 x i16> %y to <16 x i64>
@@ -986,46 +986,46 @@ define <16 x i64> @zextload_v16i16_v16i64(<16 x i16>* %x) {
; LMULMAX1-LABEL: zextload_v16i16_v16i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v12, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle16.v v26, (a0)
+; LMULMAX1-NEXT: vle16.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v10, v27
+; LMULMAX1-NEXT: vzext.vf4 v10, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v15, v16, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v14, v28
+; LMULMAX1-NEXT: vzext.vf4 v14, v15
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v9, v29
+; LMULMAX1-NEXT: vzext.vf4 v9, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v11, v27
+; LMULMAX1-NEXT: vzext.vf4 v11, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v13, v27
+; LMULMAX1-NEXT: vzext.vf4 v13, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v28, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v15, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v15, v27
-; LMULMAX1-NEXT: vzext.vf4 v8, v25
-; LMULMAX1-NEXT: vzext.vf4 v12, v26
+; LMULMAX1-NEXT: vzext.vf4 v15, v8
+; LMULMAX1-NEXT: vzext.vf4 v8, v12
+; LMULMAX1-NEXT: vzext.vf4 v12, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i16_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX4-NEXT: vle16.v v26, (a0)
+; LMULMAX4-NEXT: vle16.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; LMULMAX4-NEXT: vslidedown.vi v28, v26, 8
+; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX4-NEXT: vzext.vf4 v12, v28
-; LMULMAX4-NEXT: vzext.vf4 v8, v26
+; LMULMAX4-NEXT: vzext.vf4 v12, v8
+; LMULMAX4-NEXT: vzext.vf4 v8, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i16>, <16 x i16>* %x
%z = zext <16 x i16> %y to <16 x i64>
@@ -1036,10 +1036,10 @@ define void @truncstore_v2i32_v2i8(<2 x i32> %x, <2 x i8>* %z) {
; CHECK-LABEL: truncstore_v2i32_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i32> %x to <2 x i8>
store <2 x i8> %y, <2 x i8>* %z
@@ -1050,8 +1050,8 @@ define void @truncstore_v2i32_v2i16(<2 x i32> %x, <2 x i16>* %z) {
; CHECK-LABEL: truncstore_v2i32_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i32> %x to <2 x i16>
store <2 x i16> %y, <2 x i16>* %z
@@ -1062,9 +1062,9 @@ define <2 x i64> @sextload_v2i32_v2i64(<2 x i32>* %x) {
; CHECK-LABEL: sextload_v2i32_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v8, v25
+; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i32>, <2 x i32>* %x
%z = sext <2 x i32> %y to <2 x i64>
@@ -1075,9 +1075,9 @@ define <2 x i64> @zextload_v2i32_v2i64(<2 x i32>* %x) {
; CHECK-LABEL: zextload_v2i32_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v8, v25
+; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%y = load <2 x i32>, <2 x i32>* %x
%z = zext <2 x i32> %y to <2 x i64>
@@ -1088,10 +1088,10 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %z) {
; CHECK-LABEL: truncstore_v4i32_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <4 x i32> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z
@@ -1102,8 +1102,8 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %z) {
; CHECK-LABEL: truncstore_v4i32_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <4 x i32> %x to <4 x i16>
store <4 x i16> %y, <4 x i16>* %z
@@ -1114,20 +1114,20 @@ define <4 x i64> @sextload_v4i32_v4i64(<4 x i32>* %x) {
; LMULMAX1-LABEL: sextload_v4i32_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v9, v26
-; LMULMAX1-NEXT: vsext.vf2 v8, v25
+; LMULMAX1-NEXT: vsext.vf2 v9, v8
+; LMULMAX1-NEXT: vsext.vf2 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v4i32_v4i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX4-NEXT: vle32.v v25, (a0)
+; LMULMAX4-NEXT: vle32.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; LMULMAX4-NEXT: vsext.vf2 v8, v25
+; LMULMAX4-NEXT: vsext.vf2 v8, v10
; LMULMAX4-NEXT: ret
%y = load <4 x i32>, <4 x i32>* %x
%z = sext <4 x i32> %y to <4 x i64>
@@ -1138,20 +1138,20 @@ define <4 x i64> @zextload_v4i32_v4i64(<4 x i32>* %x) {
; LMULMAX1-LABEL: zextload_v4i32_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v9, v26
-; LMULMAX1-NEXT: vzext.vf2 v8, v25
+; LMULMAX1-NEXT: vzext.vf2 v9, v8
+; LMULMAX1-NEXT: vzext.vf2 v8, v10
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v4i32_v4i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX4-NEXT: vle32.v v25, (a0)
+; LMULMAX4-NEXT: vle32.v v10, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; LMULMAX4-NEXT: vzext.vf2 v8, v25
+; LMULMAX4-NEXT: vzext.vf2 v8, v10
; LMULMAX4-NEXT: ret
%y = load <4 x i32>, <4 x i32>* %x
%z = zext <4 x i32> %y to <4 x i64>
@@ -1162,29 +1162,29 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v8i32_v8i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
-; LMULMAX1-NEXT: vse8.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
+; LMULMAX1-NEXT: vse8.v v10, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v8i32_v8i8:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX4-NEXT: vse8.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0
+; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <8 x i32> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z
@@ -1195,23 +1195,23 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v8i32_v8i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
-; LMULMAX1-NEXT: vse16.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
+; LMULMAX1-NEXT: vse16.v v10, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v8i32_v8i16:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
-; LMULMAX4-NEXT: vse16.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
+; LMULMAX4-NEXT: vse16.v v10, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <8 x i32> %x to <8 x i16>
store <8 x i16> %y, <8 x i16>* %z
@@ -1222,27 +1222,27 @@ define <8 x i64> @sextload_v8i32_v8i64(<8 x i32>* %x) {
; LMULMAX1-LABEL: sextload_v8i32_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v9, v27
+; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v11, v27
-; LMULMAX1-NEXT: vsext.vf2 v8, v25
-; LMULMAX1-NEXT: vsext.vf2 v10, v26
+; LMULMAX1-NEXT: vsext.vf2 v11, v8
+; LMULMAX1-NEXT: vsext.vf2 v8, v10
+; LMULMAX1-NEXT: vsext.vf2 v10, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v8i32_v8i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vle32.v v26, (a0)
+; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX4-NEXT: vsext.vf2 v8, v26
+; LMULMAX4-NEXT: vsext.vf2 v8, v12
; LMULMAX4-NEXT: ret
%y = load <8 x i32>, <8 x i32>* %x
%z = sext <8 x i32> %y to <8 x i64>
@@ -1253,27 +1253,27 @@ define <8 x i64> @zextload_v8i32_v8i64(<8 x i32>* %x) {
; LMULMAX1-LABEL: zextload_v8i32_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v9, v27
+; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v11, v27
-; LMULMAX1-NEXT: vzext.vf2 v8, v25
-; LMULMAX1-NEXT: vzext.vf2 v10, v26
+; LMULMAX1-NEXT: vzext.vf2 v11, v8
+; LMULMAX1-NEXT: vzext.vf2 v8, v10
+; LMULMAX1-NEXT: vzext.vf2 v10, v12
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v8i32_v8i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vle32.v v26, (a0)
+; LMULMAX4-NEXT: vle32.v v12, (a0)
; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX4-NEXT: vzext.vf2 v8, v26
+; LMULMAX4-NEXT: vzext.vf2 v8, v12
; LMULMAX4-NEXT: ret
%y = load <8 x i32>, <8 x i32>* %x
%z = zext <8 x i32> %y to <8 x i64>
@@ -1284,41 +1284,41 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i32_v16i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 8
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 12
-; LMULMAX1-NEXT: vse8.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 12
+; LMULMAX1-NEXT: vse8.v v12, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i32_v16i8:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0
-; LMULMAX4-NEXT: vse8.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0
+; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <16 x i32> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z
@@ -1329,34 +1329,34 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i32_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vmv1r.v v27, v26
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 0
+; LMULMAX1-NEXT: vmv1r.v v13, v12
+; LMULMAX1-NEXT: vslideup.vi v13, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v13, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 4
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse16.v v26, (a1)
-; LMULMAX1-NEXT: vse16.v v27, (a0)
+; LMULMAX1-NEXT: vse16.v v12, (a1)
+; LMULMAX1-NEXT: vse16.v v13, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i32_v16i16:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0
-; LMULMAX4-NEXT: vse16.v v26, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
+; LMULMAX4-NEXT: vse16.v v12, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <16 x i32> %x to <16 x i16>
store <16 x i16> %y, <16 x i16>* %z
@@ -1368,43 +1368,43 @@ define <16 x i64> @sextload_v16i32_v16i64(<16 x i32>* %x) {
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v16, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
-; LMULMAX1-NEXT: vle32.v v26, (a1)
-; LMULMAX1-NEXT: vle32.v v27, (a0)
+; LMULMAX1-NEXT: vle32.v v14, (a1)
+; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle32.v v28, (a0)
+; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v9, v29
+; LMULMAX1-NEXT: vsext.vf2 v9, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v28, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v11, v29
+; LMULMAX1-NEXT: vsext.vf2 v11, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v14, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v13, v29
+; LMULMAX1-NEXT: vsext.vf2 v13, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf2 v15, v29
-; LMULMAX1-NEXT: vsext.vf2 v8, v27
-; LMULMAX1-NEXT: vsext.vf2 v10, v28
-; LMULMAX1-NEXT: vsext.vf2 v12, v26
-; LMULMAX1-NEXT: vsext.vf2 v14, v25
+; LMULMAX1-NEXT: vsext.vf2 v15, v8
+; LMULMAX1-NEXT: vsext.vf2 v8, v10
+; LMULMAX1-NEXT: vsext.vf2 v10, v12
+; LMULMAX1-NEXT: vsext.vf2 v12, v14
+; LMULMAX1-NEXT: vsext.vf2 v14, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: sextload_v16i32_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (a0)
+; LMULMAX4-NEXT: vle32.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, mu
-; LMULMAX4-NEXT: vslidedown.vi v8, v28, 8
+; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; LMULMAX4-NEXT: vsext.vf2 v12, v8
-; LMULMAX4-NEXT: vsext.vf2 v8, v28
+; LMULMAX4-NEXT: vsext.vf2 v8, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i32>, <16 x i32>* %x
%z = sext <16 x i32> %y to <16 x i64>
@@ -1416,43 +1416,43 @@ define <16 x i64> @zextload_v16i32_v16i64(<16 x i32>* %x) {
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v16, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
-; LMULMAX1-NEXT: vle32.v v26, (a1)
-; LMULMAX1-NEXT: vle32.v v27, (a0)
+; LMULMAX1-NEXT: vle32.v v14, (a1)
+; LMULMAX1-NEXT: vle32.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle32.v v28, (a0)
+; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v9, v29
+; LMULMAX1-NEXT: vzext.vf2 v9, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v28, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v11, v29
+; LMULMAX1-NEXT: vzext.vf2 v11, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v14, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v13, v29
+; LMULMAX1-NEXT: vzext.vf2 v13, v8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf2 v15, v29
-; LMULMAX1-NEXT: vzext.vf2 v8, v27
-; LMULMAX1-NEXT: vzext.vf2 v10, v28
-; LMULMAX1-NEXT: vzext.vf2 v12, v26
-; LMULMAX1-NEXT: vzext.vf2 v14, v25
+; LMULMAX1-NEXT: vzext.vf2 v15, v8
+; LMULMAX1-NEXT: vzext.vf2 v8, v10
+; LMULMAX1-NEXT: vzext.vf2 v10, v12
+; LMULMAX1-NEXT: vzext.vf2 v12, v14
+; LMULMAX1-NEXT: vzext.vf2 v14, v16
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: zextload_v16i32_v16i64:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vle32.v v28, (a0)
+; LMULMAX4-NEXT: vle32.v v16, (a0)
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, mu
-; LMULMAX4-NEXT: vslidedown.vi v8, v28, 8
+; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; LMULMAX4-NEXT: vzext.vf2 v12, v8
-; LMULMAX4-NEXT: vzext.vf2 v8, v28
+; LMULMAX4-NEXT: vzext.vf2 v8, v16
; LMULMAX4-NEXT: ret
%y = load <16 x i32>, <16 x i32>* %x
%z = zext <16 x i32> %y to <16 x i64>
@@ -1463,12 +1463,12 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %z) {
; CHECK-LABEL: truncstore_v2i64_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i8>
store <2 x i8> %y, <2 x i8>* %z
@@ -1479,10 +1479,10 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %z) {
; CHECK-LABEL: truncstore_v2i64_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i16>
store <2 x i16> %y, <2 x i16>* %z
@@ -1493,8 +1493,8 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %z) {
; CHECK-LABEL: truncstore_v2i64_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i64> %x to <2 x i32>
store <2 x i32> %y, <2 x i32>* %z
@@ -1505,35 +1505,35 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
-; LMULMAX1-NEXT: vse8.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 2
+; LMULMAX1-NEXT: vse8.v v10, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v4i64_v4i8:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX4-NEXT: vse8.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0
+; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z
@@ -1544,29 +1544,29 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
-; LMULMAX1-NEXT: vse16.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 2
+; LMULMAX1-NEXT: vse16.v v10, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v4i64_v4i16:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX4-NEXT: vse16.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0
+; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i16>
store <4 x i16> %y, <4 x i16>* %z
@@ -1577,23 +1577,23 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
-; LMULMAX1-NEXT: vse32.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 2
+; LMULMAX1-NEXT: vse32.v v10, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v4i64_v4i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0
-; LMULMAX4-NEXT: vse32.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
+; LMULMAX4-NEXT: vse32.v v10, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i32>
store <4 x i32> %y, <4 x i32>* %z
@@ -1604,51 +1604,51 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 6
-; LMULMAX1-NEXT: vse8.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 6
+; LMULMAX1-NEXT: vse8.v v12, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v8i64_v8i8:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX4-NEXT: vse8.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0
+; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z
@@ -1659,41 +1659,41 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 6
-; LMULMAX1-NEXT: vse16.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 6
+; LMULMAX1-NEXT: vse16.v v12, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v8i64_v8i16:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0
-; LMULMAX4-NEXT: vse16.v v25, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0
+; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i16>
store <8 x i16> %y, <8 x i16>* %z
@@ -1704,34 +1704,34 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vmv1r.v v27, v26
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 0
+; LMULMAX1-NEXT: vmv1r.v v13, v12
+; LMULMAX1-NEXT: vslideup.vi v13, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v13, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 2
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse32.v v26, (a1)
-; LMULMAX1-NEXT: vse32.v v27, (a0)
+; LMULMAX1-NEXT: vse32.v v12, (a1)
+; LMULMAX1-NEXT: vse32.v v13, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v8i64_v8i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0
-; LMULMAX4-NEXT: vse32.v v26, (a0)
+; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
+; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i32>
store <8 x i32> %y, <8 x i32>* %z
@@ -1742,95 +1742,95 @@ define void @truncstore_v16i64_v16i8(<16 x i64> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v16, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 0
+; LMULMAX1-NEXT: vslideup.vi v8, v16, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 2
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 6
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v12, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 10, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 8
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v13, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v13, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 10
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 10
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v14, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v14, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 14, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 12
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 12
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v15, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v15, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 14
-; LMULMAX1-NEXT: vse8.v v25, (a0)
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 14
+; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i64_v16i8:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v16, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX4-NEXT: vnsrl.wi v8, v16, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX4-NEXT: vmv.v.i v26, 0
+; LMULMAX4-NEXT: vmv.v.i v9, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, tu, mu
-; LMULMAX4-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX4-NEXT: vslideup.vi v9, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v28, v12, 0
+; LMULMAX4-NEXT: vnsrl.wi v10, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v28, 0
+; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu
-; LMULMAX4-NEXT: vslideup.vi v26, v25, 8
-; LMULMAX4-NEXT: vse8.v v26, (a0)
+; LMULMAX4-NEXT: vslideup.vi v9, v8, 8
+; LMULMAX4-NEXT: vse8.v v9, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z
@@ -1841,78 +1841,78 @@ define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v16, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
-; LMULMAX1-NEXT: vmv1r.v v27, v26
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 0
+; LMULMAX1-NEXT: vmv1r.v v17, v16
+; LMULMAX1-NEXT: vslideup.vi v17, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v17, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v17, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 6
+; LMULMAX1-NEXT: vslideup.vi v17, v8, 6
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v12, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v16, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v13, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v13, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v16, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v14, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v14, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 4
+; LMULMAX1-NEXT: vslideup.vi v16, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v15, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v15, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 6
+; LMULMAX1-NEXT: vslideup.vi v16, v8, 6
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse16.v v26, (a1)
-; LMULMAX1-NEXT: vse16.v v27, (a0)
+; LMULMAX1-NEXT: vse16.v v16, (a1)
+; LMULMAX1-NEXT: vse16.v v17, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i64_v16i16:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v12, 0
+; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v28, v26, 0
+; LMULMAX4-NEXT: vnsrl.wi v12, v16, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0
+; LMULMAX4-NEXT: vnsrl.wi v14, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v30, v26, 0
+; LMULMAX4-NEXT: vnsrl.wi v8, v14, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX4-NEXT: vmv.v.i v26, 0
+; LMULMAX4-NEXT: vmv.v.i v10, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, tu, mu
-; LMULMAX4-NEXT: vslideup.vi v26, v30, 0
+; LMULMAX4-NEXT: vslideup.vi v10, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu
-; LMULMAX4-NEXT: vslideup.vi v26, v28, 8
-; LMULMAX4-NEXT: vse16.v v26, (a0)
+; LMULMAX4-NEXT: vslideup.vi v10, v12, 8
+; LMULMAX4-NEXT: vse16.v v10, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i16>
store <16 x i16> %y, <16 x i16>* %z
@@ -1923,62 +1923,62 @@ define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v16, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vmv1r.v v27, v26
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 0
+; LMULMAX1-NEXT: vmv1r.v v17, v16
+; LMULMAX1-NEXT: vslideup.vi v17, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v17, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vmv1r.v v28, v26
-; LMULMAX1-NEXT: vslideup.vi v28, v25, 0
+; LMULMAX1-NEXT: vmv1r.v v9, v16
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v28, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v12, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vmv1r.v v29, v26
-; LMULMAX1-NEXT: vslideup.vi v29, v25, 0
+; LMULMAX1-NEXT: vmv1r.v v10, v16
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v13, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v13, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v14, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v14, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v16, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v15, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v15, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v16, v8, 2
; LMULMAX1-NEXT: addi a1, a0, 48
-; LMULMAX1-NEXT: vse32.v v26, (a1)
+; LMULMAX1-NEXT: vse32.v v16, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32
-; LMULMAX1-NEXT: vse32.v v29, (a1)
+; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse32.v v28, (a1)
-; LMULMAX1-NEXT: vse32.v v27, (a0)
+; LMULMAX1-NEXT: vse32.v v9, (a1)
+; LMULMAX1-NEXT: vse32.v v17, (a0)
; LMULMAX1-NEXT: ret
;
; LMULMAX4-LABEL: truncstore_v16i64_v16i32:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX4-NEXT: vnsrl.wi v28, v12, 0
+; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: vmv.v.i v8, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, tu, mu
; LMULMAX4-NEXT: vslideup.vi v8, v12, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu
-; LMULMAX4-NEXT: vslideup.vi v8, v28, 8
+; LMULMAX4-NEXT: vslideup.vi v8, v16, 8
; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i32>
@@ -1990,8 +1990,8 @@ define <vscale x 2 x float> @extload_nxv2f16_nxv2f32(<vscale x 2 x half>* %x) {
; CHECK-LABEL: extload_nxv2f16_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: ret
%y = load <vscale x 2 x half>, <vscale x 2 x half>* %x
%z = fpext <vscale x 2 x half> %y to <vscale x 2 x float>
@@ -2002,10 +2002,10 @@ define <vscale x 2 x double> @extload_nxv2f16_nxv2f64(<vscale x 2 x half>* %x) {
; CHECK-LABEL: extload_nxv2f16_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x half>, <vscale x 2 x half>* %x
%z = fpext <vscale x 2 x half> %y to <vscale x 2 x double>
@@ -2015,9 +2015,9 @@ define <vscale x 2 x double> @extload_nxv2f16_nxv2f64(<vscale x 2 x half>* %x) {
define <vscale x 4 x float> @extload_nxv4f16_nxv4f32(<vscale x 4 x half>* %x) {
; CHECK-LABEL: extload_nxv4f16_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 4 x half>, <vscale x 4 x half>* %x
%z = fpext <vscale x 4 x half> %y to <vscale x 4 x float>
@@ -2027,11 +2027,11 @@ define <vscale x 4 x float> @extload_nxv4f16_nxv4f32(<vscale x 4 x half>* %x) {
define <vscale x 4 x double> @extload_nxv4f16_nxv4f64(<vscale x 4 x half>* %x) {
; CHECK-LABEL: extload_nxv4f16_nxv4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a0)
+; CHECK-NEXT: vl1re16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x half>, <vscale x 4 x half>* %x
%z = fpext <vscale x 4 x half> %y to <vscale x 4 x double>
@@ -2041,9 +2041,9 @@ define <vscale x 4 x double> @extload_nxv4f16_nxv4f64(<vscale x 4 x half>* %x) {
define <vscale x 8 x float> @extload_nxv8f16_nxv8f32(<vscale x 8 x half>* %x) {
; CHECK-LABEL: extload_nxv8f16_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 8 x half>, <vscale x 8 x half>* %x
%z = fpext <vscale x 8 x half> %y to <vscale x 8 x float>
@@ -2053,11 +2053,11 @@ define <vscale x 8 x float> @extload_nxv8f16_nxv8f32(<vscale x 8 x half>* %x) {
define <vscale x 8 x double> @extload_nxv8f16_nxv8f64(<vscale x 8 x half>* %x) {
; CHECK-LABEL: extload_nxv8f16_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v26
+; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x half>, <vscale x 8 x half>* %x
%z = fpext <vscale x 8 x half> %y to <vscale x 8 x double>
@@ -2067,9 +2067,9 @@ define <vscale x 8 x double> @extload_nxv8f16_nxv8f64(<vscale x 8 x half>* %x) {
define <vscale x 16 x float> @extload_nxv16f16_nxv16f32(<vscale x 16 x half>* %x) {
; CHECK-LABEL: extload_nxv16f16_nxv16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 16 x half>, <vscale x 16 x half>* %x
%z = fpext <vscale x 16 x half> %y to <vscale x 16 x float>
@@ -2079,13 +2079,13 @@ define <vscale x 16 x float> @extload_nxv16f16_nxv16f32(<vscale x 16 x half>* %x
define <vscale x 16 x double> @extload_nxv16f16_nxv16f64(<vscale x 16 x half>* %x) {
; CHECK-LABEL: extload_nxv16f16_nxv16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v16, v28
+; CHECK-NEXT: vfwcvt.f.f.v v20, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v16
+; CHECK-NEXT: vfwcvt.f.f.v v8, v20
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v24, v30
+; CHECK-NEXT: vfwcvt.f.f.v v24, v18
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v16, v24
; CHECK-NEXT: ret
@@ -2098,8 +2098,8 @@ define void @truncstore_nxv2f32_nxv2f16(<vscale x 2 x float> %x, <vscale x 2 x h
; CHECK-LABEL: truncstore_nxv2f32_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 2 x float> %x to <vscale x 2 x half>
store <vscale x 2 x half> %y, <vscale x 2 x half>* %z
@@ -2109,9 +2109,9 @@ define void @truncstore_nxv2f32_nxv2f16(<vscale x 2 x float> %x, <vscale x 2 x h
define <vscale x 2 x double> @extload_nxv2f32_nxv2f64(<vscale x 2 x float>* %x) {
; CHECK-LABEL: extload_nxv2f32_nxv2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re32.v v25, (a0)
+; CHECK-NEXT: vl1re32.v v10, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%y = load <vscale x 2 x float>, <vscale x 2 x float>* %x
%z = fpext <vscale x 2 x float> %y to <vscale x 2 x double>
@@ -2122,8 +2122,8 @@ define void @truncstore_nxv4f32_nxv4f16(<vscale x 4 x float> %x, <vscale x 4 x h
; CHECK-LABEL: truncstore_nxv4f32_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 4 x float> %x to <vscale x 4 x half>
store <vscale x 4 x half> %y, <vscale x 4 x half>* %z
@@ -2133,9 +2133,9 @@ define void @truncstore_nxv4f32_nxv4f16(<vscale x 4 x float> %x, <vscale x 4 x h
define <vscale x 4 x double> @extload_nxv4f32_nxv4f64(<vscale x 4 x float>* %x) {
; CHECK-LABEL: extload_nxv4f32_nxv4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re32.v v26, (a0)
+; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%y = load <vscale x 4 x float>, <vscale x 4 x float>* %x
%z = fpext <vscale x 4 x float> %y to <vscale x 4 x double>
@@ -2146,8 +2146,8 @@ define void @truncstore_nxv8f32_nxv8f16(<vscale x 8 x float> %x, <vscale x 8 x h
; CHECK-LABEL: truncstore_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 8 x float> %x to <vscale x 8 x half>
store <vscale x 8 x half> %y, <vscale x 8 x half>* %z
@@ -2157,9 +2157,9 @@ define void @truncstore_nxv8f32_nxv8f16(<vscale x 8 x float> %x, <vscale x 8 x h
define <vscale x 8 x double> @extload_nxv8f32_nxv8f64(<vscale x 8 x float>* %x) {
; CHECK-LABEL: extload_nxv8f32_nxv8f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v8, v16
; CHECK-NEXT: ret
%y = load <vscale x 8 x float>, <vscale x 8 x float>* %x
%z = fpext <vscale x 8 x float> %y to <vscale x 8 x double>
@@ -2170,8 +2170,8 @@ define void @truncstore_nxv16f32_nxv16f16(<vscale x 16 x float> %x, <vscale x 16
; CHECK-LABEL: truncstore_nxv16f32_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 16 x float> %x to <vscale x 16 x half>
store <vscale x 16 x half> %y, <vscale x 16 x half>* %z
@@ -2195,10 +2195,10 @@ define void @truncstore_nxv2f64_nxv2f16(<vscale x 2 x double> %x, <vscale x 2 x
; CHECK-LABEL: truncstore_nxv2f64_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v8, v10
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 2 x double> %x to <vscale x 2 x half>
store <vscale x 2 x half> %y, <vscale x 2 x half>* %z
@@ -2209,8 +2209,8 @@ define void @truncstore_nxv2f64_nxv2f32(<vscale x 2 x double> %x, <vscale x 2 x
; CHECK-LABEL: truncstore_nxv2f64_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vs1r.v v10, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 2 x double> %x to <vscale x 2 x float>
store <vscale x 2 x float> %y, <vscale x 2 x float>* %z
@@ -2221,10 +2221,10 @@ define void @truncstore_nxv4f64_nxv4f16(<vscale x 4 x double> %x, <vscale x 4 x
; CHECK-LABEL: truncstore_nxv4f64_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v26
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v8, v12
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 4 x double> %x to <vscale x 4 x half>
store <vscale x 4 x half> %y, <vscale x 4 x half>* %z
@@ -2235,8 +2235,8 @@ define void @truncstore_nxv4f64_nxv4f32(<vscale x 4 x double> %x, <vscale x 4 x
; CHECK-LABEL: truncstore_nxv4f64_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vs2r.v v12, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 4 x double> %x to <vscale x 4 x float>
store <vscale x 4 x float> %y, <vscale x 4 x float>* %z
@@ -2247,10 +2247,10 @@ define void @truncstore_nxv8f64_nxv8f16(<vscale x 8 x double> %x, <vscale x 8 x
; CHECK-LABEL: truncstore_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v8, v16
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 8 x double> %x to <vscale x 8 x half>
store <vscale x 8 x half> %y, <vscale x 8 x half>* %z
@@ -2261,8 +2261,8 @@ define void @truncstore_nxv8f64_nxv8f32(<vscale x 8 x double> %x, <vscale x 8 x
; CHECK-LABEL: truncstore_nxv8f64_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 8 x double> %x to <vscale x 8 x float>
store <vscale x 8 x float> %y, <vscale x 8 x float>* %z
@@ -2273,13 +2273,13 @@ define void @truncstore_nxv16f64_nxv16f16(<vscale x 16 x double> %x, <vscale x 1
; CHECK-LABEL: truncstore_nxv16f64_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8
+; CHECK-NEXT: vfncvt.rod.f.f.w v24, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v16
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v10, v28
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: ret
%y = fptrunc <vscale x 16 x double> %x to <vscale x 16 x half>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index aa530f330cf73..341a06c036130 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -6,12 +6,12 @@ define i1 @extractelt_v1i1(<1 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <1 x i8>, <1 x i8>* %x
%b = icmp eq <1 x i8> %a, zeroinitializer
@@ -23,13 +23,13 @@ define i1 @extractelt_v2i1(<2 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = icmp eq <2 x i8> %a, zeroinitializer
@@ -41,13 +41,13 @@ define i1 @extractelt_v4i1(<4 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = icmp eq <4 x i8> %a, zeroinitializer
@@ -59,13 +59,13 @@ define i1 @extractelt_v8i1(<8 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = icmp eq <8 x i8> %a, zeroinitializer
@@ -77,13 +77,13 @@ define i1 @extractelt_v16i1(<16 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = icmp eq <16 x i8> %a, zeroinitializer
@@ -96,13 +96,13 @@ define i1 @extractelt_v32i1(<32 x i8>* %x, i64 %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = icmp eq <32 x i8> %a, zeroinitializer
@@ -115,13 +115,13 @@ define i1 @extractelt_v64i1(<64 x i8>* %x, i64 %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu
-; CHECK-NEXT: vslidedown.vx v28, v28, a1
-; CHECK-NEXT: vmv.x.s a0, v28
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = icmp eq <64 x i8> %a, zeroinitializer
@@ -160,18 +160,18 @@ define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind {
; RV32-NEXT: addi a2, a0, 128
; RV32-NEXT: addi a3, zero, 128
; RV32-NEXT: vsetvli zero, a3, e8, m8, ta, mu
-; RV32-NEXT: vle8.v v8, (a0)
-; RV32-NEXT: vle8.v v16, (a2)
+; RV32-NEXT: vle8.v v16, (a0)
+; RV32-NEXT: vle8.v v24, (a2)
; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: add a0, a0, a1
-; RV32-NEXT: vmseq.vi v25, v8, 0
-; RV32-NEXT: vmseq.vi v0, v16, 0
-; RV32-NEXT: vmv.v.i v8, 0
-; RV32-NEXT: vmerge.vim v16, v8, 1, v0
+; RV32-NEXT: vmseq.vi v8, v16, 0
+; RV32-NEXT: vmseq.vi v0, v24, 0
+; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: vmerge.vim v24, v16, 1, v0
; RV32-NEXT: addi a1, sp, 256
-; RV32-NEXT: vse8.v v16, (a1)
-; RV32-NEXT: vmv1r.v v0, v25
-; RV32-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-NEXT: vse8.v v24, (a1)
+; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vmerge.vim v8, v16, 1, v0
; RV32-NEXT: addi a1, sp, 128
; RV32-NEXT: vse8.v v8, (a1)
; RV32-NEXT: lb a0, 0(a0)
@@ -192,18 +192,18 @@ define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind {
; RV64-NEXT: addi a2, a0, 128
; RV64-NEXT: addi a3, zero, 128
; RV64-NEXT: vsetvli zero, a3, e8, m8, ta, mu
-; RV64-NEXT: vle8.v v8, (a0)
-; RV64-NEXT: vle8.v v16, (a2)
+; RV64-NEXT: vle8.v v16, (a0)
+; RV64-NEXT: vle8.v v24, (a2)
; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: add a0, a0, a1
-; RV64-NEXT: vmseq.vi v25, v8, 0
-; RV64-NEXT: vmseq.vi v0, v16, 0
-; RV64-NEXT: vmv.v.i v8, 0
-; RV64-NEXT: vmerge.vim v16, v8, 1, v0
+; RV64-NEXT: vmseq.vi v8, v16, 0
+; RV64-NEXT: vmseq.vi v0, v24, 0
+; RV64-NEXT: vmv.v.i v16, 0
+; RV64-NEXT: vmerge.vim v24, v16, 1, v0
; RV64-NEXT: addi a1, sp, 256
-; RV64-NEXT: vse8.v v16, (a1)
-; RV64-NEXT: vmv1r.v v0, v25
-; RV64-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-NEXT: vse8.v v24, (a1)
+; RV64-NEXT: vmv1r.v v0, v8
+; RV64-NEXT: vmerge.vim v8, v16, 1, v0
; RV64-NEXT: addi a1, sp, 128
; RV64-NEXT: vse8.v v8, (a1)
; RV64-NEXT: lb a0, 0(a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
index 9b0741afe2edb..690da3979a002 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
@@ -6,9 +6,9 @@ define void @extract_v2i8_v4i8_0(<4 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0)
@@ -20,11 +20,11 @@ define void @extract_v2i8_v4i8_2(<4 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v4i8_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 2
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2)
@@ -36,9 +36,9 @@ define void @extract_v2i8_v8i8_0(<8 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0)
@@ -50,11 +50,11 @@ define void @extract_v2i8_v8i8_6(<8 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_v8i8_6:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 6
+; CHECK-NEXT: vslidedown.vi v8, v8, 6
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6)
@@ -66,17 +66,17 @@ define void @extract_v2i32_v8i32_0(<8 x i32>* %x, <2 x i32>* %y) {
; LMULMAX2-LABEL: extract_v2i32_v8i32_0:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX2-NEXT: vse32.v v26, (a1)
+; LMULMAX2-NEXT: vse32.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i32_v8i32_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vse32.v v25, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0)
@@ -88,21 +88,21 @@ define void @extract_v2i32_v8i32_2(<8 x i32>* %x, <2 x i32>* %y) {
; LMULMAX2-LABEL: extract_v2i32_v8i32_2:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX2-NEXT: vse32.v v26, (a1)
+; LMULMAX2-NEXT: vse32.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i32_v8i32_2:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vse32.v v25, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2)
@@ -114,22 +114,22 @@ define void @extract_v2i32_v8i32_6(<8 x i32>* %x, <2 x i32>* %y) {
; LMULMAX2-LABEL: extract_v2i32_v8i32_6:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v26, v26, 6
+; LMULMAX2-NEXT: vslidedown.vi v8, v8, 6
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX2-NEXT: vse32.v v26, (a1)
+; LMULMAX2-NEXT: vse32.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i32_v8i32_6:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vse32.v v25, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6)
@@ -176,9 +176,9 @@ define void @extract_v2i8_nxv2i8_2(<vscale x 2 x i8> %x, <2 x i8>* %y) {
; CHECK-LABEL: extract_v2i8_nxv2i8_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v8, 2
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 2)
store <2 x i8> %c, <2 x i8>* %y
@@ -214,17 +214,17 @@ define void @extract_v8i1_v64i1_0(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vlm.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v8i1_v64i1_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vlm.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vsm.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
@@ -237,21 +237,21 @@ define void @extract_v8i1_v64i1_8(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vlm.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v25, v25, 1
+; LMULMAX2-NEXT: vslidedown.vi v8, v8, 1
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v8i1_v64i1_8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vlm.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 1
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 1
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vsm.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
@@ -265,20 +265,20 @@ define void @extract_v8i1_v64i1_48(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2-NEXT: addi a0, a0, 4
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vlm.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v25, v25, 2
+; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v8i1_v64i1_48:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 6
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vlm.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vsm.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
@@ -312,9 +312,9 @@ define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv64i1_8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v0, 1
+; CHECK-NEXT: vslidedown.vi v8, v0, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8)
store <8 x i1> %c, <8 x i1>* %y
@@ -325,9 +325,9 @@ define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv64i1_48:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v0, 6
+; CHECK-NEXT: vslidedown.vi v8, v0, 6
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48)
store <8 x i1> %c, <8 x i1>* %y
@@ -342,15 +342,15 @@ define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vlm.v v0, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v25, 0
-; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
+; LMULMAX2-NEXT: vmv.v.i v9, 0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
+; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i1_v64i1_0:
@@ -358,15 +358,15 @@ define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT: vsm.v v25, (a1)
+; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
+; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
@@ -380,42 +380,42 @@ define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vlm.v v0, (a0)
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v26, v26, 2
+; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX2-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX2-NEXT: vmv.v.i v25, 0
-; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX2-NEXT: vmsne.vi v0, v8, 0
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
+; LMULMAX2-NEXT: vmv.v.i v9, 0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
+; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i1_v64i1_2:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v0, (a0)
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT: vsm.v v25, (a1)
+; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
+; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
@@ -430,21 +430,21 @@ define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vlm.v v0, (a0)
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v26, v26, 10
+; LMULMAX2-NEXT: vslidedown.vi v8, v8, 10
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX2-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX2-NEXT: vmv.v.i v25, 0
-; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX2-NEXT: vmsne.vi v0, v8, 0
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
+; LMULMAX2-NEXT: vmv.v.i v9, 0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
+; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i1_v64i1_42:
@@ -452,21 +452,21 @@ define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX1-NEXT: addi a0, a0, 4
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v0, (a0)
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 10
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 10
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
+; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT: vsm.v v25, (a1)
+; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
+; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
@@ -478,15 +478,15 @@ define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y
@@ -497,21 +497,21 @@ define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 2
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y
@@ -522,15 +522,15 @@ define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y
@@ -547,15 +547,15 @@ define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y
@@ -573,15 +573,15 @@ define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
store <2 x i1> %c, <2 x i1>* %y
@@ -592,21 +592,21 @@ define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv32i1_26:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v28, v28, 26
+; CHECK-NEXT: vslidedown.vi v8, v8, 26
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v28, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
store <2 x i1> %c, <2 x i1>* %y
@@ -617,9 +617,9 @@ define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv32i1_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v0, 2
+; CHECK-NEXT: vslidedown.vi v8, v0, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16)
store <8 x i1> %c, <8 x i1>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
index 2b2b63668f9ff..37e1f229e2036 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
@@ -6,10 +6,10 @@ define i8 @extractelt_v16i8(<16 x i8>* %x) nounwind {
; CHECK-LABEL: extractelt_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 7
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = extractelement <16 x i8> %a, i32 7
@@ -20,10 +20,10 @@ define i16 @extractelt_v8i16(<8 x i16>* %x) nounwind {
; CHECK-LABEL: extractelt_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 7
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = extractelement <8 x i16> %a, i32 7
@@ -34,10 +34,10 @@ define i32 @extractelt_v4i32(<4 x i32>* %x) nounwind {
; CHECK-LABEL: extractelt_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 2
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = extractelement <4 x i32> %a, i32 2
@@ -48,19 +48,19 @@ define i64 @extractelt_v2i64(<2 x i64>* %x) nounwind {
; RV32-LABEL: extractelt_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: extractelt_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = extractelement <2 x i64> %a, i32 0
@@ -71,10 +71,10 @@ define half @extractelt_v8f16(<8 x half>* %x) nounwind {
; CHECK-LABEL: extractelt_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 7
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = extractelement <8 x half> %a, i32 7
@@ -85,10 +85,10 @@ define float @extractelt_v4f32(<4 x float>* %x) nounwind {
; CHECK-LABEL: extractelt_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 2
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = extractelement <4 x float> %a, i32 2
@@ -99,8 +99,8 @@ define double @extractelt_v2f64(<2 x double>* %x) nounwind {
; CHECK-LABEL: extractelt_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = extractelement <2 x double> %a, i32 0
@@ -112,10 +112,10 @@ define i8 @extractelt_v32i8(<32 x i8>* %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v26, 7
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = extractelement <32 x i8> %a, i32 7
@@ -126,10 +126,10 @@ define i16 @extractelt_v16i16(<16 x i16>* %x) nounwind {
; CHECK-LABEL: extractelt_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v26, 7
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = extractelement <16 x i16> %a, i32 7
@@ -140,10 +140,10 @@ define i32 @extractelt_v8i32(<8 x i32>* %x) nounwind {
; CHECK-LABEL: extractelt_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v26, 6
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 6
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = extractelement <8 x i32> %a, i32 6
@@ -154,22 +154,22 @@ define i64 @extractelt_v4i64(<4 x i64>* %x) nounwind {
; RV32-LABEL: extractelt_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; RV32-NEXT: vslidedown.vi v26, v26, 3
-; RV32-NEXT: vmv.x.s a0, v26
+; RV32-NEXT: vslidedown.vi v8, v8, 3
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
-; RV32-NEXT: vsrl.vx v26, v26, a1
-; RV32-NEXT: vmv.x.s a1, v26
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: extractelt_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; RV64-NEXT: vslidedown.vi v26, v26, 3
-; RV64-NEXT: vmv.x.s a0, v26
+; RV64-NEXT: vslidedown.vi v8, v8, 3
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = extractelement <4 x i64> %a, i32 3
@@ -180,10 +180,10 @@ define half @extractelt_v16f16(<16 x half>* %x) nounwind {
; CHECK-LABEL: extractelt_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v26, 7
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = extractelement <16 x half> %a, i32 7
@@ -194,10 +194,10 @@ define float @extractelt_v8f32(<8 x float>* %x) nounwind {
; CHECK-LABEL: extractelt_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v26, v26, 2
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = extractelement <8 x float> %a, i32 2
@@ -208,8 +208,8 @@ define double @extractelt_v4f64(<4 x double>* %x) nounwind {
; CHECK-LABEL: extractelt_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = extractelement <4 x double> %a, i32 0
@@ -224,21 +224,21 @@ define i64 @extractelt_v3i64(<3 x i64>* %x) nounwind {
; RV32-LABEL: extractelt_v3i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vle32.v v26, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; RV32-NEXT: vslidedown.vi v28, v26, 4
-; RV32-NEXT: vmv.x.s a0, v28
-; RV32-NEXT: vslidedown.vi v26, v26, 5
-; RV32-NEXT: vmv.x.s a1, v26
+; RV32-NEXT: vslidedown.vi v10, v8, 4
+; RV32-NEXT: vmv.x.s a0, v10
+; RV32-NEXT: vslidedown.vi v8, v8, 5
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: extractelt_v3i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; RV64-NEXT: vslidedown.vi v26, v26, 2
-; RV64-NEXT: vmv.x.s a0, v26
+; RV64-NEXT: vslidedown.vi v8, v8, 2
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%a = load <3 x i64>, <3 x i64>* %x
%b = extractelement <3 x i64> %a, i32 2
@@ -249,10 +249,10 @@ define i8 @extractelt_v16i8_idx(<16 x i8>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v16i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = extractelement <16 x i8> %a, i32 %idx
@@ -263,10 +263,10 @@ define i16 @extractelt_v8i16_idx(<8 x i16>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v8i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = extractelement <8 x i16> %a, i32 %idx
@@ -277,11 +277,11 @@ define i32 @extractelt_v4i32_idx(<4 x i32>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v4i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vadd.vv v25, v25, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = add <4 x i32> %a, %a
@@ -293,24 +293,24 @@ define i64 @extractelt_v2i64_idx(<2 x i64>* %x, i32 signext %idx) nounwind {
; RV32-LABEL: extractelt_v2i64_idx:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
-; RV32-NEXT: vadd.vv v25, v25, v25
+; RV32-NEXT: vle64.v v8, (a0)
+; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vslidedown.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vslidedown.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: extractelt_v2i64_idx:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vadd.vv v25, v25, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vslidedown.vx v25, v25, a1
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vslidedown.vx v8, v8, a1
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = add <2 x i64> %a, %a
@@ -322,11 +322,11 @@ define half @extractelt_v8f16_idx(<8 x half>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v8f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfadd.vv v25, v25, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = fadd <8 x half> %a, %a
@@ -338,11 +338,11 @@ define float @extractelt_v4f32_idx(<4 x float>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v4f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfadd.vv v25, v25, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = fadd <4 x float> %a, %a
@@ -354,11 +354,11 @@ define double @extractelt_v2f64_idx(<2 x double>* %x, i32 signext %idx) nounwind
; CHECK-LABEL: extractelt_v2f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfadd.vv v25, v25, v25
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vslidedown.vx v25, v25, a1
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = fadd <2 x double> %a, %a
@@ -371,10 +371,10 @@ define i8 @extractelt_v32i8_idx(<32 x i8>* %x, i32 signext %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = extractelement <32 x i8> %a, i32 %idx
@@ -385,10 +385,10 @@ define i16 @extractelt_v16i16_idx(<16 x i16>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v16i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = extractelement <16 x i16> %a, i32 %idx
@@ -399,11 +399,11 @@ define i32 @extractelt_v8i32_idx(<8 x i32>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v8i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vadd.vv v26, v26, v26
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vmv.x.s a0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = add <8 x i32> %a, %a
@@ -415,24 +415,24 @@ define i64 @extractelt_v4i64_idx(<4 x i64>* %x, i32 signext %idx) nounwind {
; RV32-LABEL: extractelt_v4i64_idx:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vle64.v v8, (a0)
+; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; RV32-NEXT: vslidedown.vx v26, v26, a1
-; RV32-NEXT: vmv.x.s a0, v26
+; RV32-NEXT: vslidedown.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
-; RV32-NEXT: vsrl.vx v26, v26, a1
-; RV32-NEXT: vmv.x.s a1, v26
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: extractelt_v4i64_idx:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
-; RV64-NEXT: vadd.vv v26, v26, v26
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; RV64-NEXT: vslidedown.vx v26, v26, a1
-; RV64-NEXT: vmv.x.s a0, v26
+; RV64-NEXT: vslidedown.vx v8, v8, a1
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = add <4 x i64> %a, %a
@@ -444,11 +444,11 @@ define half @extractelt_v16f16_idx(<16 x half>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v16f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vfadd.vv v26, v26, v26
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = fadd <16 x half> %a, %a
@@ -460,11 +460,11 @@ define float @extractelt_v8f32_idx(<8 x float>* %x, i32 signext %idx) nounwind {
; CHECK-LABEL: extractelt_v8f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vfadd.vv v26, v26, v26
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = fadd <8 x float> %a, %a
@@ -476,11 +476,11 @@ define double @extractelt_v4f64_idx(<4 x double>* %x, i32 signext %idx) nounwind
; CHECK-LABEL: extractelt_v4f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vfadd.vv v26, v26, v26
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vslidedown.vx v26, v26, a1
-; CHECK-NEXT: vfmv.f.s fa0, v26
+; CHECK-NEXT: vslidedown.vx v8, v8, a1
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = fadd <4 x double> %a, %a
@@ -496,25 +496,25 @@ define i64 @extractelt_v3i64_idx(<3 x i64>* %x, i32 signext %idx) nounwind {
; RV32-LABEL: extractelt_v3i64_idx:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vle64.v v8, (a0)
+; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: add a1, a1, a1
; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; RV32-NEXT: vslidedown.vx v28, v26, a1
-; RV32-NEXT: vmv.x.s a0, v28
+; RV32-NEXT: vslidedown.vx v10, v8, a1
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, a1, 1
-; RV32-NEXT: vslidedown.vx v26, v26, a1
-; RV32-NEXT: vmv.x.s a1, v26
+; RV32-NEXT: vslidedown.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: extractelt_v3i64_idx:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
-; RV64-NEXT: vadd.vv v26, v26, v26
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; RV64-NEXT: vslidedown.vx v26, v26, a1
-; RV64-NEXT: vmv.x.s a0, v26
+; RV64-NEXT: vslidedown.vx v8, v8, a1
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%a = load <3 x i64>, <3 x i64>* %x
%b = add <3 x i64> %a, %a
@@ -526,10 +526,10 @@ define void @store_extractelt_v16i8(<16 x i8>* %x, i8* %p) nounwind {
; CHECK-LABEL: store_extractelt_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 7
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = extractelement <16 x i8> %a, i32 7
@@ -541,10 +541,10 @@ define void @store_extractelt_v8i16(<8 x i16>* %x, i16* %p) nounwind {
; CHECK-LABEL: store_extractelt_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 7
-; CHECK-NEXT: vse16.v v25, (a1)
+; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = extractelement <8 x i16> %a, i32 7
@@ -556,10 +556,10 @@ define void @store_extractelt_v4i32(<4 x i32>* %x, i32* %p) nounwind {
; CHECK-LABEL: store_extractelt_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
-; CHECK-NEXT: vslidedown.vi v25, v25, 2
-; CHECK-NEXT: vse32.v v25, (a1)
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = extractelement <4 x i32> %a, i32 2
@@ -572,13 +572,13 @@ define void @store_extractelt_v4i64(<2 x i64>* %x, i64* %p) nounwind {
; RV32-LABEL: store_extractelt_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v25, 1
+; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a0, v26
-; RV32-NEXT: vmv.x.s a2, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a0, v9
+; RV32-NEXT: vmv.x.s a2, v8
; RV32-NEXT: sw a2, 0(a1)
; RV32-NEXT: sw a0, 4(a1)
; RV32-NEXT: ret
@@ -586,10 +586,10 @@ define void @store_extractelt_v4i64(<2 x i64>* %x, i64* %p) nounwind {
; RV64-LABEL: store_extractelt_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v25, 1
-; RV64-NEXT: vse64.v v25, (a1)
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = extractelement <2 x i64> %a, i64 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
index b3680a70c3dce..d1525447c40d7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
@@ -82,8 +82,8 @@ define i64 @bitcast_v4f16_i64(<4 x half> %a) {
; RV32-FP: # %bb.0:
; RV32-FP-NEXT: addi a0, zero, 32
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-FP-NEXT: vsrl.vx v25, v8, a0
-; RV32-FP-NEXT: vmv.x.s a1, v25
+; RV32-FP-NEXT: vsrl.vx v9, v8, a0
+; RV32-FP-NEXT: vmv.x.s a1, v9
; RV32-FP-NEXT: vmv.x.s a0, v8
; RV32-FP-NEXT: ret
;
@@ -101,8 +101,8 @@ define i64 @bitcast_v2f32_i64(<2 x float> %a) {
; RV32-FP: # %bb.0:
; RV32-FP-NEXT: addi a0, zero, 32
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-FP-NEXT: vsrl.vx v25, v8, a0
-; RV32-FP-NEXT: vmv.x.s a1, v25
+; RV32-FP-NEXT: vsrl.vx v9, v8, a0
+; RV32-FP-NEXT: vmv.x.s a1, v9
; RV32-FP-NEXT: vmv.x.s a0, v8
; RV32-FP-NEXT: ret
;
@@ -120,8 +120,8 @@ define i64 @bitcast_v1f64_i64(<1 x double> %a) {
; RV32-FP: # %bb.0:
; RV32-FP-NEXT: addi a0, zero, 32
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-FP-NEXT: vsrl.vx v25, v8, a0
-; RV32-FP-NEXT: vmv.x.s a1, v25
+; RV32-FP-NEXT: vsrl.vx v9, v8, a0
+; RV32-FP-NEXT: vmv.x.s a1, v9
; RV32-FP-NEXT: vmv.x.s a0, v8
; RV32-FP-NEXT: ret
;
@@ -246,11 +246,11 @@ define <4 x half> @bitcast_i64_v4f16(i64 %a) {
; RV32-FP-LABEL: bitcast_i64_v4f16:
; RV32-FP: # %bb.0:
; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-FP-NEXT: vmv.v.i v25, 0
-; RV32-FP-NEXT: vslide1up.vx v26, v25, a1
-; RV32-FP-NEXT: vslide1up.vx v25, v26, a0
+; RV32-FP-NEXT: vmv.v.i v8, 0
+; RV32-FP-NEXT: vslide1up.vx v9, v8, a1
+; RV32-FP-NEXT: vslide1up.vx v10, v9, a0
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-FP-NEXT: vslideup.vi v8, v25, 0
+; RV32-FP-NEXT: vslideup.vi v8, v10, 0
; RV32-FP-NEXT: ret
;
; RV64-FP-LABEL: bitcast_i64_v4f16:
@@ -266,11 +266,11 @@ define <2 x float> @bitcast_i64_v2f32(i64 %a) {
; RV32-FP-LABEL: bitcast_i64_v2f32:
; RV32-FP: # %bb.0:
; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-FP-NEXT: vmv.v.i v25, 0
-; RV32-FP-NEXT: vslide1up.vx v26, v25, a1
-; RV32-FP-NEXT: vslide1up.vx v25, v26, a0
+; RV32-FP-NEXT: vmv.v.i v8, 0
+; RV32-FP-NEXT: vslide1up.vx v9, v8, a1
+; RV32-FP-NEXT: vslide1up.vx v10, v9, a0
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-FP-NEXT: vslideup.vi v8, v25, 0
+; RV32-FP-NEXT: vslideup.vi v8, v10, 0
; RV32-FP-NEXT: ret
;
; RV64-FP-LABEL: bitcast_i64_v2f32:
@@ -286,11 +286,11 @@ define <1 x double> @bitcast_i64_v1f64(i64 %a) {
; RV32-FP-LABEL: bitcast_i64_v1f64:
; RV32-FP: # %bb.0:
; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-FP-NEXT: vmv.v.i v25, 0
-; RV32-FP-NEXT: vslide1up.vx v26, v25, a1
-; RV32-FP-NEXT: vslide1up.vx v25, v26, a0
+; RV32-FP-NEXT: vmv.v.i v8, 0
+; RV32-FP-NEXT: vslide1up.vx v9, v8, a1
+; RV32-FP-NEXT: vslide1up.vx v10, v9, a0
; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-FP-NEXT: vslideup.vi v8, v25, 0
+; RV32-FP-NEXT: vslideup.vi v8, v10, 0
; RV32-FP-NEXT: ret
;
; RV64-FP-LABEL: bitcast_i64_v1f64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index 3941ed6a4d4d3..eba7f00807f62 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -13,8 +13,8 @@ define void @buildvec_no_vid_v4f32(<4 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI0_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI0_0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
store <4 x float> <float 0.0, float 4.0, float 0.0, float 2.0>, <4 x float>* %x
ret void
@@ -43,11 +43,11 @@ define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x,
; LMULMAX1-NEXT: vfmv.f.s ft0, v8
; LMULMAX1-NEXT: fsw ft0, 16(sp)
; LMULMAX1-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v10, 7
-; LMULMAX1-NEXT: vfmv.f.s ft0, v26
+; LMULMAX1-NEXT: vslidedown.vi v10, v10, 7
+; LMULMAX1-NEXT: vfmv.f.s ft0, v10
; LMULMAX1-NEXT: fsw ft0, 28(sp)
-; LMULMAX1-NEXT: vslidedown.vi v26, v8, 7
-; LMULMAX1-NEXT: vfmv.f.s ft0, v26
+; LMULMAX1-NEXT: vslidedown.vi v8, v8, 7
+; LMULMAX1-NEXT: vfmv.f.s ft0, v8
; LMULMAX1-NEXT: fsw ft0, 20(sp)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a0, sp, 16
@@ -61,19 +61,19 @@ define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x,
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.s.x v0, a0
; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-NEXT: vrgather.vi v25, v8, 0
-; LMULMAX2-NEXT: vrgather.vi v25, v9, 3, v0.t
+; LMULMAX2-NEXT: vrgather.vi v12, v8, 0
+; LMULMAX2-NEXT: vrgather.vi v12, v9, 3, v0.t
; LMULMAX2-NEXT: addi a0, zero, 8
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.s.x v0, a0
; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-NEXT: vrgather.vi v26, v10, 0
-; LMULMAX2-NEXT: vrgather.vi v26, v11, 3, v0.t
+; LMULMAX2-NEXT: vrgather.vi v8, v10, 0
+; LMULMAX2-NEXT: vrgather.vi v8, v11, 3, v0.t
; LMULMAX2-NEXT: addi a0, zero, 3
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.s.x v0, a0
; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX2-NEXT: vmerge.vvm v8, v26, v25, v0
+; LMULMAX2-NEXT: vmerge.vvm v8, v8, v12, v0
; LMULMAX2-NEXT: ret
%z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15>
ret <4 x float> %z
@@ -85,11 +85,11 @@ define void @buildvec_dominant0_v2f32(<2 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI2_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI2_0)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vlse32.v v25, (a1), zero
+; CHECK-NEXT: vlse32.v v8, (a1), zero
; CHECK-NEXT: fmv.w.x ft0, zero
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vfmv.s.f v25, ft0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
store <2 x float> <float 0.0, float 1.0>, <2 x float>* %x
ret void
@@ -104,8 +104,8 @@ define void @buildvec_dominant1_v2f32(<2 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI3_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_0)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
store <2 x float> <float 1.0, float 2.0>, <2 x float>* %x
ret void
@@ -117,13 +117,13 @@ define void @buildvec_dominant0_v4f32(<4 x float>* %x) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: lui a1, %hi(.LCPI4_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI4_0)
-; CHECK-NEXT: vlse32.v v25, (a1), zero
+; CHECK-NEXT: vlse32.v v8, (a1), zero
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vfmv.s.f v26, ft0
+; CHECK-NEXT: vfmv.s.f v9, ft0
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v25, v26, 2
+; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, <4 x float>* %x
ret void
@@ -134,12 +134,12 @@ define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) {
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, ft0
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 1
+; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%v0 = insertelement <4 x float> undef, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 0.0, i32 1
@@ -155,12 +155,12 @@ define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) {
; CHECK-NEXT: lui a1, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, ft0
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v8, ft0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 1
+; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%v0 = insertelement <4 x float> undef, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 2.0, i32 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
index 9324a403db0e4..f858b69f008ad 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
@@ -8,9 +8,9 @@ define void @fpext_v2f16_v2f32(<2 x half>* %x, <2 x float>* %y) {
; CHECK-LABEL: fpext_v2f16_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
-; CHECK-NEXT: vse32.v v26, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vse32.v v9, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%d = fpext <2 x half> %a to <2 x float>
@@ -22,11 +22,11 @@ define void @fpext_v2f16_v2f64(<2 x half>* %x, <2 x double>* %y) {
; CHECK-LABEL: fpext_v2f16_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v26
-; CHECK-NEXT: vse64.v v25, (a1)
+; CHECK-NEXT: vfwcvt.f.f.v v8, v9
+; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%d = fpext <2 x half> %a to <2 x double>
@@ -38,23 +38,23 @@ define void @fpext_v8f16_v8f32(<8 x half>* %x, <8 x float>* %y) {
; LMULMAX8-LABEL: fpext_v8f16_v8f32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX8-NEXT: vle16.v v25, (a0)
-; LMULMAX8-NEXT: vfwcvt.f.f.v v26, v25
-; LMULMAX8-NEXT: vse32.v v26, (a1)
+; LMULMAX8-NEXT: vle16.v v8, (a0)
+; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8
+; LMULMAX8-NEXT: vse32.v v10, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fpext_v8f16_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v9, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v27, v26
-; LMULMAX1-NEXT: vfwcvt.f.f.v v26, v25
+; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9
+; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v8
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse32.v v27, (a0)
-; LMULMAX1-NEXT: vse32.v v26, (a1)
+; LMULMAX1-NEXT: vse32.v v10, (a0)
+; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%d = fpext <8 x half> %a to <8 x float>
@@ -66,46 +66,46 @@ define void @fpext_v8f16_v8f64(<8 x half>* %x, <8 x double>* %y) {
; LMULMAX8-LABEL: fpext_v8f16_v8f64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX8-NEXT: vle16.v v25, (a0)
-; LMULMAX8-NEXT: vfwcvt.f.f.v v26, v25
+; LMULMAX8-NEXT: vle16.v v8, (a0)
+; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfwcvt.f.f.v v28, v26
-; LMULMAX8-NEXT: vse64.v v28, (a1)
+; LMULMAX8-NEXT: vfwcvt.f.f.v v12, v10
+; LMULMAX8-NEXT: vse64.v v12, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fpext_v8f16_v8f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v27, v26
+; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v26, v27
+; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v29, v28
+; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v28, v29
+; LMULMAX1-NEXT: vfwcvt.f.f.v v11, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v29, v27
+; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v27, v29
+; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v29, v25
+; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.f.f.v v25, v29
+; LMULMAX1-NEXT: vfwcvt.f.f.v v8, v12
; LMULMAX1-NEXT: addi a0, a1, 32
-; LMULMAX1-NEXT: vse64.v v27, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
+; LMULMAX1-NEXT: vse64.v v10, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
-; LMULMAX1-NEXT: vse64.v v28, (a0)
+; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse64.v v26, (a0)
+; LMULMAX1-NEXT: vse64.v v9, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%d = fpext <8 x half> %a to <8 x double>
@@ -117,10 +117,10 @@ define void @fpround_v2f32_v2f16(<2 x float>* %x, <2 x half>* %y) {
; CHECK-LABEL: fpround_v2f32_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vse16.v v26, (a1)
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vse16.v v9, (a1)
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%d = fptrunc <2 x float> %a to <2 x half>
@@ -132,12 +132,12 @@ define void @fpround_v2f64_v2f16(<2 x double>* %x, <2 x half>* %y) {
; CHECK-LABEL: fpround_v2f64_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v26
-; CHECK-NEXT: vse16.v v25, (a1)
+; CHECK-NEXT: vfncvt.f.f.w v8, v9
+; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%d = fptrunc <2 x double> %a to <2 x half>
@@ -149,29 +149,29 @@ define void @fpround_v8f32_v8f16(<8 x float>* %x, <8 x half>* %y) {
; LMULMAX8-LABEL: fpround_v8f32_v8f16:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
-; LMULMAX8-NEXT: vse16.v v25, (a1)
+; LMULMAX8-NEXT: vfncvt.f.f.w v10, v8
+; LMULMAX8-NEXT: vse16.v v10, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fpround_v8f32_v8f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v27, v25
+; LMULMAX1-NEXT: vfncvt.f.f.w v10, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v27, v26
+; LMULMAX1-NEXT: vfncvt.f.f.w v10, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v27, 4
-; LMULMAX1-NEXT: vse16.v v25, (a1)
+; LMULMAX1-NEXT: vslideup.vi v8, v10, 4
+; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%d = fptrunc <8 x float> %a to <8 x half>
@@ -183,51 +183,51 @@ define void @fpround_v8f64_v8f16(<8 x double>* %x, <8 x half>* %y) {
; LMULMAX8-LABEL: fpround_v8f64_v8f16:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX8-NEXT: vle64.v v28, (a0)
+; LMULMAX8-NEXT: vle64.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfncvt.rod.f.f.w v26, v28
+; LMULMAX8-NEXT: vfncvt.rod.f.f.w v12, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
-; LMULMAX8-NEXT: vse16.v v25, (a1)
+; LMULMAX8-NEXT: vfncvt.f.f.w v8, v12
+; LMULMAX8-NEXT: vse16.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fpround_v8f64_v8f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vle64.v v25, (a2)
+; LMULMAX1-NEXT: vle64.v v8, (a2)
; LMULMAX1-NEXT: addi a2, a0, 32
-; LMULMAX1-NEXT: vle64.v v26, (a2)
-; LMULMAX1-NEXT: vle64.v v27, (a0)
+; LMULMAX1-NEXT: vle64.v v9, (a2)
+; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle64.v v28, (a0)
+; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rod.f.f.w v29, v27
+; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29
+; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v29, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v28
+; LMULMAX1-NEXT: vfncvt.rod.f.f.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27
+; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v26
+; LMULMAX1-NEXT: vfncvt.rod.f.f.w v10, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27
+; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rod.f.f.w v26, v25
+; LMULMAX1-NEXT: vfncvt.rod.f.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26
+; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
-; LMULMAX1-NEXT: vse16.v v29, (a1)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 6
+; LMULMAX1-NEXT: vse16.v v12, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%d = fptrunc <8 x double> %a to <8 x half>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
index 60508396aec1e..9999efbe33808 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
@@ -6,10 +6,10 @@ define void @fcmp_oeq_vv_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oeq_vv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmfeq.vv v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -22,10 +22,10 @@ define void @fcmp_oeq_vv_v8f16_nonans(<8 x half>* %x, <8 x half>* %y, <8 x i1>*
; CHECK-LABEL: fcmp_oeq_vv_v8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmfeq.vv v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -38,19 +38,19 @@ define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmfne.vv v0, v25, v26
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -63,19 +63,19 @@ define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>
; CHECK-LABEL: fcmp_une_vv_v4f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmfne.vv v0, v25, v26
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -88,19 +88,19 @@ define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z)
; CHECK-LABEL: fcmp_ogt_vv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmflt.vv v0, v26, v25
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -113,19 +113,19 @@ define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i
; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmflt.vv v0, v26, v25
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -138,10 +138,10 @@ define void @fcmp_olt_vv_v16f16(<16 x half>* %x, <16 x half>* %y, <16 x i1>* %z)
; CHECK-LABEL: fcmp_olt_vv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vmflt.vv v25, v26, v28
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -154,10 +154,10 @@ define void @fcmp_olt_vv_v16f16_nonans(<16 x half>* %x, <16 x half>* %y, <16 x i
; CHECK-LABEL: fcmp_olt_vv_v16f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vmflt.vv v25, v26, v28
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -170,10 +170,10 @@ define void @fcmp_oge_vv_v8f32(<8 x float>* %x, <8 x float>* %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oge_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vmfle.vv v25, v28, v26
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vmfle.vv v12, v10, v8
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -186,10 +186,10 @@ define void @fcmp_oge_vv_v8f32_nonans(<8 x float>* %x, <8 x float>* %y, <8 x i1>
; CHECK-LABEL: fcmp_oge_vv_v8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vmfle.vv v25, v28, v26
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vmfle.vv v12, v10, v8
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -202,19 +202,19 @@ define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z)
; CHECK-LABEL: fcmp_ole_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vle64.v v28, (a1)
-; CHECK-NEXT: vmfle.vv v0, v26, v28
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v10, (a1)
+; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -227,19 +227,19 @@ define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i
; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vle64.v v28, (a1)
-; CHECK-NEXT: vmfle.vv v0, v26, v28
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v10, (a1)
+; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -253,11 +253,11 @@ define void @fcmp_ule_vv_v32f16(<32 x half>* %x, <32 x half>* %y, <32 x i1>* %z)
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: vmflt.vv v25, v8, v28
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v12, (a1)
+; CHECK-NEXT: vmflt.vv v16, v12, v8
+; CHECK-NEXT: vmnand.mm v8, v16, v16
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = load <32 x half>, <32 x half>* %y
@@ -271,10 +271,10 @@ define void @fcmp_ule_vv_v32f16_nonans(<32 x half>* %x, <32 x half>* %y, <32 x i
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: vmfle.vv v25, v28, v8
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v12, (a1)
+; CHECK-NEXT: vmfle.vv v16, v8, v12
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = load <32 x half>, <32 x half>* %y
@@ -287,11 +287,11 @@ define void @fcmp_uge_vv_v16f32(<16 x float>* %x, <16 x float>* %y, <16 x i1>* %
; CHECK-LABEL: fcmp_uge_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vmflt.vv v25, v28, v8
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v12, (a1)
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vmnand.mm v8, v16, v16
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = load <16 x float>, <16 x float>* %y
@@ -304,10 +304,10 @@ define void @fcmp_uge_vv_v16f32_nonans(<16 x float>* %x, <16 x float>* %y, <16 x
; CHECK-LABEL: fcmp_uge_vv_v16f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vmfle.vv v25, v8, v28
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v12, (a1)
+; CHECK-NEXT: vmfle.vv v16, v12, v8
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = load <16 x float>, <16 x float>* %y
@@ -320,11 +320,11 @@ define void @fcmp_ult_vv_v8f64(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z)
; CHECK-LABEL: fcmp_ult_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
-; CHECK-NEXT: vle64.v v8, (a1)
-; CHECK-NEXT: vmfle.vv v25, v8, v28
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v12, (a1)
+; CHECK-NEXT: vmfle.vv v16, v12, v8
+; CHECK-NEXT: vmnand.mm v8, v16, v16
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = load <8 x double>, <8 x double>* %y
@@ -337,10 +337,10 @@ define void @fcmp_ult_vv_v8f64_nonans(<8 x double>* %x, <8 x double>* %y, <8 x i
; CHECK-LABEL: fcmp_ult_vv_v8f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
-; CHECK-NEXT: vle64.v v8, (a1)
-; CHECK-NEXT: vmflt.vv v25, v28, v8
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v12, (a1)
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = load <8 x double>, <8 x double>* %y
@@ -356,9 +356,9 @@ define void @fcmp_ugt_vv_v64f16(<64 x half>* %x, <64 x half>* %y, <64 x i1>* %z)
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vmfle.vv v25, v8, v16
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmfle.vv v24, v8, v16
+; CHECK-NEXT: vmnand.mm v8, v24, v24
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = load <64 x half>, <64 x half>* %y
@@ -374,8 +374,8 @@ define void @fcmp_ugt_vv_v64f16_nonans(<64 x half>* %x, <64 x half>* %y, <64 x i
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vmflt.vv v25, v16, v8
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmflt.vv v24, v16, v8
+; CHECK-NEXT: vsm.v v24, (a2)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = load <64 x half>, <64 x half>* %y
@@ -391,10 +391,10 @@ define void @fcmp_ueq_vv_v32f32(<32 x float>* %x, <32 x float>* %y, <32 x i1>* %
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmflt.vv v26, v16, v8
-; CHECK-NEXT: vmnor.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmflt.vv v25, v16, v8
+; CHECK-NEXT: vmnor.mm v8, v25, v24
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = load <32 x float>, <32 x float>* %y
@@ -410,8 +410,8 @@ define void @fcmp_ueq_vv_v32f32_nonans(<32 x float>* %x, <32 x float>* %y, <32 x
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vmfeq.vv v25, v8, v16
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmfeq.vv v24, v8, v16
+; CHECK-NEXT: vsm.v v24, (a2)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = load <32 x float>, <32 x float>* %y
@@ -426,10 +426,10 @@ define void @fcmp_one_vv_v8f64(<16 x double>* %x, <16 x double>* %y, <16 x i1>*
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v16, (a1)
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmflt.vv v26, v16, v8
-; CHECK-NEXT: vmor.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmflt.vv v25, v16, v8
+; CHECK-NEXT: vmor.mm v8, v25, v24
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = load <16 x double>, <16 x double>* %y
@@ -444,8 +444,8 @@ define void @fcmp_one_vv_v8f64_nonans(<16 x double>* %x, <16 x double>* %y, <16
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v16, (a1)
-; CHECK-NEXT: vmfne.vv v25, v8, v16
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmfne.vv v24, v8, v16
+; CHECK-NEXT: vsm.v v24, (a2)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = load <16 x double>, <16 x double>* %y
@@ -458,21 +458,21 @@ define void @fcmp_ord_vv_v4f16(<4 x half>* %x, <4 x half>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ord_vv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmfeq.vv v25, v25, v25
-; CHECK-NEXT: vmfeq.vv v26, v26, v26
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vmfeq.vv v8, v8, v8
+; CHECK-NEXT: vmfeq.vv v9, v9, v9
+; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x
%b = load <4 x half>, <4 x half>* %y
@@ -485,21 +485,21 @@ define void @fcmp_uno_vv_v4f16(<2 x half>* %x, <2 x half>* %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_uno_vv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmfne.vv v25, v25, v25
-; CHECK-NEXT: vmfne.vv v26, v26, v26
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vmfne.vv v8, v8, v8
+; CHECK-NEXT: vmfne.vv v9, v9, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%b = load <2 x half>, <2 x half>* %y
@@ -512,9 +512,9 @@ define void @fcmp_oeq_vf_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oeq_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfeq.vf v8, v8, fa0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -528,9 +528,9 @@ define void @fcmp_oeq_vf_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oeq_vf_v8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfeq.vf v8, v8, fa0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -544,18 +544,18 @@ define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmfne.vf v0, v25, fa0
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -569,18 +569,18 @@ define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmfne.vf v0, v25, fa0
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -594,18 +594,18 @@ define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vmfgt.vf v0, v25, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -619,18 +619,18 @@ define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z)
; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vmfgt.vf v0, v25, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -644,9 +644,9 @@ define void @fcmp_olt_vf_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) {
; CHECK-LABEL: fcmp_olt_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmflt.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -660,9 +660,9 @@ define void @fcmp_olt_vf_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z)
; CHECK-LABEL: fcmp_olt_vf_v16f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmflt.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -676,9 +676,9 @@ define void @fcmp_oge_vf_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oge_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmfge.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfge.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -692,9 +692,9 @@ define void @fcmp_oge_vf_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oge_vf_v8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmfge.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfge.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -708,18 +708,18 @@ define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vmfle.vf v0, v26, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -733,18 +733,18 @@ define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z)
; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vmfle.vf v0, v26, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -759,10 +759,10 @@ define void @fcmp_ule_vf_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v28, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v12, v12
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -777,9 +777,9 @@ define void @fcmp_ule_vf_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z)
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vmfle.vf v25, v28, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfle.vf v12, v8, fa0
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -793,10 +793,10 @@ define void @fcmp_uge_vf_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
; CHECK-LABEL: fcmp_uge_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vmflt.vf v25, v28, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v12, v12
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -810,9 +810,9 @@ define void @fcmp_uge_vf_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z
; CHECK-LABEL: fcmp_uge_vf_v16f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vmfge.vf v25, v28, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfge.vf v12, v8, fa0
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -826,10 +826,10 @@ define void @fcmp_ult_vf_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_ult_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
-; CHECK-NEXT: vmfge.vf v25, v28, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfge.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v12, v12
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -843,9 +843,9 @@ define void @fcmp_ult_vf_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z)
; CHECK-LABEL: fcmp_ult_vf_v8f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
-; CHECK-NEXT: vmflt.vf v25, v28, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -861,9 +861,9 @@ define void @fcmp_ugt_vf_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfle.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v16, v16
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -879,8 +879,8 @@ define void @fcmp_ugt_vf_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z)
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -896,10 +896,10 @@ define void @fcmp_ueq_vf_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) {
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmfgt.vf v17, v8, fa0
+; CHECK-NEXT: vmnor.mm v8, v17, v16
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -915,8 +915,8 @@ define void @fcmp_ueq_vf_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vmfeq.vf v25, v8, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfeq.vf v16, v8, fa0
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -931,10 +931,10 @@ define void @fcmp_one_vf_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmfgt.vf v17, v8, fa0
+; CHECK-NEXT: vmor.mm v8, v17, v16
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -949,8 +949,8 @@ define void @fcmp_one_vf_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* %
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vmfne.vf v25, v8, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfne.vf v16, v8, fa0
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -964,21 +964,21 @@ define void @fcmp_ord_vf_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ord_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v26, v26, fa0
-; CHECK-NEXT: vmfeq.vv v25, v25, v25
-; CHECK-NEXT: vmand.mm v0, v25, v26
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v8, v8, v8
+; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> undef, half %y, i32 0
@@ -992,21 +992,21 @@ define void @fcmp_uno_vf_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_uno_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v26, v26, fa0
-; CHECK-NEXT: vmfne.vv v25, v25, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vmfne.vf v9, v9, fa0
+; CHECK-NEXT: vmfne.vv v8, v8, v8
+; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> undef, half %y, i32 0
@@ -1020,9 +1020,9 @@ define void @fcmp_oeq_fv_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oeq_fv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfeq.vf v8, v8, fa0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1036,9 +1036,9 @@ define void @fcmp_oeq_fv_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oeq_fv_v8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfeq.vf v8, v8, fa0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1052,18 +1052,18 @@ define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmfne.vf v0, v25, fa0
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1077,18 +1077,18 @@ define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmfne.vf v0, v25, fa0
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1102,18 +1102,18 @@ define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vmflt.vf v0, v25, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1127,18 +1127,18 @@ define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z)
; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vmflt.vf v0, v25, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1152,9 +1152,9 @@ define void @fcmp_olt_fv_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) {
; CHECK-LABEL: fcmp_olt_fv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -1168,9 +1168,9 @@ define void @fcmp_olt_fv_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z)
; CHECK-LABEL: fcmp_olt_fv_v16f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -1184,9 +1184,9 @@ define void @fcmp_oge_fv_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oge_fv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmfle.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfle.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -1200,9 +1200,9 @@ define void @fcmp_oge_fv_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_oge_fv_v8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmfle.vf v25, v26, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfle.vf v10, v8, fa0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -1216,18 +1216,18 @@ define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vmfge.vf v0, v26, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -1241,18 +1241,18 @@ define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z)
; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vmfge.vf v0, v26, fa0
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -1267,10 +1267,10 @@ define void @fcmp_ule_fv_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vmflt.vf v25, v28, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v12, v12
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -1285,9 +1285,9 @@ define void @fcmp_ule_fv_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z)
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vmfge.vf v25, v28, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmfge.vf v12, v8, fa0
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -1301,10 +1301,10 @@ define void @fcmp_uge_fv_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
; CHECK-LABEL: fcmp_uge_fv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v28, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v12, v12
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -1318,9 +1318,9 @@ define void @fcmp_uge_fv_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z
; CHECK-LABEL: fcmp_uge_fv_v16f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vmfle.vf v25, v28, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmfle.vf v12, v8, fa0
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -1334,10 +1334,10 @@ define void @fcmp_ult_fv_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
; CHECK-LABEL: fcmp_ult_fv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
-; CHECK-NEXT: vmfle.vf v25, v28, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfle.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v12, v12
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -1351,9 +1351,9 @@ define void @fcmp_ult_fv_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z)
; CHECK-LABEL: fcmp_ult_fv_v8f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v28, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -1369,9 +1369,9 @@ define void @fcmp_ugt_fv_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfge.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v8, v16, v16
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -1387,8 +1387,8 @@ define void @fcmp_ugt_fv_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z)
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -1404,10 +1404,10 @@ define void @fcmp_ueq_fv_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) {
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmflt.vf v17, v8, fa0
+; CHECK-NEXT: vmnor.mm v8, v17, v16
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -1423,8 +1423,8 @@ define void @fcmp_ueq_fv_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vmfeq.vf v25, v8, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfeq.vf v16, v8, fa0
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -1439,10 +1439,10 @@ define void @fcmp_one_fv_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmflt.vf v17, v8, fa0
+; CHECK-NEXT: vmor.mm v8, v17, v16
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -1457,8 +1457,8 @@ define void @fcmp_one_fv_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* %
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vmfne.vf v25, v8, fa0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmfne.vf v16, v8, fa0
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -1472,21 +1472,21 @@ define void @fcmp_ord_fv_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ord_fv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v26, v26, fa0
-; CHECK-NEXT: vmfeq.vv v25, v25, v25
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v8, v8, v8
+; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> undef, half %y, i32 0
@@ -1500,21 +1500,21 @@ define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_uno_fv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v26, v26, fa0
-; CHECK-NEXT: vmfne.vv v25, v25, v25
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vmfne.vf v9, v9, fa0
+; CHECK-NEXT: vmfne.vv v8, v8, v8
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> undef, half %y, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
index 3a484b2e36353..35eaa42435224 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
@@ -86,10 +86,10 @@ define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI4_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI4_0)
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v12, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vrgatherei16.vv v26, v8, v25
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vrgatherei16.vv v10, v8, v12
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_permute_shuffle_vu_v4f64:
@@ -97,9 +97,9 @@ define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI4_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI4_0)
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
-; RV64-NEXT: vrgather.vv v26, v8, v28
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vle64.v v12, (a0)
+; RV64-NEXT: vrgather.vv v10, v8, v12
+; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 1>
ret <4 x double> %s
@@ -111,10 +111,10 @@ define <4 x double> @vrgather_permute_shuffle_uv_v4f64(<4 x double> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI5_0)
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v12, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vrgatherei16.vv v26, v8, v25
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vrgatherei16.vv v10, v8, v12
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_permute_shuffle_uv_v4f64:
@@ -122,9 +122,9 @@ define <4 x double> @vrgather_permute_shuffle_uv_v4f64(<4 x double> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI5_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI5_0)
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
-; RV64-NEXT: vrgather.vv v26, v8, v28
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vle64.v v12, (a0)
+; RV64-NEXT: vrgather.vv v10, v8, v12
+; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%s = shufflevector <4 x double> undef, <4 x double> %x, <4 x i32> <i32 5, i32 6, i32 4, i32 5>
ret <4 x double> %s
@@ -136,15 +136,15 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y)
; RV32-NEXT: lui a0, %hi(.LCPI6_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI6_0)
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v14, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vrgatherei16.vv v26, v8, v25
+; RV32-NEXT: vrgatherei16.vv v12, v8, v14
; RV32-NEXT: addi a0, zero, 8
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vrgather.vi v26, v10, 1, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vrgather.vi v12, v10, 1, v0.t
+; RV32-NEXT: vmv2r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_vv_v4f64:
@@ -152,14 +152,14 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y)
; RV64-NEXT: lui a0, %hi(.LCPI6_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI6_0)
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
-; RV64-NEXT: vrgather.vv v26, v8, v28
+; RV64-NEXT: vle64.v v14, (a0)
+; RV64-NEXT: vrgather.vv v12, v8, v14
; RV64-NEXT: addi a0, zero, 8
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vrgather.vi v26, v10, 1, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vrgather.vi v12, v10, 1, v0.t
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
ret <4 x double> %s
@@ -174,12 +174,12 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV32-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI7_0)
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vid.v v25
-; RV32-NEXT: vrsub.vi v25, v25, 4
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vid.v v12
+; RV32-NEXT: vrsub.vi v12, v12, 4
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vrgatherei16.vv v26, v8, v25, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_xv_v4f64:
@@ -190,11 +190,11 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: lui a0, %hi(.LCPI7_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI7_0)
-; RV64-NEXT: vlse64.v v26, (a0), zero
-; RV64-NEXT: vid.v v28
-; RV64-NEXT: vrsub.vi v28, v28, 4
-; RV64-NEXT: vrgather.vv v26, v8, v28, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vlse64.v v10, (a0), zero
+; RV64-NEXT: vid.v v12
+; RV64-NEXT: vrsub.vi v12, v12, 4
+; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t
+; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x double> %s
@@ -204,33 +204,33 @@ define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
; RV32-LABEL: vrgather_shuffle_vx_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vid.v v25
+; RV32-NEXT: vid.v v10
; RV32-NEXT: addi a0, zero, 3
-; RV32-NEXT: vmul.vx v25, v25, a0
+; RV32-NEXT: vmul.vx v12, v10, a0
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: lui a0, %hi(.LCPI8_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI8_0)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vrgatherei16.vv v26, v8, v25, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_vx_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vid.v v26
+; RV64-NEXT: vid.v v10
; RV64-NEXT: addi a0, zero, 3
-; RV64-NEXT: vmul.vx v28, v26, a0
+; RV64-NEXT: vmul.vx v12, v10, a0
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: lui a0, %hi(.LCPI8_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI8_0)
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vlse64.v v26, (a0), zero
-; RV64-NEXT: vrgather.vv v26, v8, v28, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vlse64.v v10, (a0), zero
+; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t
+; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x double> %s
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
index 09faa302e7d9a..02c00403780df 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
@@ -8,8 +8,8 @@ define void @splat_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: splat_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vfmv.v.f v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x half> undef, half %y, i32 0
%b = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> zeroinitializer
@@ -21,8 +21,8 @@ define void @splat_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: splat_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vfmv.v.f v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x float> undef, float %y, i32 0
%b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer
@@ -34,8 +34,8 @@ define void @splat_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: splat_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vfmv.v.f v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x double> undef, double %y, i32 0
%b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer
@@ -47,17 +47,17 @@ define void @splat_16f16(<16 x half>* %x, half %y) {
; LMULMAX2-LABEL: splat_16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vfmv.v.f v26, fa0
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vfmv.v.f v8, fa0
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_16f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vfmv.v.f v25, fa0
+; LMULMAX1-NEXT: vfmv.v.f v8, fa0
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse16.v v25, (a1)
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a1)
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x half> undef, half %y, i32 0
%b = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> zeroinitializer
@@ -69,17 +69,17 @@ define void @splat_v8f32(<8 x float>* %x, float %y) {
; LMULMAX2-LABEL: splat_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vfmv.v.f v26, fa0
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vfmv.v.f v8, fa0
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vfmv.v.f v25, fa0
+; LMULMAX1-NEXT: vfmv.v.f v8, fa0
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse32.v v25, (a1)
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x float> undef, float %y, i32 0
%b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
@@ -91,17 +91,17 @@ define void @splat_v4f64(<4 x double>* %x, double %y) {
; LMULMAX2-LABEL: splat_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vfmv.v.f v26, fa0
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vfmv.v.f v8, fa0
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v4f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vfmv.v.f v25, fa0
+; LMULMAX1-NEXT: vfmv.v.f v8, fa0
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse64.v v25, (a1)
-; LMULMAX1-NEXT: vse64.v v25, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
+; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <4 x double> undef, double %y, i32 0
%b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer
@@ -113,8 +113,8 @@ define void @splat_zero_v8f16(<8 x half>* %x) {
; CHECK-LABEL: splat_zero_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x half> undef, half 0.0, i32 0
%b = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> zeroinitializer
@@ -126,8 +126,8 @@ define void @splat_zero_v4f32(<4 x float>* %x) {
; CHECK-LABEL: splat_zero_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x float> undef, float 0.0, i32 0
%b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer
@@ -139,8 +139,8 @@ define void @splat_zero_v2f64(<2 x double>* %x) {
; CHECK-LABEL: splat_zero_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x double> undef, double 0.0, i32 0
%b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer
@@ -152,17 +152,17 @@ define void @splat_zero_16f16(<16 x half>* %x) {
; LMULMAX2-LABEL: splat_zero_16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_16f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x half> undef, half 0.0, i32 0
%b = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> zeroinitializer
@@ -174,17 +174,17 @@ define void @splat_zero_v8f32(<8 x float>* %x) {
; LMULMAX2-LABEL: splat_zero_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x float> undef, float 0.0, i32 0
%b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
@@ -196,17 +196,17 @@ define void @splat_zero_v4f64(<4 x double>* %x) {
; LMULMAX2-LABEL: splat_zero_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v4f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vse64.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse64.v v25, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <4 x double> undef, double 0.0, i32 0
%b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
index 51715a9f91dbd..eab91b5fcca43 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
@@ -9,8 +9,8 @@ define void @gather_const_v8f16(<8 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 10
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vlse16.v v25, (a1), zero
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vlse16.v v8, (a1), zero
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = extractelement <8 x half> %a, i32 5
@@ -25,8 +25,8 @@ define void @gather_const_v4f32(<4 x float>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 8
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vlse32.v v25, (a1), zero
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vlse32.v v8, (a1), zero
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = extractelement <4 x float> %a, i32 2
@@ -40,8 +40,8 @@ define void @gather_const_v2f64(<2 x double>* %x) {
; CHECK-LABEL: gather_const_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vlse64.v v8, (a0), zero
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = extractelement <2 x double> %a, i32 0
@@ -69,18 +69,18 @@ define void @gather_const_v64f16(<64 x half>* %x) {
; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: addi a5, a0, 94
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vlse16.v v25, (a5), zero
+; LMULMAX1-NEXT: vlse16.v v8, (a5), zero
; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96
-; LMULMAX1-NEXT: vse16.v v25, (a2)
-; LMULMAX1-NEXT: vse16.v v25, (a1)
-; LMULMAX1-NEXT: vse16.v v25, (a5)
-; LMULMAX1-NEXT: vse16.v v25, (a4)
-; LMULMAX1-NEXT: vse16.v v25, (a3)
-; LMULMAX1-NEXT: vse16.v v25, (a7)
-; LMULMAX1-NEXT: vse16.v v25, (a0)
-; LMULMAX1-NEXT: vse16.v v25, (a6)
+; LMULMAX1-NEXT: vse16.v v8, (a2)
+; LMULMAX1-NEXT: vse16.v v8, (a1)
+; LMULMAX1-NEXT: vse16.v v8, (a5)
+; LMULMAX1-NEXT: vse16.v v8, (a4)
+; LMULMAX1-NEXT: vse16.v v8, (a3)
+; LMULMAX1-NEXT: vse16.v v8, (a7)
+; LMULMAX1-NEXT: vse16.v v8, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a6)
; LMULMAX1-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = extractelement <64 x half> %a, i32 47
@@ -108,18 +108,18 @@ define void @gather_const_v32f32(<32 x float>* %x) {
; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: addi a5, a0, 68
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vlse32.v v25, (a5), zero
+; LMULMAX1-NEXT: vlse32.v v8, (a5), zero
; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96
-; LMULMAX1-NEXT: vse32.v v25, (a2)
-; LMULMAX1-NEXT: vse32.v v25, (a1)
-; LMULMAX1-NEXT: vse32.v v25, (a5)
-; LMULMAX1-NEXT: vse32.v v25, (a4)
-; LMULMAX1-NEXT: vse32.v v25, (a3)
-; LMULMAX1-NEXT: vse32.v v25, (a7)
-; LMULMAX1-NEXT: vse32.v v25, (a0)
-; LMULMAX1-NEXT: vse32.v v25, (a6)
+; LMULMAX1-NEXT: vse32.v v8, (a2)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a5)
+; LMULMAX1-NEXT: vse32.v v8, (a4)
+; LMULMAX1-NEXT: vse32.v v8, (a3)
+; LMULMAX1-NEXT: vse32.v v8, (a7)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a6)
; LMULMAX1-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = extractelement <32 x float> %a, i32 17
@@ -145,18 +145,18 @@ define void @gather_const_v16f64(<16 x double>* %x) {
; LMULMAX1-NEXT: addi a3, a0, 32
; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vlse64.v v25, (a4), zero
+; LMULMAX1-NEXT: vlse64.v v8, (a4), zero
; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96
-; LMULMAX1-NEXT: vse64.v v25, (a2)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
-; LMULMAX1-NEXT: vse64.v v25, (a5)
-; LMULMAX1-NEXT: vse64.v v25, (a4)
-; LMULMAX1-NEXT: vse64.v v25, (a3)
-; LMULMAX1-NEXT: vse64.v v25, (a7)
-; LMULMAX1-NEXT: vse64.v v25, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a6)
+; LMULMAX1-NEXT: vse64.v v8, (a2)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
+; LMULMAX1-NEXT: vse64.v v8, (a5)
+; LMULMAX1-NEXT: vse64.v v8, (a4)
+; LMULMAX1-NEXT: vse64.v v8, (a3)
+; LMULMAX1-NEXT: vse64.v v8, (a7)
+; LMULMAX1-NEXT: vse64.v v8, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a6)
; LMULMAX1-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = extractelement <16 x double> %a, i32 10
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
index 13f8a306597c7..a66d41cf80e31 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -8,10 +8,10 @@ define void @fadd_v8f16(<8 x half>* %x, <8 x half>* %y) {
; CHECK-LABEL: fadd_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfadd.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfadd.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -24,10 +24,10 @@ define void @fadd_v4f32(<4 x float>* %x, <4 x float>* %y) {
; CHECK-LABEL: fadd_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfadd.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -40,10 +40,10 @@ define void @fadd_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: fadd_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfadd.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfadd.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -56,10 +56,10 @@ define void @fsub_v8f16(<8 x half>* %x, <8 x half>* %y) {
; CHECK-LABEL: fsub_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfsub.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfsub.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -72,10 +72,10 @@ define void @fsub_v4f32(<4 x float>* %x, <4 x float>* %y) {
; CHECK-LABEL: fsub_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfsub.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfsub.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -88,10 +88,10 @@ define void @fsub_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: fsub_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfsub.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfsub.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -104,10 +104,10 @@ define void @fmul_v8f16(<8 x half>* %x, <8 x half>* %y) {
; CHECK-LABEL: fmul_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfmul.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfmul.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -120,10 +120,10 @@ define void @fmul_v4f32(<4 x float>* %x, <4 x float>* %y) {
; CHECK-LABEL: fmul_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfmul.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfmul.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -136,10 +136,10 @@ define void @fmul_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: fmul_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfmul.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfmul.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -152,10 +152,10 @@ define void @fdiv_v8f16(<8 x half>* %x, <8 x half>* %y) {
; CHECK-LABEL: fdiv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfdiv.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -168,10 +168,10 @@ define void @fdiv_v4f32(<4 x float>* %x, <4 x float>* %y) {
; CHECK-LABEL: fdiv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfdiv.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -184,10 +184,10 @@ define void @fdiv_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: fdiv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfdiv.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -200,9 +200,9 @@ define void @fneg_v8f16(<8 x half>* %x) {
; CHECK-LABEL: fneg_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfsgnjn.vv v25, v25, v25
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = fneg <8 x half> %a
@@ -214,9 +214,9 @@ define void @fneg_v4f32(<4 x float>* %x) {
; CHECK-LABEL: fneg_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfsgnjn.vv v25, v25, v25
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = fneg <4 x float> %a
@@ -228,9 +228,9 @@ define void @fneg_v2f64(<2 x double>* %x) {
; CHECK-LABEL: fneg_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfsgnjn.vv v25, v25, v25
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v8
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = fneg <2 x double> %a
@@ -242,9 +242,9 @@ define void @fabs_v8f16(<8 x half>* %x) {
; CHECK-LABEL: fabs_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfsgnjx.vv v25, v25, v25
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
@@ -257,9 +257,9 @@ define void @fabs_v4f32(<4 x float>* %x) {
; CHECK-LABEL: fabs_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfsgnjx.vv v25, v25, v25
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
@@ -272,9 +272,9 @@ define void @fabs_v2f64(<2 x double>* %x) {
; CHECK-LABEL: fabs_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfsgnjx.vv v25, v25, v25
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfsgnjx.vv v8, v8, v8
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.fabs.v2f64(<2 x double> %a)
@@ -287,10 +287,10 @@ define void @copysign_v8f16(<8 x half>* %x, <8 x half>* %y) {
; CHECK-LABEL: copysign_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfsgnj.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfsgnj.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -304,10 +304,10 @@ define void @copysign_v4f32(<4 x float>* %x, <4 x float>* %y) {
; CHECK-LABEL: copysign_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfsgnj.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfsgnj.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -321,10 +321,10 @@ define void @copysign_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: copysign_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfsgnj.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfsgnj.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -338,9 +338,9 @@ define void @copysign_vf_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: copysign_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfsgnj.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfsgnj.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -354,9 +354,9 @@ define void @copysign_vf_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: copysign_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfsgnj.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfsgnj.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -370,9 +370,9 @@ define void @copysign_vf_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: copysign_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfsgnj.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfsgnj.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -386,10 +386,10 @@ define void @copysign_neg_v8f16(<8 x half>* %x, <8 x half>* %y) {
; CHECK-LABEL: copysign_neg_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfsgnjn.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -403,10 +403,10 @@ define void @copysign_neg_v4f32(<4 x float>* %x, <4 x float>* %y) {
; CHECK-LABEL: copysign_neg_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfsgnjn.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -420,10 +420,10 @@ define void @copysign_neg_v2f64(<2 x double>* %x, <2 x double>* %y) {
; CHECK-LABEL: copysign_neg_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfsgnjn.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -437,11 +437,11 @@ define void @copysign_neg_trunc_v4f16_v4f32(<4 x half>* %x, <4 x float>* %y) {
; CHECK-LABEL: copysign_neg_trunc_v4f16_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vfncvt.f.f.w v27, v25
-; CHECK-NEXT: vfsgnjn.vv v25, v26, v27
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vfsgnjn.vv v8, v9, v10
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -457,13 +457,13 @@ define void @copysign_neg_ext_v2f64_v2f32(<2 x double>* %x, <2 x float>* %y) {
; CHECK-LABEL: copysign_neg_ext_v2f64_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vle64.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v27, v25
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v25, v26, v27
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vfsgnjn.vv v8, v9, v10
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x float>, <2 x float>* %y
@@ -478,9 +478,9 @@ define void @sqrt_v8f16(<8 x half>* %x) {
; CHECK-LABEL: sqrt_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfsqrt.v v25, v25
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfsqrt.v v8, v8
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)
@@ -493,9 +493,9 @@ define void @sqrt_v4f32(<4 x float>* %x) {
; CHECK-LABEL: sqrt_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfsqrt.v v25, v25
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfsqrt.v v8, v8
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
@@ -508,9 +508,9 @@ define void @sqrt_v2f64(<2 x double>* %x) {
; CHECK-LABEL: sqrt_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfsqrt.v v25, v25
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfsqrt.v v8, v8
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
@@ -523,11 +523,11 @@ define void @fma_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x half>* %z) {
; CHECK-LABEL: fma_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vle16.v v27, (a2)
-; CHECK-NEXT: vfmacc.vv v27, v25, v26
-; CHECK-NEXT: vse16.v v27, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: vfmacc.vv v10, v8, v9
+; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -542,11 +542,11 @@ define void @fma_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x float>* %z) {
; CHECK-LABEL: fma_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vle32.v v27, (a2)
-; CHECK-NEXT: vfmacc.vv v27, v25, v26
-; CHECK-NEXT: vse32.v v27, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: vfmacc.vv v10, v8, v9
+; CHECK-NEXT: vse32.v v10, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -561,11 +561,11 @@ define void @fma_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x double>* %z) {
; CHECK-LABEL: fma_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vle64.v v27, (a2)
-; CHECK-NEXT: vfmacc.vv v27, v25, v26
-; CHECK-NEXT: vse64.v v27, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vle64.v v10, (a2)
+; CHECK-NEXT: vfmacc.vv v10, v8, v9
+; CHECK-NEXT: vse64.v v10, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -580,11 +580,11 @@ define void @fmsub_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x half>* %z) {
; CHECK-LABEL: fmsub_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vle16.v v27, (a2)
-; CHECK-NEXT: vfmsac.vv v27, v25, v26
-; CHECK-NEXT: vse16.v v27, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: vfmsac.vv v10, v8, v9
+; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -599,11 +599,11 @@ define void @fnmsub_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x float>* %z) {
; CHECK-LABEL: fnmsub_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vle32.v v27, (a2)
-; CHECK-NEXT: vfnmsac.vv v27, v25, v26
-; CHECK-NEXT: vse32.v v27, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: vfnmsac.vv v10, v8, v9
+; CHECK-NEXT: vse32.v v10, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -618,11 +618,11 @@ define void @fnmadd_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x double>* %z)
; CHECK-LABEL: fnmadd_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vle64.v v27, (a2)
-; CHECK-NEXT: vfnmacc.vv v27, v25, v26
-; CHECK-NEXT: vse64.v v27, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vle64.v v10, (a2)
+; CHECK-NEXT: vfnmacc.vv v10, v8, v9
+; CHECK-NEXT: vse64.v v10, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -638,40 +638,40 @@ define void @fadd_v16f16(<16 x half>* %x, <16 x half>* %y) {
; LMULMAX2-LABEL: fadd_v16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vfadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vfadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fadd_v16f16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfadd.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fadd_v16f16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -684,40 +684,40 @@ define void @fadd_v8f32(<8 x float>* %x, <8 x float>* %y) {
; LMULMAX2-LABEL: fadd_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vfadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vfadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fadd_v8f32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfadd.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fadd_v8f32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -730,40 +730,40 @@ define void @fadd_v4f64(<4 x double>* %x, <4 x double>* %y) {
; LMULMAX2-LABEL: fadd_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vfadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vfadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fadd_v4f64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfadd.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fadd_v4f64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -776,40 +776,40 @@ define void @fsub_v16f16(<16 x half>* %x, <16 x half>* %y) {
; LMULMAX2-LABEL: fsub_v16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vfsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vfsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fsub_v16f16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfsub.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fsub_v16f16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfsub.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfsub.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -822,40 +822,40 @@ define void @fsub_v8f32(<8 x float>* %x, <8 x float>* %y) {
; LMULMAX2-LABEL: fsub_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vfsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vfsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fsub_v8f32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfsub.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fsub_v8f32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfsub.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfsub.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -868,40 +868,40 @@ define void @fsub_v4f64(<4 x double>* %x, <4 x double>* %y) {
; LMULMAX2-LABEL: fsub_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vfsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vfsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fsub_v4f64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfsub.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fsub_v4f64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfsub.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfsub.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -914,40 +914,40 @@ define void @fmul_v16f16(<16 x half>* %x, <16 x half>* %y) {
; LMULMAX2-LABEL: fmul_v16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vfmul.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vfmul.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fmul_v16f16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfmul.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfmul.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfmul.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fmul_v16f16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfmul.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfmul.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -960,40 +960,40 @@ define void @fmul_v8f32(<8 x float>* %x, <8 x float>* %y) {
; LMULMAX2-LABEL: fmul_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vfmul.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vfmul.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fmul_v8f32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfmul.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfmul.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfmul.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fmul_v8f32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfmul.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfmul.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -1006,40 +1006,40 @@ define void @fmul_v4f64(<4 x double>* %x, <4 x double>* %y) {
; LMULMAX2-LABEL: fmul_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vfmul.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vfmul.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fmul_v4f64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfmul.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfmul.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfmul.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fmul_v4f64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfmul.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfmul.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -1052,40 +1052,40 @@ define void @fdiv_v16f16(<16 x half>* %x, <16 x half>* %y) {
; LMULMAX2-LABEL: fdiv_v16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vfdiv.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fdiv_v16f16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfdiv.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fdiv_v16f16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfdiv.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfdiv.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -1098,40 +1098,40 @@ define void @fdiv_v8f32(<8 x float>* %x, <8 x float>* %y) {
; LMULMAX2-LABEL: fdiv_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vfdiv.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fdiv_v8f32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfdiv.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fdiv_v8f32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfdiv.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfdiv.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -1144,40 +1144,40 @@ define void @fdiv_v4f64(<4 x double>* %x, <4 x double>* %y) {
; LMULMAX2-LABEL: fdiv_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vfdiv.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: fdiv_v4f64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vfdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vfdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vfdiv.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: fdiv_v4f64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vfdiv.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vfdiv.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -1190,21 +1190,21 @@ define void @fneg_v16f16(<16 x half>* %x) {
; LMULMAX2-LABEL: fneg_v16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vfsgnjn.vv v26, v26, v26
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vfsgnjn.vv v8, v8, v8
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: fneg_v16f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle16.v v25, (a1)
-; LMULMAX1-NEXT: vle16.v v26, (a0)
-; LMULMAX1-NEXT: vfsgnjn.vv v25, v25, v25
-; LMULMAX1-NEXT: vfsgnjn.vv v26, v26, v26
-; LMULMAX1-NEXT: vse16.v v26, (a0)
-; LMULMAX1-NEXT: vse16.v v25, (a1)
+; LMULMAX1-NEXT: vle16.v v8, (a1)
+; LMULMAX1-NEXT: vle16.v v9, (a0)
+; LMULMAX1-NEXT: vfsgnjn.vv v8, v8, v8
+; LMULMAX1-NEXT: vfsgnjn.vv v9, v9, v9
+; LMULMAX1-NEXT: vse16.v v9, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = fneg <16 x half> %a
@@ -1216,21 +1216,21 @@ define void @fneg_v8f32(<8 x float>* %x) {
; LMULMAX2-LABEL: fneg_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vfsgnjn.vv v26, v26, v26
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vfsgnjn.vv v8, v8, v8
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: fneg_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle32.v v25, (a1)
-; LMULMAX1-NEXT: vle32.v v26, (a0)
-; LMULMAX1-NEXT: vfsgnjn.vv v25, v25, v25
-; LMULMAX1-NEXT: vfsgnjn.vv v26, v26, v26
-; LMULMAX1-NEXT: vse32.v v26, (a0)
-; LMULMAX1-NEXT: vse32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a1)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
+; LMULMAX1-NEXT: vfsgnjn.vv v8, v8, v8
+; LMULMAX1-NEXT: vfsgnjn.vv v9, v9, v9
+; LMULMAX1-NEXT: vse32.v v9, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = fneg <8 x float> %a
@@ -1242,21 +1242,21 @@ define void @fneg_v4f64(<4 x double>* %x) {
; LMULMAX2-LABEL: fneg_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vfsgnjn.vv v26, v26, v26
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vfsgnjn.vv v8, v8, v8
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: fneg_v4f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle64.v v25, (a1)
-; LMULMAX1-NEXT: vle64.v v26, (a0)
-; LMULMAX1-NEXT: vfsgnjn.vv v25, v25, v25
-; LMULMAX1-NEXT: vfsgnjn.vv v26, v26, v26
-; LMULMAX1-NEXT: vse64.v v26, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
+; LMULMAX1-NEXT: vle64.v v8, (a1)
+; LMULMAX1-NEXT: vle64.v v9, (a0)
+; LMULMAX1-NEXT: vfsgnjn.vv v8, v8, v8
+; LMULMAX1-NEXT: vfsgnjn.vv v9, v9, v9
+; LMULMAX1-NEXT: vse64.v v9, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = fneg <4 x double> %a
@@ -1268,29 +1268,29 @@ define void @fma_v16f16(<16 x half>* %x, <16 x half>* %y, <16 x half>* %z) {
; LMULMAX2-LABEL: fma_v16f16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vle16.v v30, (a2)
-; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28
-; LMULMAX2-NEXT: vse16.v v30, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vle16.v v12, (a2)
+; LMULMAX2-NEXT: vfmacc.vv v12, v8, v10
+; LMULMAX2-NEXT: vse16.v v12, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: fma_v16f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v8, (a0)
; LMULMAX1-NEXT: addi a3, a0, 16
-; LMULMAX1-NEXT: vle16.v v26, (a3)
-; LMULMAX1-NEXT: vle16.v v27, (a1)
+; LMULMAX1-NEXT: vle16.v v9, (a3)
+; LMULMAX1-NEXT: vle16.v v10, (a1)
; LMULMAX1-NEXT: addi a1, a1, 16
-; LMULMAX1-NEXT: vle16.v v28, (a1)
+; LMULMAX1-NEXT: vle16.v v11, (a1)
; LMULMAX1-NEXT: addi a1, a2, 16
-; LMULMAX1-NEXT: vle16.v v29, (a1)
-; LMULMAX1-NEXT: vle16.v v30, (a2)
-; LMULMAX1-NEXT: vfmacc.vv v29, v26, v28
-; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27
-; LMULMAX1-NEXT: vse16.v v30, (a0)
-; LMULMAX1-NEXT: vse16.v v29, (a3)
+; LMULMAX1-NEXT: vle16.v v12, (a1)
+; LMULMAX1-NEXT: vle16.v v13, (a2)
+; LMULMAX1-NEXT: vfmacc.vv v12, v9, v11
+; LMULMAX1-NEXT: vfmacc.vv v13, v8, v10
+; LMULMAX1-NEXT: vse16.v v13, (a0)
+; LMULMAX1-NEXT: vse16.v v12, (a3)
; LMULMAX1-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -1305,29 +1305,29 @@ define void @fma_v8f32(<8 x float>* %x, <8 x float>* %y, <8 x float>* %z) {
; LMULMAX2-LABEL: fma_v8f32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vle32.v v30, (a2)
-; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28
-; LMULMAX2-NEXT: vse32.v v30, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vle32.v v12, (a2)
+; LMULMAX2-NEXT: vfmacc.vv v12, v8, v10
+; LMULMAX2-NEXT: vse32.v v12, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: fma_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: addi a3, a0, 16
-; LMULMAX1-NEXT: vle32.v v26, (a3)
-; LMULMAX1-NEXT: vle32.v v27, (a1)
+; LMULMAX1-NEXT: vle32.v v9, (a3)
+; LMULMAX1-NEXT: vle32.v v10, (a1)
; LMULMAX1-NEXT: addi a1, a1, 16
-; LMULMAX1-NEXT: vle32.v v28, (a1)
+; LMULMAX1-NEXT: vle32.v v11, (a1)
; LMULMAX1-NEXT: addi a1, a2, 16
-; LMULMAX1-NEXT: vle32.v v29, (a1)
-; LMULMAX1-NEXT: vle32.v v30, (a2)
-; LMULMAX1-NEXT: vfmacc.vv v29, v26, v28
-; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27
-; LMULMAX1-NEXT: vse32.v v30, (a0)
-; LMULMAX1-NEXT: vse32.v v29, (a3)
+; LMULMAX1-NEXT: vle32.v v12, (a1)
+; LMULMAX1-NEXT: vle32.v v13, (a2)
+; LMULMAX1-NEXT: vfmacc.vv v12, v9, v11
+; LMULMAX1-NEXT: vfmacc.vv v13, v8, v10
+; LMULMAX1-NEXT: vse32.v v13, (a0)
+; LMULMAX1-NEXT: vse32.v v12, (a3)
; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -1342,29 +1342,29 @@ define void @fma_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x double>* %z) {
; LMULMAX2-LABEL: fma_v4f64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vle64.v v30, (a2)
-; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28
-; LMULMAX2-NEXT: vse64.v v30, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vle64.v v12, (a2)
+; LMULMAX2-NEXT: vfmacc.vv v12, v8, v10
+; LMULMAX2-NEXT: vse64.v v12, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: fma_v4f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vle64.v v25, (a0)
+; LMULMAX1-NEXT: vle64.v v8, (a0)
; LMULMAX1-NEXT: addi a3, a0, 16
-; LMULMAX1-NEXT: vle64.v v26, (a3)
-; LMULMAX1-NEXT: vle64.v v27, (a1)
+; LMULMAX1-NEXT: vle64.v v9, (a3)
+; LMULMAX1-NEXT: vle64.v v10, (a1)
; LMULMAX1-NEXT: addi a1, a1, 16
-; LMULMAX1-NEXT: vle64.v v28, (a1)
+; LMULMAX1-NEXT: vle64.v v11, (a1)
; LMULMAX1-NEXT: addi a1, a2, 16
-; LMULMAX1-NEXT: vle64.v v29, (a1)
-; LMULMAX1-NEXT: vle64.v v30, (a2)
-; LMULMAX1-NEXT: vfmacc.vv v29, v26, v28
-; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27
-; LMULMAX1-NEXT: vse64.v v30, (a0)
-; LMULMAX1-NEXT: vse64.v v29, (a3)
+; LMULMAX1-NEXT: vle64.v v12, (a1)
+; LMULMAX1-NEXT: vle64.v v13, (a2)
+; LMULMAX1-NEXT: vfmacc.vv v12, v9, v11
+; LMULMAX1-NEXT: vfmacc.vv v13, v8, v10
+; LMULMAX1-NEXT: vse64.v v13, (a0)
+; LMULMAX1-NEXT: vse64.v v12, (a3)
; LMULMAX1-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -1379,9 +1379,9 @@ define void @fadd_vf_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fadd_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfadd.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfadd.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1395,9 +1395,9 @@ define void @fadd_vf_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fadd_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfadd.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfadd.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1411,9 +1411,9 @@ define void @fadd_vf_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fadd_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfadd.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfadd.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1427,9 +1427,9 @@ define void @fadd_fv_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fadd_fv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfadd.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfadd.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1443,9 +1443,9 @@ define void @fadd_fv_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fadd_fv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfadd.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfadd.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1459,9 +1459,9 @@ define void @fadd_fv_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fadd_fv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfadd.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfadd.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1475,9 +1475,9 @@ define void @fsub_vf_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfsub.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfsub.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1491,9 +1491,9 @@ define void @fsub_vf_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfsub.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfsub.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1507,9 +1507,9 @@ define void @fsub_vf_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fsub_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfsub.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfsub.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1523,9 +1523,9 @@ define void @fsub_fv_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fsub_fv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfrsub.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1539,9 +1539,9 @@ define void @fsub_fv_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fsub_fv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfrsub.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1555,9 +1555,9 @@ define void @fsub_fv_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fsub_fv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfrsub.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfrsub.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1571,9 +1571,9 @@ define void @fmul_vf_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fmul_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfmul.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmul.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1587,9 +1587,9 @@ define void @fmul_vf_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fmul_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfmul.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfmul.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1603,9 +1603,9 @@ define void @fmul_vf_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fmul_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfmul.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfmul.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1619,9 +1619,9 @@ define void @fmul_fv_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fmul_fv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfmul.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmul.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1635,9 +1635,9 @@ define void @fmul_fv_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fmul_fv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfmul.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfmul.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1651,9 +1651,9 @@ define void @fmul_fv_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fmul_fv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfmul.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfmul.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1667,9 +1667,9 @@ define void @fdiv_vf_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fdiv_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfdiv.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfdiv.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1683,9 +1683,9 @@ define void @fdiv_vf_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fdiv_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfdiv.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfdiv.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1699,9 +1699,9 @@ define void @fdiv_vf_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fdiv_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfdiv.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfdiv.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1715,9 +1715,9 @@ define void @fdiv_fv_v8f16(<8 x half>* %x, half %y) {
; CHECK-LABEL: fdiv_fv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfrdiv.vf v25, v25, fa0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1731,9 +1731,9 @@ define void @fdiv_fv_v4f32(<4 x float>* %x, float %y) {
; CHECK-LABEL: fdiv_fv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfrdiv.vf v25, v25, fa0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1747,9 +1747,9 @@ define void @fdiv_fv_v2f64(<2 x double>* %x, double %y) {
; CHECK-LABEL: fdiv_fv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfrdiv.vf v25, v25, fa0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1763,10 +1763,10 @@ define void @fma_vf_v8f16(<8 x half>* %x, <8 x half>* %y, half %z) {
; CHECK-LABEL: fma_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -1781,10 +1781,10 @@ define void @fma_vf_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) {
; CHECK-LABEL: fma_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -1799,10 +1799,10 @@ define void @fma_vf_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) {
; CHECK-LABEL: fma_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -1817,10 +1817,10 @@ define void @fma_fv_v8f16(<8 x half>* %x, <8 x half>* %y, half %z) {
; CHECK-LABEL: fma_fv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -1835,10 +1835,10 @@ define void @fma_fv_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) {
; CHECK-LABEL: fma_fv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -1853,10 +1853,10 @@ define void @fma_fv_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) {
; CHECK-LABEL: fma_fv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -1871,10 +1871,10 @@ define void @fmsub_vf_v8f16(<8 x half>* %x, <8 x half>* %y, half %z) {
; CHECK-LABEL: fmsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vfmsac.vf v26, fa0, v25
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vfmsac.vf v9, fa0, v8
+; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -1890,10 +1890,10 @@ define void @fnmsub_vf_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) {
; CHECK-LABEL: fnmsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfnmsac.vf v26, fa0, v25
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfnmsac.vf v9, fa0, v8
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -1909,10 +1909,10 @@ define void @fnmadd_vf_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) {
; CHECK-LABEL: fnmadd_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfnmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfnmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -1929,10 +1929,10 @@ define void @fnmsub_fv_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) {
; CHECK-LABEL: fnmsub_fv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfnmsac.vf v26, fa0, v25
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfnmsac.vf v9, fa0, v8
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -1948,10 +1948,10 @@ define void @fnmadd_fv_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) {
; CHECK-LABEL: fnmadd_fv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vfnmacc.vf v26, fa0, v25
-; CHECK-NEXT: vse64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vfnmacc.vf v9, fa0, v8
+; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
index 905f6050d80df..fa3ddbb7fb7ef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
@@ -8,9 +8,9 @@ define void @fp2si_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) {
; CHECK-LABEL: fp2si_v2f32_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfcvt.rtz.x.f.v v25, v25
-; CHECK-NEXT: vse32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
+; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%d = fptosi <2 x float> %a to <2 x i32>
@@ -22,9 +22,9 @@ define void @fp2ui_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) {
; CHECK-LABEL: fp2ui_v2f32_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfcvt.rtz.xu.f.v v25, v25
-; CHECK-NEXT: vse32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
+; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%d = fptoui <2 x float> %a to <2 x i32>
@@ -36,9 +36,9 @@ define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) {
; CHECK-LABEL: fp2si_v2f32_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptosi <2 x float> %x to <2 x i1>
ret <2 x i1> %z
@@ -48,9 +48,9 @@ define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) {
; CHECK-LABEL: fp2ui_v2f32_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptoui <2 x float> %x to <2 x i1>
ret <2 x i1> %z
@@ -60,22 +60,22 @@ define void @fp2si_v8f32_v8i32(<8 x float>* %x, <8 x i32>* %y) {
; LMULMAX8-LABEL: fp2si_v8f32_v8i32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
-; LMULMAX8-NEXT: vfcvt.rtz.x.f.v v26, v26
-; LMULMAX8-NEXT: vse32.v v26, (a1)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
+; LMULMAX8-NEXT: vfcvt.rtz.x.f.v v8, v8
+; LMULMAX8-NEXT: vse32.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2si_v8f32_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle32.v v25, (a2)
-; LMULMAX1-NEXT: vle32.v v26, (a0)
-; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v25, v25
-; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v26, v26
-; LMULMAX1-NEXT: vse32.v v26, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a2)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
+; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v8, v8
+; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v9, v9
+; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%d = fptosi <8 x float> %a to <8 x i32>
@@ -87,22 +87,22 @@ define void @fp2ui_v8f32_v8i32(<8 x float>* %x, <8 x i32>* %y) {
; LMULMAX8-LABEL: fp2ui_v8f32_v8i32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
-; LMULMAX8-NEXT: vfcvt.rtz.xu.f.v v26, v26
-; LMULMAX8-NEXT: vse32.v v26, (a1)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
+; LMULMAX8-NEXT: vfcvt.rtz.xu.f.v v8, v8
+; LMULMAX8-NEXT: vse32.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2ui_v8f32_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle32.v v25, (a2)
-; LMULMAX1-NEXT: vle32.v v26, (a0)
-; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v25, v25
-; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v26, v26
-; LMULMAX1-NEXT: vse32.v v26, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a2)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
+; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v8, v8
+; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v9, v9
+; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%d = fptoui <8 x float> %a to <8 x i32>
@@ -114,39 +114,39 @@ define <8 x i1> @fp2si_v8f32_v8i1(<8 x float> %x) {
; LMULMAX8-LABEL: fp2si_v8f32_v8i1:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v25, v8
-; LMULMAX8-NEXT: vand.vi v25, v25, 1
-; LMULMAX8-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v10, v8
+; LMULMAX8-NEXT: vand.vi v8, v10, 1
+; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2si_v8f32_v8i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
+; LMULMAX1-NEXT: vmerge.vim v11, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v8
-; LMULMAX1-NEXT: vand.vi v27, v27, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v8
+; LMULMAX1-NEXT: vand.vi v8, v12, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v11, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v11, 0
+; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v26, v9
-; LMULMAX1-NEXT: vand.vi v26, v26, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9
+; LMULMAX1-NEXT: vand.vi v9, v11, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: ret
%z = fptosi <8 x float> %x to <8 x i1>
ret <8 x i1> %z
@@ -156,39 +156,39 @@ define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) {
; LMULMAX8-LABEL: fp2ui_v8f32_v8i1:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; LMULMAX8-NEXT: vand.vi v25, v25, 1
-; LMULMAX8-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; LMULMAX8-NEXT: vand.vi v8, v10, 1
+; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2ui_v8f32_v8i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
+; LMULMAX1-NEXT: vmerge.vim v11, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v8
-; LMULMAX1-NEXT: vand.vi v27, v27, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; LMULMAX1-NEXT: vand.vi v8, v12, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v11, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v11, 0
+; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v26, v9
-; LMULMAX1-NEXT: vand.vi v26, v26, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9
+; LMULMAX1-NEXT: vand.vi v9, v11, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: ret
%z = fptoui <8 x float> %x to <8 x i1>
ret <8 x i1> %z
@@ -198,9 +198,9 @@ define void @fp2si_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) {
; CHECK-LABEL: fp2si_v2f32_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v25
-; CHECK-NEXT: vse64.v v26, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vse64.v v9, (a1)
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%d = fptosi <2 x float> %a to <2 x i64>
@@ -212,9 +212,9 @@ define void @fp2ui_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) {
; CHECK-LABEL: fp2ui_v2f32_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v25
-; CHECK-NEXT: vse64.v v26, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vse64.v v9, (a1)
; CHECK-NEXT: ret
%a = load <2 x float>, <2 x float>* %x
%d = fptoui <2 x float> %a to <2 x i64>
@@ -226,34 +226,34 @@ define void @fp2si_v8f32_v8i64(<8 x float>* %x, <8 x i64>* %y) {
; LMULMAX8-LABEL: fp2si_v8f32_v8i64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
-; LMULMAX8-NEXT: vfwcvt.rtz.x.f.v v28, v26
-; LMULMAX8-NEXT: vse64.v v28, (a1)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
+; LMULMAX8-NEXT: vfwcvt.rtz.x.f.v v12, v8
+; LMULMAX8-NEXT: vse64.v v12, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2si_v8f32_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle32.v v25, (a2)
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a2)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v10, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v28, v27
+; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v11, v10
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v29, v27
-; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v27, v25
-; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v25, v26
+; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v12, v10
+; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v8, v9
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse64.v v29, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
+; LMULMAX1-NEXT: vse64.v v12, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
-; LMULMAX1-NEXT: vse64.v v28, (a0)
+; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 32
-; LMULMAX1-NEXT: vse64.v v27, (a0)
+; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%d = fptosi <8 x float> %a to <8 x i64>
@@ -265,34 +265,34 @@ define void @fp2ui_v8f32_v8i64(<8 x float>* %x, <8 x i64>* %y) {
; LMULMAX8-LABEL: fp2ui_v8f32_v8i64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
-; LMULMAX8-NEXT: vfwcvt.rtz.xu.f.v v28, v26
-; LMULMAX8-NEXT: vse64.v v28, (a1)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
+; LMULMAX8-NEXT: vfwcvt.rtz.xu.f.v v12, v8
+; LMULMAX8-NEXT: vse64.v v12, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2ui_v8f32_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle32.v v25, (a2)
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a2)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v10, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v28, v27
+; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v11, v10
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2
+; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v29, v27
-; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v27, v25
-; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v25, v26
+; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v12, v10
+; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse64.v v29, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
+; LMULMAX1-NEXT: vse64.v v12, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
-; LMULMAX1-NEXT: vse64.v v28, (a0)
+; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 32
-; LMULMAX1-NEXT: vse64.v v27, (a0)
+; LMULMAX1-NEXT: vse64.v v10, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%d = fptoui <8 x float> %a to <8 x i64>
@@ -304,11 +304,11 @@ define void @fp2si_v2f16_v2i64(<2 x half>* %x, <2 x i64>* %y) {
; CHECK-LABEL: fp2si_v2f16_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v26
-; CHECK-NEXT: vse64.v v25, (a1)
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%d = fptosi <2 x half> %a to <2 x i64>
@@ -320,11 +320,11 @@ define void @fp2ui_v2f16_v2i64(<2 x half>* %x, <2 x i64>* %y) {
; CHECK-LABEL: fp2ui_v2f16_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v26
-; CHECK-NEXT: vse64.v v25, (a1)
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%d = fptoui <2 x half> %a to <2 x i64>
@@ -336,9 +336,9 @@ define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) {
; CHECK-LABEL: fp2si_v2f16_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptosi <2 x half> %x to <2 x i1>
ret <2 x i1> %z
@@ -348,9 +348,9 @@ define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) {
; CHECK-LABEL: fp2ui_v2f16_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptoui <2 x half> %x to <2 x i1>
ret <2 x i1> %z
@@ -360,14 +360,14 @@ define void @fp2si_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) {
; CHECK-LABEL: fp2si_v2f64_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%d = fptosi <2 x double> %a to <2 x i8>
@@ -379,14 +379,14 @@ define void @fp2ui_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) {
; CHECK-LABEL: fp2ui_v2f64_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%d = fptoui <2 x double> %a to <2 x i8>
@@ -398,9 +398,9 @@ define <2 x i1> @fp2si_v2f64_v2i1(<2 x double> %x) {
; CHECK-LABEL: fp2si_v2f64_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptosi <2 x double> %x to <2 x i1>
ret <2 x i1> %z
@@ -410,9 +410,9 @@ define <2 x i1> @fp2ui_v2f64_v2i1(<2 x double> %x) {
; CHECK-LABEL: fp2ui_v2f64_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptoui <2 x double> %x to <2 x i1>
ret <2 x i1> %z
@@ -422,61 +422,61 @@ define void @fp2si_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
; LMULMAX8-LABEL: fp2si_v8f64_v8i8:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX8-NEXT: vle64.v v28, (a0)
+; LMULMAX8-NEXT: vle64.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v26, v28
+; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX8-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX8-NEXT: vse8.v v25, (a1)
+; LMULMAX8-NEXT: vnsrl.wi v8, v8, 0
+; LMULMAX8-NEXT: vse8.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2si_v8f64_v8i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vle64.v v25, (a2)
+; LMULMAX1-NEXT: vle64.v v8, (a2)
; LMULMAX1-NEXT: addi a2, a0, 32
-; LMULMAX1-NEXT: vle64.v v26, (a2)
-; LMULMAX1-NEXT: vle64.v v27, (a0)
+; LMULMAX1-NEXT: vle64.v v9, (a2)
+; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle64.v v28, (a0)
+; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v29, v27
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v29, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v28
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v26
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v26, v25
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
-; LMULMAX1-NEXT: vse8.v v29, (a1)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 6
+; LMULMAX1-NEXT: vse8.v v12, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%d = fptosi <8 x double> %a to <8 x i8>
@@ -488,61 +488,61 @@ define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
; LMULMAX8-LABEL: fp2ui_v8f64_v8i8:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX8-NEXT: vle64.v v28, (a0)
+; LMULMAX8-NEXT: vle64.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v26, v28
+; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX8-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX8-NEXT: vse8.v v25, (a1)
+; LMULMAX8-NEXT: vnsrl.wi v8, v8, 0
+; LMULMAX8-NEXT: vse8.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2ui_v8f64_v8i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vle64.v v25, (a2)
+; LMULMAX1-NEXT: vle64.v v8, (a2)
; LMULMAX1-NEXT: addi a2, a0, 32
-; LMULMAX1-NEXT: vle64.v v26, (a2)
-; LMULMAX1-NEXT: vle64.v v27, (a0)
+; LMULMAX1-NEXT: vle64.v v9, (a2)
+; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle64.v v28, (a0)
+; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v29, v27
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v29, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v28
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v26
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v27, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v26, v25
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
-; LMULMAX1-NEXT: vse8.v v29, (a1)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 6
+; LMULMAX1-NEXT: vse8.v v12, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%d = fptoui <8 x double> %a to <8 x i8>
@@ -554,61 +554,61 @@ define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) {
; LMULMAX8-LABEL: fp2si_v8f64_v8i1:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v26, v8
-; LMULMAX8-NEXT: vand.vi v26, v26, 1
-; LMULMAX8-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8
+; LMULMAX8-NEXT: vand.vi v8, v12, 1
+; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2si_v8f64_v8i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
+; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v8
-; LMULMAX1-NEXT: vand.vi v27, v27, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v14, v8
+; LMULMAX1-NEXT: vand.vi v8, v14, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v14, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v13, v14, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v13, 0
+; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v28, v9
-; LMULMAX1-NEXT: vand.vi v28, v28, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v14, v9
+; LMULMAX1-NEXT: vand.vi v9, v14, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v9, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v13, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v13, 0
+; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v28, v10
-; LMULMAX1-NEXT: vand.vi v28, v28, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v10
+; LMULMAX1-NEXT: vand.vi v10, v13, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v10, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 4
+; LMULMAX1-NEXT: vslideup.vi v9, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
+; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v26, v11
-; LMULMAX1-NEXT: vand.vi v26, v26, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11
+; LMULMAX1-NEXT: vand.vi v10, v10, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 6
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: ret
%z = fptosi <8 x double> %x to <8 x i1>
ret <8 x i1> %z
@@ -618,61 +618,61 @@ define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) {
; LMULMAX8-LABEL: fp2ui_v8f64_v8i1:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; LMULMAX8-NEXT: vand.vi v26, v26, 1
-; LMULMAX8-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; LMULMAX8-NEXT: vand.vi v8, v12, 1
+; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: fp2ui_v8f64_v8i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
+; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v8
-; LMULMAX1-NEXT: vand.vi v27, v27, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v27, 0
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v14, v8
+; LMULMAX1-NEXT: vand.vi v8, v14, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vmerge.vim v14, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v13, v14, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v13, 0
+; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v28, v9
-; LMULMAX1-NEXT: vand.vi v28, v28, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v14, v9
+; LMULMAX1-NEXT: vand.vi v9, v14, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v9, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v13, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v13, 0
+; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v28, v10
-; LMULMAX1-NEXT: vand.vi v28, v28, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v10
+; LMULMAX1-NEXT: vand.vi v10, v13, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v10, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v28, 4
+; LMULMAX1-NEXT: vslideup.vi v9, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
+; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v26, v11
-; LMULMAX1-NEXT: vand.vi v26, v26, 1
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11
+; LMULMAX1-NEXT: vand.vi v10, v10, 1
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 6
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: ret
%z = fptoui <8 x double> %x to <8 x i1>
ret <8 x i1> %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index 0e3afd64cd7e5..de3f024fd3cc4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -8,9 +8,9 @@ define void @si2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) {
; CHECK-LABEL: si2fp_v2i32_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfcvt.f.x.v v25, v25
-; CHECK-NEXT: vse32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
+; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%d = sitofp <2 x i32> %a to <2 x float>
@@ -22,9 +22,9 @@ define void @ui2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) {
; CHECK-LABEL: ui2fp_v2i32_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfcvt.f.xu.v v25, v25
-; CHECK-NEXT: vse32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
+; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%d = uitofp <2 x i32> %a to <2 x float>
@@ -36,9 +36,9 @@ define <2 x float> @si2fp_v2i1_v2f32(<2 x i1> %x) {
; CHECK-LABEL: si2fp_v2i1_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x float>
ret <2 x float> %z
@@ -48,9 +48,9 @@ define <2 x float> @ui2fp_v2i1_v2f32(<2 x i1> %x) {
; CHECK-LABEL: ui2fp_v2i1_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x float>
ret <2 x float> %z
@@ -60,22 +60,22 @@ define void @si2fp_v8i32_v8f32(<8 x i32>* %x, <8 x float>* %y) {
; LMULMAX8-LABEL: si2fp_v8i32_v8f32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
-; LMULMAX8-NEXT: vfcvt.f.x.v v26, v26
-; LMULMAX8-NEXT: vse32.v v26, (a1)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
+; LMULMAX8-NEXT: vfcvt.f.x.v v8, v8
+; LMULMAX8-NEXT: vse32.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: si2fp_v8i32_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle32.v v25, (a2)
-; LMULMAX1-NEXT: vle32.v v26, (a0)
-; LMULMAX1-NEXT: vfcvt.f.x.v v25, v25
-; LMULMAX1-NEXT: vfcvt.f.x.v v26, v26
-; LMULMAX1-NEXT: vse32.v v26, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a2)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
+; LMULMAX1-NEXT: vfcvt.f.x.v v8, v8
+; LMULMAX1-NEXT: vfcvt.f.x.v v9, v9
+; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%d = sitofp <8 x i32> %a to <8 x float>
@@ -87,22 +87,22 @@ define void @ui2fp_v8i32_v8f32(<8 x i32>* %x, <8 x float>* %y) {
; LMULMAX8-LABEL: ui2fp_v8i32_v8f32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
-; LMULMAX8-NEXT: vfcvt.f.xu.v v26, v26
-; LMULMAX8-NEXT: vse32.v v26, (a1)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
+; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8
+; LMULMAX8-NEXT: vse32.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: ui2fp_v8i32_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle32.v v25, (a2)
-; LMULMAX1-NEXT: vle32.v v26, (a0)
-; LMULMAX1-NEXT: vfcvt.f.xu.v v25, v25
-; LMULMAX1-NEXT: vfcvt.f.xu.v v26, v26
-; LMULMAX1-NEXT: vse32.v v26, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a2)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
+; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v8
+; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v9
+; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%d = uitofp <8 x i32> %a to <8 x float>
@@ -114,27 +114,27 @@ define <8 x float> @si2fp_v8i1_v8f32(<8 x i1> %x) {
; LMULMAX8-LABEL: si2fp_v8i1_v8f32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, 0
-; LMULMAX8-NEXT: vmerge.vim v26, v26, -1, v0
-; LMULMAX8-NEXT: vfcvt.f.x.v v8, v26
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vmerge.vim v8, v8, -1, v0
+; LMULMAX8-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: si2fp_v8i1_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, -1, v0
-; LMULMAX1-NEXT: vfcvt.f.x.v v8, v26
+; LMULMAX1-NEXT: vmv.v.i v9, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v9, -1, v0
+; LMULMAX1-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v26, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
+; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v25, -1, v0
-; LMULMAX1-NEXT: vfcvt.f.x.v v9, v25
+; LMULMAX1-NEXT: vmerge.vim v9, v9, -1, v0
+; LMULMAX1-NEXT: vfcvt.f.x.v v9, v9
; LMULMAX1-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x float>
ret <8 x float> %z
@@ -144,27 +144,27 @@ define <8 x float> @ui2fp_v8i1_v8f32(<8 x i1> %x) {
; LMULMAX8-LABEL: ui2fp_v8i1_v8f32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, 0
-; LMULMAX8-NEXT: vmerge.vim v26, v26, 1, v0
-; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v26
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: ui2fp_v8i1_v8f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0
-; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v26
+; LMULMAX1-NEXT: vmv.v.i v9, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v9, 1, v0
+; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
-; LMULMAX1-NEXT: vmerge.vim v26, v26, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
+; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v26, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
-; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v25
+; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
+; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v9
; LMULMAX1-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x float>
ret <8 x float> %z
@@ -174,11 +174,11 @@ define void @si2fp_v2i16_v2f64(<2 x i16>* %x, <2 x double>* %y) {
; CHECK-LABEL: si2fp_v2i16_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v25
-; CHECK-NEXT: vfcvt.f.x.v v25, v26
-; CHECK-NEXT: vse64.v v25, (a1)
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v9
+; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%d = sitofp <2 x i16> %a to <2 x double>
@@ -190,11 +190,11 @@ define void @ui2fp_v2i16_v2f64(<2 x i16>* %x, <2 x double>* %y) {
; CHECK-LABEL: ui2fp_v2i16_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v25
-; CHECK-NEXT: vfcvt.f.xu.v v25, v26
-; CHECK-NEXT: vse64.v v25, (a1)
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v9
+; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%d = uitofp <2 x i16> %a to <2 x double>
@@ -206,40 +206,40 @@ define void @si2fp_v8i16_v8f64(<8 x i16>* %x, <8 x double>* %y) {
; LMULMAX8-LABEL: si2fp_v8i16_v8f64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX8-NEXT: vle16.v v25, (a0)
+; LMULMAX8-NEXT: vle16.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX8-NEXT: vsext.vf4 v28, v25
-; LMULMAX8-NEXT: vfcvt.f.x.v v28, v28
-; LMULMAX8-NEXT: vse64.v v28, (a1)
+; LMULMAX8-NEXT: vsext.vf4 v12, v8
+; LMULMAX8-NEXT: vfcvt.f.x.v v8, v12
+; LMULMAX8-NEXT: vse64.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: si2fp_v8i16_v8f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v27, v26
-; LMULMAX1-NEXT: vfcvt.f.x.v v26, v27
+; LMULMAX1-NEXT: vsext.vf4 v10, v9
+; LMULMAX1-NEXT: vfcvt.f.x.v v9, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v29, v28
-; LMULMAX1-NEXT: vfcvt.f.x.v v28, v29
-; LMULMAX1-NEXT: vsext.vf4 v29, v27
-; LMULMAX1-NEXT: vfcvt.f.x.v v27, v29
-; LMULMAX1-NEXT: vsext.vf4 v29, v25
-; LMULMAX1-NEXT: vfcvt.f.x.v v25, v29
+; LMULMAX1-NEXT: vsext.vf4 v12, v11
+; LMULMAX1-NEXT: vfcvt.f.x.v v11, v12
+; LMULMAX1-NEXT: vsext.vf4 v12, v10
+; LMULMAX1-NEXT: vfcvt.f.x.v v10, v12
+; LMULMAX1-NEXT: vsext.vf4 v12, v8
+; LMULMAX1-NEXT: vfcvt.f.x.v v8, v12
; LMULMAX1-NEXT: addi a0, a1, 32
-; LMULMAX1-NEXT: vse64.v v27, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
+; LMULMAX1-NEXT: vse64.v v10, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
-; LMULMAX1-NEXT: vse64.v v28, (a0)
+; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse64.v v26, (a0)
+; LMULMAX1-NEXT: vse64.v v9, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%d = sitofp <8 x i16> %a to <8 x double>
@@ -251,40 +251,40 @@ define void @ui2fp_v8i16_v8f64(<8 x i16>* %x, <8 x double>* %y) {
; LMULMAX8-LABEL: ui2fp_v8i16_v8f64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX8-NEXT: vle16.v v25, (a0)
+; LMULMAX8-NEXT: vle16.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; LMULMAX8-NEXT: vzext.vf4 v28, v25
-; LMULMAX8-NEXT: vfcvt.f.xu.v v28, v28
-; LMULMAX8-NEXT: vse64.v v28, (a1)
+; LMULMAX8-NEXT: vzext.vf4 v12, v8
+; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v12
+; LMULMAX8-NEXT: vse64.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: ui2fp_v8i16_v8f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v27, v26
-; LMULMAX1-NEXT: vfcvt.f.xu.v v26, v27
+; LMULMAX1-NEXT: vzext.vf4 v10, v9
+; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v27, 2
+; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vzext.vf4 v29, v28
-; LMULMAX1-NEXT: vfcvt.f.xu.v v28, v29
-; LMULMAX1-NEXT: vzext.vf4 v29, v27
-; LMULMAX1-NEXT: vfcvt.f.xu.v v27, v29
-; LMULMAX1-NEXT: vzext.vf4 v29, v25
-; LMULMAX1-NEXT: vfcvt.f.xu.v v25, v29
+; LMULMAX1-NEXT: vzext.vf4 v12, v11
+; LMULMAX1-NEXT: vfcvt.f.xu.v v11, v12
+; LMULMAX1-NEXT: vzext.vf4 v12, v10
+; LMULMAX1-NEXT: vfcvt.f.xu.v v10, v12
+; LMULMAX1-NEXT: vzext.vf4 v12, v8
+; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v12
; LMULMAX1-NEXT: addi a0, a1, 32
-; LMULMAX1-NEXT: vse64.v v27, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
+; LMULMAX1-NEXT: vse64.v v10, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 48
-; LMULMAX1-NEXT: vse64.v v28, (a0)
+; LMULMAX1-NEXT: vse64.v v11, (a0)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse64.v v26, (a0)
+; LMULMAX1-NEXT: vse64.v v9, (a0)
; LMULMAX1-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%d = uitofp <8 x i16> %a to <8 x double>
@@ -296,48 +296,48 @@ define <8 x double> @si2fp_v8i1_v8f64(<8 x i1> %x) {
; LMULMAX8-LABEL: si2fp_v8i1_v8f64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v28, 0
-; LMULMAX8-NEXT: vmerge.vim v28, v28, -1, v0
-; LMULMAX8-NEXT: vfcvt.f.x.v v8, v28
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vmerge.vim v8, v8, -1, v0
+; LMULMAX8-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: si2fp_v8i1_v8f64:
; LMULMAX1: # %bb.0:
-; LMULMAX1-NEXT: vmv1r.v v25, v0
+; LMULMAX1-NEXT: vmv1r.v v10, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
-; LMULMAX1-NEXT: vmerge.vim v27, v26, -1, v0
-; LMULMAX1-NEXT: vfcvt.f.x.v v8, v27
+; LMULMAX1-NEXT: vmv.v.i v11, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v11, -1, v0
+; LMULMAX1-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
+; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v28, 2
+; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v28, v26, -1, v0
-; LMULMAX1-NEXT: vfcvt.f.x.v v9, v28
+; LMULMAX1-NEXT: vmerge.vim v9, v11, -1, v0
+; LMULMAX1-NEXT: vfcvt.f.x.v v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v28, 0
-; LMULMAX1-NEXT: vmv1r.v v0, v25
-; LMULMAX1-NEXT: vmerge.vim v25, v28, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v13, 0
+; LMULMAX1-NEXT: vmv1r.v v0, v10
+; LMULMAX1-NEXT: vmerge.vim v10, v13, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v26, -1, v0
-; LMULMAX1-NEXT: vfcvt.f.x.v v10, v25
+; LMULMAX1-NEXT: vmerge.vim v10, v11, -1, v0
+; LMULMAX1-NEXT: vfcvt.f.x.v v10, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v12, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v26, -1, v0
-; LMULMAX1-NEXT: vfcvt.f.x.v v11, v25
+; LMULMAX1-NEXT: vmerge.vim v11, v11, -1, v0
+; LMULMAX1-NEXT: vfcvt.f.x.v v11, v11
; LMULMAX1-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x double>
ret <8 x double> %z
@@ -347,48 +347,48 @@ define <8 x double> @ui2fp_v8i1_v8f64(<8 x i1> %x) {
; LMULMAX8-LABEL: ui2fp_v8i1_v8f64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v28, 0
-; LMULMAX8-NEXT: vmerge.vim v28, v28, 1, v0
-; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v28
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: ui2fp_v8i1_v8f64:
; LMULMAX1: # %bb.0:
-; LMULMAX1-NEXT: vmv1r.v v25, v0
+; LMULMAX1-NEXT: vmv1r.v v10, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v26, 0
-; LMULMAX1-NEXT: vmerge.vim v27, v26, 1, v0
-; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v27
+; LMULMAX1-NEXT: vmv.v.i v11, 0
+; LMULMAX1-NEXT: vmerge.vim v8, v11, 1, v0
+; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
-; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
+; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v28, v28, 2
+; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v28, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v28, v26, 1, v0
-; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v28
+; LMULMAX1-NEXT: vmerge.vim v9, v11, 1, v0
+; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v28, 0
-; LMULMAX1-NEXT: vmv1r.v v0, v25
-; LMULMAX1-NEXT: vmerge.vim v25, v28, 1, v0
+; LMULMAX1-NEXT: vmv.v.i v13, 0
+; LMULMAX1-NEXT: vmv1r.v v0, v10
+; LMULMAX1-NEXT: vmerge.vim v10, v13, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v26, 1, v0
-; LMULMAX1-NEXT: vfcvt.f.xu.v v10, v25
+; LMULMAX1-NEXT: vmerge.vim v10, v11, 1, v0
+; LMULMAX1-NEXT: vfcvt.f.xu.v v10, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v27, 1, v0
+; LMULMAX1-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2
+; LMULMAX1-NEXT: vslidedown.vi v12, v12, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmsne.vi v0, v25, 0
+; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vim v25, v26, 1, v0
-; LMULMAX1-NEXT: vfcvt.f.xu.v v11, v25
+; LMULMAX1-NEXT: vmerge.vim v11, v11, 1, v0
+; LMULMAX1-NEXT: vfcvt.f.xu.v v11, v11
; LMULMAX1-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x double>
ret <8 x double> %z
@@ -398,12 +398,12 @@ define void @si2fp_v2i64_v2f16(<2 x i64>* %x, <2 x half>* %y) {
; CHECK-LABEL: si2fp_v2i64_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v26
-; CHECK-NEXT: vse16.v v25, (a1)
+; CHECK-NEXT: vfncvt.f.f.w v8, v9
+; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%d = sitofp <2 x i64> %a to <2 x half>
@@ -415,12 +415,12 @@ define void @ui2fp_v2i64_v2f16(<2 x i64>* %x, <2 x half>* %y) {
; CHECK-LABEL: ui2fp_v2i64_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v26
-; CHECK-NEXT: vse16.v v25, (a1)
+; CHECK-NEXT: vfncvt.f.f.w v8, v9
+; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%d = uitofp <2 x i64> %a to <2 x half>
@@ -432,9 +432,9 @@ define <2 x half> @si2fp_v2i1_v2f16(<2 x i1> %x) {
; CHECK-LABEL: si2fp_v2i1_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x half>
ret <2 x half> %z
@@ -444,9 +444,9 @@ define <2 x half> @ui2fp_v2i1_v2f16(<2 x i1> %x) {
; CHECK-LABEL: ui2fp_v2i1_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x half>
ret <2 x half> %z
@@ -456,51 +456,51 @@ define void @si2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) {
; LMULMAX8-LABEL: si2fp_v8i64_v8f16:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX8-NEXT: vle64.v v28, (a0)
+; LMULMAX8-NEXT: vle64.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfncvt.f.x.w v26, v28
+; LMULMAX8-NEXT: vfncvt.f.x.w v12, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
-; LMULMAX8-NEXT: vse16.v v25, (a1)
+; LMULMAX8-NEXT: vfncvt.f.f.w v8, v12
+; LMULMAX8-NEXT: vse16.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: si2fp_v8i64_v8f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vle64.v v25, (a2)
+; LMULMAX1-NEXT: vle64.v v8, (a2)
; LMULMAX1-NEXT: addi a2, a0, 32
-; LMULMAX1-NEXT: vle64.v v26, (a2)
-; LMULMAX1-NEXT: vle64.v v27, (a0)
+; LMULMAX1-NEXT: vle64.v v9, (a2)
+; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle64.v v28, (a0)
+; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.x.w v29, v27
+; LMULMAX1-NEXT: vfncvt.f.x.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29
+; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v29, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.x.w v27, v28
+; LMULMAX1-NEXT: vfncvt.f.x.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27
+; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.x.w v27, v26
+; LMULMAX1-NEXT: vfncvt.f.x.w v10, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27
+; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.x.w v26, v25
+; LMULMAX1-NEXT: vfncvt.f.x.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26
+; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
-; LMULMAX1-NEXT: vse16.v v29, (a1)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 6
+; LMULMAX1-NEXT: vse16.v v12, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%d = sitofp <8 x i64> %a to <8 x half>
@@ -512,51 +512,51 @@ define void @ui2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) {
; LMULMAX8-LABEL: ui2fp_v8i64_v8f16:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX8-NEXT: vle64.v v28, (a0)
+; LMULMAX8-NEXT: vle64.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX8-NEXT: vfncvt.f.xu.w v26, v28
+; LMULMAX8-NEXT: vfncvt.f.xu.w v12, v8
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26
-; LMULMAX8-NEXT: vse16.v v25, (a1)
+; LMULMAX8-NEXT: vfncvt.f.f.w v8, v12
+; LMULMAX8-NEXT: vse16.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX1-LABEL: ui2fp_v8i64_v8f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vle64.v v25, (a2)
+; LMULMAX1-NEXT: vle64.v v8, (a2)
; LMULMAX1-NEXT: addi a2, a0, 32
-; LMULMAX1-NEXT: vle64.v v26, (a2)
-; LMULMAX1-NEXT: vle64.v v27, (a0)
+; LMULMAX1-NEXT: vle64.v v9, (a2)
+; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle64.v v28, (a0)
+; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.xu.w v29, v27
+; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29
+; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v29, 0
+; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v27, 0
+; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v28
+; LMULMAX1-NEXT: vfncvt.f.xu.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27
+; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v28, 2
+; LMULMAX1-NEXT: vslideup.vi v12, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v26
+; LMULMAX1-NEXT: vfncvt.f.xu.w v10, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27
+; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v26, 4
+; LMULMAX1-NEXT: vslideup.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.xu.w v26, v25
+; LMULMAX1-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26
+; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v29, v25, 6
-; LMULMAX1-NEXT: vse16.v v29, (a1)
+; LMULMAX1-NEXT: vslideup.vi v12, v8, 6
+; LMULMAX1-NEXT: vse16.v v12, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%d = uitofp <8 x i64> %a to <8 x half>
@@ -568,9 +568,9 @@ define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) {
; CHECK-LABEL: si2fp_v8i1_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x half>
ret <8 x half> %z
@@ -580,9 +580,9 @@ define <8 x half> @ui2fp_v8i1_v8f16(<8 x i1> %x) {
; CHECK-LABEL: ui2fp_v8i1_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x half>
ret <8 x half> %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
index c1187e035ce11..613433c3cd26a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
@@ -8,13 +8,13 @@ define <1 x i1> @insertelt_v1i1(<1 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <1 x i1> %x, i1 %elt, i64 0
ret <1 x i1> %y
@@ -24,30 +24,30 @@ define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) noun
; RV32-LABEL: insertelt_idx_v1i1:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
-; RV32-NEXT: vmv.v.i v26, 0
-; RV32-NEXT: vmerge.vim v26, v26, 1, v0
+; RV32-NEXT: vmv.s.x v8, a0
+; RV32-NEXT: vmv.v.i v9, 0
+; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
-; RV32-NEXT: vslideup.vx v26, v25, a1
+; RV32-NEXT: vslideup.vx v9, v8, a1
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; RV32-NEXT: vand.vi v25, v26, 1
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vand.vi v8, v9, 1
+; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_idx_v1i1:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; RV64-NEXT: vmv.s.x v25, a0
-; RV64-NEXT: vmv.v.i v26, 0
-; RV64-NEXT: vmerge.vim v26, v26, 1, v0
+; RV64-NEXT: vmv.s.x v8, a0
+; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; RV64-NEXT: vslideup.vx v26, v25, a0
+; RV64-NEXT: vslideup.vx v9, v8, a0
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; RV64-NEXT: vand.vi v25, v26, 1
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vand.vi v8, v9, 1
+; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret
%y = insertelement <1 x i1> %x, i1 %elt, i32 %idx
ret <1 x i1> %y
@@ -57,14 +57,14 @@ define <2 x i1> @insertelt_v2i1(<2 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 1
+; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <2 x i1> %x, i1 %elt, i64 1
ret <2 x i1> %y
@@ -74,30 +74,30 @@ define <2 x i1> @insertelt_idx_v2i1(<2 x i1> %x, i1 %elt, i32 zeroext %idx) noun
; RV32-LABEL: insertelt_idx_v2i1:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
-; RV32-NEXT: vmv.v.i v26, 0
-; RV32-NEXT: vmerge.vim v26, v26, 1, v0
+; RV32-NEXT: vmv.s.x v8, a0
+; RV32-NEXT: vmv.v.i v9, 0
+; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
-; RV32-NEXT: vslideup.vx v26, v25, a1
+; RV32-NEXT: vslideup.vx v9, v8, a1
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vand.vi v25, v26, 1
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vand.vi v8, v9, 1
+; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_idx_v2i1:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vmv.s.x v25, a0
-; RV64-NEXT: vmv.v.i v26, 0
-; RV64-NEXT: vmerge.vim v26, v26, 1, v0
+; RV64-NEXT: vmv.s.x v8, a0
+; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; RV64-NEXT: vslideup.vx v26, v25, a0
+; RV64-NEXT: vslideup.vx v9, v8, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vand.vi v25, v26, 1
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vand.vi v8, v9, 1
+; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret
%y = insertelement <2 x i1> %x, i1 %elt, i32 %idx
ret <2 x i1> %y
@@ -107,14 +107,14 @@ define <8 x i1> @insertelt_v8i1(<8 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 1
+; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <8 x i1> %x, i1 %elt, i64 1
ret <8 x i1> %y
@@ -124,30 +124,30 @@ define <8 x i1> @insertelt_idx_v8i1(<8 x i1> %x, i1 %elt, i32 zeroext %idx) noun
; RV32-LABEL: insertelt_idx_v8i1:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
-; RV32-NEXT: vmv.v.i v26, 0
-; RV32-NEXT: vmerge.vim v26, v26, 1, v0
+; RV32-NEXT: vmv.s.x v8, a0
+; RV32-NEXT: vmv.v.i v9, 0
+; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vx v26, v25, a1
+; RV32-NEXT: vslideup.vx v9, v8, a1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vand.vi v25, v26, 1
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vand.vi v8, v9, 1
+; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_idx_v8i1:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.s.x v25, a0
-; RV64-NEXT: vmv.v.i v26, 0
-; RV64-NEXT: vmerge.vim v26, v26, 1, v0
+; RV64-NEXT: vmv.s.x v8, a0
+; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vx v26, v25, a0
+; RV64-NEXT: vslideup.vx v9, v8, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vand.vi v25, v26, 1
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vand.vi v8, v9, 1
+; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret
%y = insertelement <8 x i1> %x, i1 %elt, i32 %idx
ret <8 x i1> %y
@@ -158,14 +158,14 @@ define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 1
+; CHECK-NEXT: vslideup.vi v12, v8, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i64 1
ret <64 x i1> %y
@@ -176,31 +176,31 @@ define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) n
; RV32: # %bb.0:
; RV32-NEXT: addi a2, zero, 64
; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; RV32-NEXT: vmv.s.x v28, a0
-; RV32-NEXT: vmv.v.i v8, 0
-; RV32-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-NEXT: vmv.s.x v8, a0
+; RV32-NEXT: vmv.v.i v12, 0
+; RV32-NEXT: vmerge.vim v12, v12, 1, v0
; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, m4, tu, mu
-; RV32-NEXT: vslideup.vx v8, v28, a1
+; RV32-NEXT: vslideup.vx v12, v8, a1
; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; RV32-NEXT: vand.vi v28, v8, 1
-; RV32-NEXT: vmsne.vi v0, v28, 0
+; RV32-NEXT: vand.vi v8, v12, 1
+; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_idx_v64i1:
; RV64: # %bb.0:
; RV64-NEXT: addi a2, zero, 64
; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; RV64-NEXT: vmv.s.x v28, a0
-; RV64-NEXT: vmv.v.i v8, 0
-; RV64-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-NEXT: vmv.s.x v8, a0
+; RV64-NEXT: vmv.v.i v12, 0
+; RV64-NEXT: vmerge.vim v12, v12, 1, v0
; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, m4, tu, mu
-; RV64-NEXT: vslideup.vx v8, v28, a0
+; RV64-NEXT: vslideup.vx v12, v8, a0
; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; RV64-NEXT: vand.vi v28, v8, 1
-; RV64-NEXT: vmsne.vi v0, v28, 0
+; RV64-NEXT: vand.vi v8, v12, 1
+; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i32 %idx
ret <64 x i1> %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
index 14f8d2667d278..2f9fdafa05441 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
@@ -8,9 +8,9 @@ define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, <2 x
; CHECK-LABEL: insert_nxv8i32_v2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 0
+; CHECK-NEXT: vslideup.vi v8, v12, 0
; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0)
@@ -21,9 +21,9 @@ define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, <2 x
; CHECK-LABEL: insert_nxv8i32_v2i32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 2
+; CHECK-NEXT: vslideup.vi v8, v12, 2
; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 2)
@@ -34,9 +34,9 @@ define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, <2 x
; CHECK-LABEL: insert_nxv8i32_v2i32_6:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 8, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 6
+; CHECK-NEXT: vslideup.vi v8, v12, 6
; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6)
@@ -47,21 +47,21 @@ define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, <8 x
; LMULMAX2-LABEL: insert_nxv8i32_v8i32_0:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v28, (a0)
+; LMULMAX2-NEXT: vle32.v v12, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v8, v28, 0
+; LMULMAX2-NEXT: vslideup.vi v8, v12, 0
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v28, (a0)
-; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0)
+; LMULMAX1-NEXT: addi a0, a0, 16
+; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m4, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v8, v28, 0
+; LMULMAX1-NEXT: vslideup.vi v8, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v8, v12, 4
+; LMULMAX1-NEXT: vslideup.vi v8, v16, 4
; LMULMAX1-NEXT: ret
%sv = load <8 x i32>, <8 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0)
@@ -72,21 +72,21 @@ define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, <8 x
; LMULMAX2-LABEL: insert_nxv8i32_v8i32_8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v28, (a0)
+; LMULMAX2-NEXT: vle32.v v12, (a0)
; LMULMAX2-NEXT: vsetivli zero, 16, e32, m4, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v8, v28, 8
+; LMULMAX2-NEXT: vslideup.vi v8, v12, 8
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_nxv8i32_v8i32_8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v28, (a0)
-; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v12, (a0)
+; LMULMAX1-NEXT: addi a0, a0, 16
+; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 12, e32, m4, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v8, v28, 8
+; LMULMAX1-NEXT: vslideup.vi v8, v12, 8
; LMULMAX1-NEXT: vsetivli zero, 16, e32, m4, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v8, v12, 12
+; LMULMAX1-NEXT: vslideup.vi v8, v16, 12
; LMULMAX1-NEXT: ret
%sv = load <8 x i32>, <8 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8)
@@ -108,13 +108,13 @@ define void @insert_v4i32_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_v2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <4 x i32>, <4 x i32>* %vp
@@ -127,12 +127,12 @@ define void @insert_v4i32_v2i32_2(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_v2i32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 2
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vslideup.vi v9, v8, 2
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <4 x i32>, <4 x i32>* %vp
@@ -145,13 +145,13 @@ define void @insert_v4i32_undef_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_undef_v2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0)
@@ -163,25 +163,25 @@ define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_0:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a1)
+; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v28, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v28, v26, 0
+; LMULMAX2-NEXT: vslideup.vi v10, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vse32.v v28, (a0)
+; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v8i32_v2i32_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vse32.v v26, (a0)
+; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp
@@ -194,24 +194,24 @@ define void @insert_v8i32_v2i32_2(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_2:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a1)
+; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v28, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a0)
; LMULMAX2-NEXT: vsetivli zero, 4, e32, m2, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v28, v26, 2
+; LMULMAX2-NEXT: vslideup.vi v10, v8, 2
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vse32.v v28, (a0)
+; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v8i32_v2i32_2:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
-; LMULMAX1-NEXT: vse32.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
+; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp
@@ -224,24 +224,24 @@ define void @insert_v8i32_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_6:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a1)
+; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v28, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a0)
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m2, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v28, v26, 6
-; LMULMAX2-NEXT: vse32.v v28, (a0)
+; LMULMAX2-NEXT: vslideup.vi v10, v8, 6
+; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v8i32_v2i32_6:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
-; LMULMAX1-NEXT: vse32.v v26, (a0)
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
+; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp
@@ -254,20 +254,20 @@ define void @insert_v8i32_undef_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_undef_v2i32_6:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a1)
+; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vslideup.vi v28, v26, 6
-; LMULMAX2-NEXT: vse32.v v28, (a0)
+; LMULMAX2-NEXT: vslideup.vi v10, v8, 6
+; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v8i32_undef_v2i32_6:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a1)
+; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vslideup.vi v26, v25, 2
+; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse32.v v26, (a0)
+; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> undef, <2 x i32> %sv, i64 6)
@@ -279,13 +279,13 @@ define void @insert_v4i16_v2i16_0(<4 x i16>* %vp, <2 x i16>* %svp) {
; CHECK-LABEL: insert_v4i16_v2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v26, (a1)
+; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v25, v26, 0
+; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %vp
%sv = load <2 x i16>, <2 x i16>* %svp
@@ -298,12 +298,12 @@ define void @insert_v4i16_v2i16_2(<4 x i16>* %vp, <2 x i16>* %svp) {
; CHECK-LABEL: insert_v4i16_v2i16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v26, (a1)
+; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v25, v26, 2
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vslideup.vi v8, v9, 2
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %vp
%sv = load <2 x i16>, <2 x i16>* %svp
@@ -317,25 +317,25 @@ define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vlm.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vlm.v v26, (a1)
+; LMULMAX2-NEXT: vlm.v v9, (a1)
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v25, v26, 0
+; LMULMAX2-NEXT: vslideup.vi v8, v9, 0
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vsm.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v32i1_v8i1_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vlm.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vlm.v v26, (a1)
+; LMULMAX1-NEXT: vlm.v v9, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 0
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vsm.v v25, (a0)
+; LMULMAX1-NEXT: vsm.v v8, (a0)
; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp
@@ -349,26 +349,26 @@ define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vlm.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vlm.v v26, (a1)
+; LMULMAX2-NEXT: vlm.v v9, (a1)
; LMULMAX2-NEXT: vsetivli zero, 3, e8, mf4, tu, mu
-; LMULMAX2-NEXT: vslideup.vi v25, v26, 2
+; LMULMAX2-NEXT: vslideup.vi v8, v9, 2
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vsm.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v32i1_v8i1_16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 2
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vlm.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vlm.v v26, (a1)
+; LMULMAX1-NEXT: vlm.v v9, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v25, v26, 0
+; LMULMAX1-NEXT: vslideup.vi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vsm.v v25, (a0)
+; LMULMAX1-NEXT: vsm.v v8, (a0)
; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp
@@ -383,19 +383,19 @@ define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vlm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v27, 0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmerge.vim v25, v27, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp
@@ -410,19 +410,19 @@ define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vlm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v27, 0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmerge.vim v25, v27, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 4
+; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp
@@ -435,9 +435,9 @@ define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, <2 x i1
; CHECK-LABEL: insert_nxv2i16_v2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 0
+; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: ret
%sv = load <2 x i16>, <2 x i16>* %svp
%c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0)
@@ -448,9 +448,9 @@ define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, <2 x i1
; CHECK-LABEL: insert_nxv2i16_v2i16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 6, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 4
+; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret
%sv = load <2 x i16>, <2 x i16>* %svp
%c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4)
@@ -461,18 +461,18 @@ define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %
; CHECK-LABEL: insert_nxv2i1_v4i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v27, 0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmerge.vim v25, v27, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%sv = load <4 x i1>, <4 x i1>* %svp
%c = call <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
@@ -483,9 +483,9 @@ define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %
; CHECK-LABEL: insert_nxv8i1_v4i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vi v0, v25, 0
+; CHECK-NEXT: vslideup.vi v0, v8, 0
; CHECK-NEXT: ret
%sv = load <8 x i1>, <8 x i1>* %svp
%c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0)
@@ -496,9 +496,9 @@ define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>*
; CHECK-LABEL: insert_nxv8i1_v8i1_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vi v0, v25, 2
+; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: ret
%sv = load <8 x i1>, <8 x i1>* %svp
%c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16)
@@ -564,9 +564,9 @@ define void @insert_v2i64_nxv16i64_hi(<2 x i64>* %psv, <vscale x 16 x i64>* %out
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 80
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: addi a2, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
index 55b24cff0801f..73b0c63764d5a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
@@ -9,24 +9,24 @@ define void @insertelt_v4i64(<4 x i64>* %x, i64 %y) {
; RV32-LABEL: insertelt_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu
-; RV32-NEXT: vmv.v.i v28, 0
-; RV32-NEXT: vslide1up.vx v30, v28, a2
-; RV32-NEXT: vslide1up.vx v28, v30, a1
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vslide1up.vx v12, v10, a2
+; RV32-NEXT: vslide1up.vx v10, v12, a1
; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v28, 3
-; RV32-NEXT: vse64.v v26, (a0)
+; RV32-NEXT: vslideup.vi v8, v10, 3
+; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
-; RV64-NEXT: vmv.s.x v28, a1
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.s.x v10, a1
; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v28, 3
-; RV64-NEXT: vse64.v v26, (a0)
+; RV64-NEXT: vslideup.vi v8, v10, 3
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = insertelement <4 x i64> %a, i64 %y, i32 3
@@ -42,29 +42,29 @@ define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) {
; RV32-LABEL: insertelt_v3i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vmv.v.i v28, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu
-; RV32-NEXT: vslideup.vi v28, v26, 0
+; RV32-NEXT: vslideup.vi v10, v8, 0
; RV32-NEXT: lw a3, 16(a0)
; RV32-NEXT: addi a4, a0, 20
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vlse32.v v26, (a4), zero
+; RV32-NEXT: vlse32.v v8, (a4), zero
; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; RV32-NEXT: vmv.s.x v26, a3
+; RV32-NEXT: vmv.s.x v8, a3
; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; RV32-NEXT: vslideup.vi v28, v26, 2
+; RV32-NEXT: vslideup.vi v10, v8, 2
; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
-; RV32-NEXT: vslide1up.vx v30, v26, a2
-; RV32-NEXT: vslide1up.vx v26, v30, a1
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vslide1up.vx v12, v8, a2
+; RV32-NEXT: vslide1up.vx v8, v12, a1
; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu
-; RV32-NEXT: vslideup.vi v28, v26, 2
+; RV32-NEXT: vslideup.vi v10, v8, 2
; RV32-NEXT: sw a1, 16(a0)
; RV32-NEXT: sw a2, 20(a0)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vse64.v v28, (a0)
+; RV32-NEXT: vse64.v v10, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_v3i64:
@@ -81,12 +81,12 @@ define void @insertelt_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: insertelt_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.s.x v26, a1
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: vsetivli zero, 15, e8, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v25, v26, 14
+; CHECK-NEXT: vslideup.vi v8, v9, 14
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> %a, i8 %y, i32 14
@@ -99,27 +99,27 @@ define void @insertelt_v32i16(<32 x i16>* %x, i16 %y, i32 %idx) {
; RV32: # %bb.0:
; RV32-NEXT: addi a3, zero, 32
; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; RV32-NEXT: vle16.v v28, (a0)
-; RV32-NEXT: vmv.s.x v8, a1
+; RV32-NEXT: vle16.v v8, (a0)
+; RV32-NEXT: vmv.s.x v12, a1
; RV32-NEXT: addi a1, a2, 1
; RV32-NEXT: vsetvli zero, a1, e16, m4, tu, mu
-; RV32-NEXT: vslideup.vx v28, v8, a2
+; RV32-NEXT: vslideup.vx v8, v12, a2
; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; RV32-NEXT: vse16.v v28, (a0)
+; RV32-NEXT: vse16.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_v32i16:
; RV64: # %bb.0:
; RV64-NEXT: addi a3, zero, 32
; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; RV64-NEXT: vle16.v v28, (a0)
-; RV64-NEXT: vmv.s.x v8, a1
+; RV64-NEXT: vle16.v v8, (a0)
+; RV64-NEXT: vmv.s.x v12, a1
; RV64-NEXT: sext.w a1, a2
; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e16, m4, tu, mu
-; RV64-NEXT: vslideup.vx v28, v8, a1
+; RV64-NEXT: vslideup.vx v8, v12, a1
; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; RV64-NEXT: vse16.v v28, (a0)
+; RV64-NEXT: vse16.v v8, (a0)
; RV64-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
@@ -131,26 +131,26 @@ define void @insertelt_v8f32(<8 x float>* %x, float %y, i32 %idx) {
; RV32-LABEL: insertelt_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vle32.v v26, (a0)
-; RV32-NEXT: vfmv.s.f v28, fa0
+; RV32-NEXT: vle32.v v8, (a0)
+; RV32-NEXT: vfmv.s.f v10, fa0
; RV32-NEXT: addi a2, a1, 1
; RV32-NEXT: vsetvli zero, a2, e32, m2, tu, mu
-; RV32-NEXT: vslideup.vx v26, v28, a1
+; RV32-NEXT: vslideup.vx v8, v10, a1
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vse32.v v26, (a0)
+; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV64-NEXT: vle32.v v26, (a0)
-; RV64-NEXT: vfmv.s.f v28, fa0
+; RV64-NEXT: vle32.v v8, (a0)
+; RV64-NEXT: vfmv.s.f v10, fa0
; RV64-NEXT: sext.w a1, a1
; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e32, m2, tu, mu
-; RV64-NEXT: vslideup.vx v26, v28, a1
+; RV64-NEXT: vslideup.vx v8, v10, a1
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV64-NEXT: vse32.v v26, (a0)
+; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> %a, float %y, i32 %idx
@@ -162,11 +162,11 @@ define void @insertelt_v8i64_0(<8 x i64>* %x) {
; CHECK-LABEL: insertelt_v8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a1, zero, -1
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vmv.s.x v28, a1
-; CHECK-NEXT: vse64.v v28, (a0)
+; CHECK-NEXT: vmv.s.x v8, a1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 -1, i32 0
@@ -178,28 +178,28 @@ define void @insertelt_v8i64(<8 x i64>* %x, i32 %idx) {
; RV32-LABEL: insertelt_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a2, zero, -1
-; RV32-NEXT: vmv.s.x v8, a2
+; RV32-NEXT: vmv.s.x v12, a2
; RV32-NEXT: addi a2, a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vslideup.vx v28, v8, a1
+; RV32-NEXT: vslideup.vx v8, v12, a1
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vse64.v v28, (a0)
+; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a2, zero, -1
-; RV64-NEXT: vmv.s.x v8, a2
+; RV64-NEXT: vmv.s.x v12, a2
; RV64-NEXT: sext.w a1, a1
; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV64-NEXT: vslideup.vx v28, v8, a1
+; RV64-NEXT: vslideup.vx v8, v12, a1
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vse64.v v28, (a0)
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 -1, i32 %idx
@@ -211,11 +211,11 @@ define void @insertelt_c6_v8i64_0(<8 x i64>* %x) {
; CHECK-LABEL: insertelt_c6_v8i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a1, zero, 6
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vmv.s.x v28, a1
-; CHECK-NEXT: vse64.v v28, (a0)
+; CHECK-NEXT: vmv.s.x v8, a1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 6, i32 0
@@ -227,28 +227,28 @@ define void @insertelt_c6_v8i64(<8 x i64>* %x, i32 %idx) {
; RV32-LABEL: insertelt_c6_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a2, zero, 6
-; RV32-NEXT: vmv.s.x v8, a2
+; RV32-NEXT: vmv.s.x v12, a2
; RV32-NEXT: addi a2, a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vslideup.vx v28, v8, a1
+; RV32-NEXT: vslideup.vx v8, v12, a1
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vse64.v v28, (a0)
+; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: insertelt_c6_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a2, zero, 6
-; RV64-NEXT: vmv.s.x v8, a2
+; RV64-NEXT: vmv.s.x v12, a2
; RV64-NEXT: sext.w a1, a1
; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV64-NEXT: vslideup.vx v28, v8, a1
+; RV64-NEXT: vslideup.vx v8, v12, a1
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vse64.v v28, (a0)
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 6, i32 %idx
@@ -262,14 +262,14 @@ define void @insertelt_c6_v8i64_0_add(<8 x i64>* %x, <8 x i64>* %y) {
; CHECK-LABEL: insertelt_c6_v8i64_0_add:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a2, zero, 6
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vmv.s.x v28, a2
+; CHECK-NEXT: vmv.s.x v8, a2
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v8, (a1)
-; CHECK-NEXT: vadd.vv v28, v28, v8
-; CHECK-NEXT: vse64.v v28, (a0)
+; CHECK-NEXT: vle64.v v12, (a1)
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 6, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 714a2afdf58c7..75e5ac705ca1c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -6,8 +6,8 @@ define void @buildvec_vid_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: buildvec_vid_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8>* %x
ret void
@@ -17,8 +17,8 @@ define void @buildvec_vid_undefelts_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: buildvec_vid_undefelts_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <16 x i8> <i8 0, i8 1, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8>* %x
ret void
@@ -31,8 +31,8 @@ define void @buildvec_notquite_vid_v16i8(<16 x i8>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI2_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI2_0)
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <16 x i8> <i8 0, i8 1, i8 3, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8>* %x
ret void
@@ -42,9 +42,9 @@ define void @buildvec_vid_plus_imm_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: buildvec_vid_plus_imm_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vadd.vi v25, v25, 2
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vi v8, v8, 2
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <16 x i8> <i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17>, <16 x i8>* %x
ret void
@@ -54,10 +54,10 @@ define void @buildvec_vid_mpy_imm_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: buildvec_vid_mpy_imm_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vid.v v25
+; CHECK-NEXT: vid.v v8
; CHECK-NEXT: addi a1, zero, 3
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <16 x i8> <i8 0, i8 3, i8 6, i8 9, i8 12, i8 15, i8 18, i8 21, i8 24, i8 27, i8 30, i8 33, i8 36, i8 39, i8 42, i8 45>, <16 x i8>* %x
ret void
@@ -67,12 +67,12 @@ define void @buildvec_vid_step2_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>
; CHECK-LABEL: buildvec_vid_step2_add0_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vadd.vv v25, v25, v25
-; CHECK-NEXT: vse8.v v25, (a0)
-; CHECK-NEXT: vse8.v v25, (a1)
-; CHECK-NEXT: vse8.v v25, (a2)
-; CHECK-NEXT: vse8.v v25, (a3)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: vse8.v v8, (a1)
+; CHECK-NEXT: vse8.v v8, (a2)
+; CHECK-NEXT: vse8.v v8, (a3)
; CHECK-NEXT: ret
store <4 x i8> <i8 0, i8 2, i8 4, i8 6>, <4 x i8>* %z0
store <4 x i8> <i8 undef, i8 2, i8 4, i8 6>, <4 x i8>* %z1
@@ -85,13 +85,13 @@ define void @buildvec_vid_step2_add1_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>
; CHECK-LABEL: buildvec_vid_step2_add1_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vadd.vv v25, v25, v25
-; CHECK-NEXT: vadd.vi v25, v25, 1
-; CHECK-NEXT: vse8.v v25, (a0)
-; CHECK-NEXT: vse8.v v25, (a1)
-; CHECK-NEXT: vse8.v v25, (a2)
-; CHECK-NEXT: vse8.v v25, (a3)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vadd.vi v8, v8, 1
+; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: vse8.v v8, (a1)
+; CHECK-NEXT: vse8.v v8, (a2)
+; CHECK-NEXT: vse8.v v8, (a3)
; CHECK-NEXT: ret
store <4 x i8> <i8 1, i8 3, i8 5, i8 7>, <4 x i8>* %z0
store <4 x i8> <i8 undef, i8 3, i8 5, i8 7>, <4 x i8>* %z1
@@ -107,12 +107,12 @@ define void @buildvec_vid_stepn1_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x
; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
-; CHECK-NEXT: vse8.v v25, (a1)
-; CHECK-NEXT: vse8.v v25, (a2)
-; CHECK-NEXT: vse8.v v25, (a3)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vrsub.vi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: vse8.v v8, (a1)
+; CHECK-NEXT: vse8.v v8, (a2)
+; CHECK-NEXT: vse8.v v8, (a3)
; CHECK-NEXT: ret
i8>* %z2, <4 x i8>* %z3) {
store <4 x i8> <i8 0, i8 -1, i8 -2, i8 -3>, <4 x i8>* %z0
@@ -126,13 +126,13 @@ define void @buildvec_vid_stepn2_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8
; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vadd.vv v25, v25, v25
-; CHECK-NEXT: vrsub.vi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
-; CHECK-NEXT: vse8.v v25, (a1)
-; CHECK-NEXT: vse8.v v25, (a2)
-; CHECK-NEXT: vse8.v v25, (a3)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vrsub.vi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: vse8.v v8, (a1)
+; CHECK-NEXT: vse8.v v8, (a2)
+; CHECK-NEXT: vse8.v v8, (a3)
; CHECK-NEXT: ret
store <4 x i8> <i8 0, i8 -2, i8 -4, i8 -6>, <4 x i8>* %z0
store <4 x i8> <i8 undef, i8 -2, i8 -4, i8 -6>, <4 x i8>* %z1
@@ -145,10 +145,10 @@ define void @buildvec_vid_stepn2_add3_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8
; CHECK-LABEL: buildvec_vid_stepn2_add3_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vadd.vv v25, v25, v25
-; CHECK-NEXT: vrsub.vi v25, v25, 3
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vrsub.vi v8, v8, 3
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <4 x i8> <i8 3, i8 1, i8 -1, i8 -3>, <4 x i8>* %z0
ret void
@@ -158,11 +158,11 @@ define void @buildvec_vid_stepn3_add3_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8
; CHECK-LABEL: buildvec_vid_stepn3_add3_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 3
-; CHECK-NEXT: vid.v v26
+; CHECK-NEXT: vmv.v.i v8, 3
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: addi a1, zero, -3
-; CHECK-NEXT: vmadd.vx v26, a1, v25
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vmadd.vx v9, a1, v8
+; CHECK-NEXT: vse8.v v9, (a0)
; CHECK-NEXT: ret
store <4 x i8> <i8 3, i8 0, i8 -3, i8 -6>, <4 x i8>* %z0
ret void
@@ -172,14 +172,14 @@ define void @buildvec_vid_stepn3_addn3_v4i32(<4 x i32>* %z0, <4 x i32>* %z1, <4
; CHECK-LABEL: buildvec_vid_stepn3_addn3_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -3
-; CHECK-NEXT: vid.v v26
+; CHECK-NEXT: vmv.v.i v8, -3
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: addi a4, zero, -3
-; CHECK-NEXT: vmadd.vx v26, a4, v25
-; CHECK-NEXT: vse32.v v26, (a0)
-; CHECK-NEXT: vse32.v v26, (a1)
-; CHECK-NEXT: vse32.v v26, (a2)
-; CHECK-NEXT: vse32.v v26, (a3)
+; CHECK-NEXT: vmadd.vx v9, a4, v8
+; CHECK-NEXT: vse32.v v9, (a0)
+; CHECK-NEXT: vse32.v v9, (a1)
+; CHECK-NEXT: vse32.v v9, (a2)
+; CHECK-NEXT: vse32.v v9, (a3)
; CHECK-NEXT: ret
store <4 x i32> <i32 -3, i32 -6, i32 -9, i32 -12>, <4 x i32>* %z0
store <4 x i32> <i32 undef, i32 -6, i32 -9, i32 -12>, <4 x i32>* %z1
@@ -194,10 +194,10 @@ define <4 x i64> @buildvec_vid_step1_add0_v4i64() {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
+; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; RV32-NEXT: vslideup.vi v8, v25, 2
+; RV32-NEXT: vslideup.vi v8, v9, 2
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
@@ -218,10 +218,10 @@ define <4 x i64> @buildvec_vid_step2_add0_v4i64() {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 2
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
+; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; RV32-NEXT: vslideup.vi v8, v25, 2
+; RV32-NEXT: vslideup.vi v8, v9, 2
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
@@ -231,8 +231,8 @@ define <4 x i64> @buildvec_vid_step2_add0_v4i64() {
; RV64-LABEL: buildvec_vid_step2_add0_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vid.v v25
-; RV64-NEXT: vadd.vv v8, v25, v25
+; RV64-NEXT: vid.v v8
+; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vadd.vi v9, v8, 4
; RV64-NEXT: ret
ret <4 x i64> <i64 0, i64 2, i64 4, i64 6>
@@ -244,29 +244,29 @@ define void @buildvec_no_vid_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <
; RV32-NEXT: lui a6, %hi(.LCPI14_0)
; RV32-NEXT: addi a6, a6, %lo(.LCPI14_0)
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV32-NEXT: vle8.v v25, (a6)
+; RV32-NEXT: vle8.v v8, (a6)
; RV32-NEXT: lui a6, %hi(.LCPI14_1)
; RV32-NEXT: addi a6, a6, %lo(.LCPI14_1)
-; RV32-NEXT: vle8.v v26, (a6)
-; RV32-NEXT: vse8.v v25, (a0)
-; RV32-NEXT: vse8.v v26, (a1)
+; RV32-NEXT: vle8.v v9, (a6)
+; RV32-NEXT: vse8.v v8, (a0)
+; RV32-NEXT: vse8.v v9, (a1)
; RV32-NEXT: lui a0, 1
; RV32-NEXT: addi a0, a0, -2048
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v8, a0
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV32-NEXT: vse8.v v25, (a2)
+; RV32-NEXT: vse8.v v8, (a2)
; RV32-NEXT: addi a0, zero, 2047
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v8, a0
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV32-NEXT: lui a0, %hi(.LCPI14_2)
; RV32-NEXT: addi a0, a0, %lo(.LCPI14_2)
-; RV32-NEXT: vle8.v v26, (a0)
-; RV32-NEXT: vse8.v v25, (a3)
-; RV32-NEXT: vmv.v.i v25, -2
-; RV32-NEXT: vse8.v v25, (a4)
-; RV32-NEXT: vse8.v v26, (a5)
+; RV32-NEXT: vle8.v v9, (a0)
+; RV32-NEXT: vse8.v v8, (a3)
+; RV32-NEXT: vmv.v.i v8, -2
+; RV32-NEXT: vse8.v v8, (a4)
+; RV32-NEXT: vse8.v v9, (a5)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_no_vid_v4i8:
@@ -274,29 +274,29 @@ define void @buildvec_no_vid_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <
; RV64-NEXT: lui a6, %hi(.LCPI14_0)
; RV64-NEXT: addi a6, a6, %lo(.LCPI14_0)
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV64-NEXT: vle8.v v25, (a6)
+; RV64-NEXT: vle8.v v8, (a6)
; RV64-NEXT: lui a6, %hi(.LCPI14_1)
; RV64-NEXT: addi a6, a6, %lo(.LCPI14_1)
-; RV64-NEXT: vle8.v v26, (a6)
-; RV64-NEXT: vse8.v v25, (a0)
-; RV64-NEXT: vse8.v v26, (a1)
+; RV64-NEXT: vle8.v v9, (a6)
+; RV64-NEXT: vse8.v v8, (a0)
+; RV64-NEXT: vse8.v v9, (a1)
; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -2048
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV64-NEXT: vse8.v v25, (a2)
+; RV64-NEXT: vse8.v v8, (a2)
; RV64-NEXT: addi a0, zero, 2047
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV64-NEXT: lui a0, %hi(.LCPI14_2)
; RV64-NEXT: addi a0, a0, %lo(.LCPI14_2)
-; RV64-NEXT: vle8.v v26, (a0)
-; RV64-NEXT: vse8.v v25, (a3)
-; RV64-NEXT: vmv.v.i v25, -2
-; RV64-NEXT: vse8.v v25, (a4)
-; RV64-NEXT: vse8.v v26, (a5)
+; RV64-NEXT: vle8.v v9, (a0)
+; RV64-NEXT: vse8.v v8, (a3)
+; RV64-NEXT: vmv.v.i v8, -2
+; RV64-NEXT: vse8.v v8, (a4)
+; RV64-NEXT: vse8.v v9, (a5)
; RV64-NEXT: ret
store <4 x i8> <i8 1, i8 3, i8 6, i8 7>, <4 x i8>* %z0
store <4 x i8> <i8 undef, i8 2, i8 5, i8 7>, <4 x i8>* %z1
@@ -311,12 +311,12 @@ define void @buildvec_dominant0_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: buildvec_dominant0_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, zero
-; CHECK-NEXT: vmv.v.i v26, 8
+; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: vmv.v.i v9, 8
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 3
+; CHECK-NEXT: vslideup.vi v9, v8, 3
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
store <8 x i16> <i16 8, i16 8, i16 undef, i16 0, i16 8, i16 undef, i16 8, i16 8>, <8 x i16>* %x
ret void
@@ -326,8 +326,8 @@ define void @buildvec_dominant1_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: buildvec_dominant1_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 8
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 8
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
store <8 x i16> <i16 undef, i16 8, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, <8 x i16>* %x
ret void
@@ -345,8 +345,8 @@ define void @buildvec_dominant1_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: buildvec_dominant1_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, -1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <2 x i8> <i8 undef, i8 -1>, <2 x i8>* %x
ret void
@@ -356,9 +356,9 @@ define void @buildvec_dominant2_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: buildvec_dominant2_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vrsub.vi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <2 x i8> <i8 0, i8 -1>, <2 x i8>* %x
ret void
@@ -370,14 +370,14 @@ define void @buildvec_dominant0_v2i32(<2 x i64>* %x) {
; RV32-NEXT: lui a1, %hi(.LCPI20_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI20_0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v25, (a1)
-; RV32-NEXT: vse32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a1)
+; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_dominant0_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v8, -1
; RV64-NEXT: lui a1, 3641
; RV64-NEXT: addiw a1, a1, -455
; RV64-NEXT: slli a1, a1, 12
@@ -387,8 +387,8 @@ define void @buildvec_dominant0_v2i32(<2 x i64>* %x) {
; RV64-NEXT: slli a1, a1, 13
; RV64-NEXT: addi a1, a1, -910
; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; RV64-NEXT: vmv.s.x v25, a1
-; RV64-NEXT: vse64.v v25, (a0)
+; RV64-NEXT: vmv.s.x v8, a1
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x
ret void
@@ -400,8 +400,8 @@ define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize {
; RV32-NEXT: lui a1, %hi(.LCPI21_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI21_0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v25, (a1)
-; RV32-NEXT: vse32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a1)
+; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_dominant1_optsize_v2i32:
@@ -409,8 +409,8 @@ define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize {
; RV64-NEXT: lui a1, %hi(.LCPI21_0)
; RV64-NEXT: addi a1, a1, %lo(.LCPI21_0)
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a1)
-; RV64-NEXT: vse64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a1)
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x
ret void
@@ -421,9 +421,9 @@ define void @buildvec_seq_v8i8_v4i16(<8 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 513
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <8 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 undef, i8 2>, <8 x i8>* %x
ret void
@@ -435,9 +435,9 @@ define void @buildvec_seq_v8i8_v2i32(<8 x i8>* %x) {
; RV32-NEXT: lui a1, 48
; RV32-NEXT: addi a1, a1, 513
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vmv.v.x v25, a1
+; RV32-NEXT: vmv.v.x v8, a1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vse8.v v25, (a0)
+; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_seq_v8i8_v2i32:
@@ -445,9 +445,9 @@ define void @buildvec_seq_v8i8_v2i32(<8 x i8>* %x) {
; RV64-NEXT: lui a1, 48
; RV64-NEXT: addiw a1, a1, 513
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vmv.v.x v25, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vse8.v v25, (a0)
+; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: ret
store <8 x i8> <i8 1, i8 2, i8 3, i8 undef, i8 1, i8 2, i8 3, i8 undef>, <8 x i8>* %x
ret void
@@ -459,8 +459,8 @@ define void @buildvec_seq_v16i8_v2i64(<16 x i8>* %x) {
; RV32-NEXT: lui a1, %hi(.LCPI24_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI24_0)
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vle8.v v25, (a1)
-; RV32-NEXT: vse8.v v25, (a0)
+; RV32-NEXT: vle8.v v8, (a1)
+; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_seq_v16i8_v2i64:
@@ -472,9 +472,9 @@ define void @buildvec_seq_v16i8_v2i64(<16 x i8>* %x) {
; RV64-NEXT: slli a1, a1, 16
; RV64-NEXT: addi a1, a1, 513
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vse8.v v25, (a0)
+; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: ret
store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>* %x
ret void
@@ -486,9 +486,9 @@ define void @buildvec_seq2_v16i8_v2i64(<16 x i8>* %x) {
; RV32-NEXT: lui a1, 528432
; RV32-NEXT: addi a1, a1, 513
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a1
+; RV32-NEXT: vmv.v.x v8, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vse8.v v25, (a0)
+; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_seq2_v16i8_v2i64:
@@ -496,9 +496,9 @@ define void @buildvec_seq2_v16i8_v2i64(<16 x i8>* %x) {
; RV64-NEXT: lui a1, 528432
; RV64-NEXT: addiw a1, a1, 513
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a1
+; RV64-NEXT: vmv.v.x v8, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vse8.v v25, (a0)
+; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: ret
store <16 x i8> <i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1, i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* %x
ret void
@@ -513,14 +513,14 @@ define void @buildvec_seq_v9i8(<9 x i8>* %x) {
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v25, 2
-; RV32-NEXT: vmerge.vim v25, v25, 1, v0
+; RV32-NEXT: vmv.v.i v8, 2
+; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: addi a1, zero, 36
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmerge.vim v25, v25, 3, v0
-; RV32-NEXT: vse8.v v25, (a0)
+; RV32-NEXT: vmerge.vim v8, v8, 3, v0
+; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: buildvec_seq_v9i8:
@@ -544,9 +544,9 @@ define void @buildvec_seq_v4i16_v2i32(<4 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, -127
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
store <4 x i16> <i16 -127, i16 -1, i16 -127, i16 -1>, <4 x i16>* %x
ret void
@@ -556,25 +556,25 @@ define void @buildvec_vid_step1o2_v4i32(<4 x i32>* %z0, <4 x i32>* %z1, <4 x i32
; CHECK-LABEL: buildvec_vid_step1o2_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vsrl.vi v25, v25, 1
-; CHECK-NEXT: vse32.v v25, (a0)
-; CHECK-NEXT: vse32.v v25, (a1)
-; CHECK-NEXT: vse32.v v25, (a2)
-; CHECK-NEXT: vse32.v v25, (a3)
-; CHECK-NEXT: vse32.v v25, (a4)
-; CHECK-NEXT: vmv.s.x v25, zero
-; CHECK-NEXT: vmv.v.i v26, 1
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: vse32.v v8, (a0)
+; CHECK-NEXT: vse32.v v8, (a1)
+; CHECK-NEXT: vse32.v v8, (a2)
+; CHECK-NEXT: vse32.v v8, (a3)
+; CHECK-NEXT: vse32.v v8, (a4)
+; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: vmv.v.i v9, 1
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 1
+; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vse32.v v26, (a5)
+; CHECK-NEXT: vse32.v v9, (a5)
; CHECK-NEXT: addi a0, zero, 1
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 3
-; CHECK-NEXT: vse32.v v26, (a6)
+; CHECK-NEXT: vslideup.vi v9, v8, 3
+; CHECK-NEXT: vse32.v v9, (a6)
; CHECK-NEXT: ret
store <4 x i32> <i32 0, i32 0, i32 1, i32 1>, <4 x i32>* %z0
store <4 x i32> <i32 0, i32 0, i32 1, i32 undef>, <4 x i32>* %z1
@@ -592,27 +592,27 @@ define void @buildvec_vid_step1o2_add3_v4i16(<4 x i16>* %z0, <4 x i16>* %z1, <4
; CHECK-LABEL: buildvec_vid_step1o2_add3_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vsrl.vi v25, v25, 1
-; CHECK-NEXT: vadd.vi v25, v25, 3
-; CHECK-NEXT: vse16.v v25, (a0)
-; CHECK-NEXT: vse16.v v25, (a1)
-; CHECK-NEXT: vse16.v v25, (a2)
-; CHECK-NEXT: vse16.v v25, (a3)
-; CHECK-NEXT: vse16.v v25, (a4)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: vadd.vi v8, v8, 3
+; CHECK-NEXT: vse16.v v8, (a0)
+; CHECK-NEXT: vse16.v v8, (a1)
+; CHECK-NEXT: vse16.v v8, (a2)
+; CHECK-NEXT: vse16.v v8, (a3)
+; CHECK-NEXT: vse16.v v8, (a4)
; CHECK-NEXT: addi a0, zero, 3
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 4
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 1
+; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vse16.v v26, (a5)
+; CHECK-NEXT: vse16.v v9, (a5)
; CHECK-NEXT: addi a0, zero, 4
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 3
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 3
-; CHECK-NEXT: vse16.v v26, (a6)
+; CHECK-NEXT: vslideup.vi v9, v8, 3
+; CHECK-NEXT: vse16.v v9, (a6)
; CHECK-NEXT: ret
store <4 x i16> <i16 3, i16 3, i16 4, i16 4>, <4 x i16>* %z0
store <4 x i16> <i16 3, i16 3, i16 4, i16 undef>, <4 x i16>* %z1
@@ -630,10 +630,10 @@ define void @buildvec_vid_stepn1o4_addn5_v8i8(<8 x i8>* %z0) {
; CHECK-LABEL: buildvec_vid_stepn1o4_addn5_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vsrl.vi v25, v25, 2
-; CHECK-NEXT: vrsub.vi v25, v25, -5
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsrl.vi v8, v8, 2
+; CHECK-NEXT: vrsub.vi v8, v8, -5
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <8 x i8> <i8 -5, i8 -5, i8 -5, i8 -5, i8 -6, i8 -6, i8 -6, i8 -6>, <8 x i8>* %z0
ret void
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
index 9b2e93cee0c58..04a1467480915 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
@@ -10,10 +10,10 @@ define void @sext_v4i8_v4i32(<4 x i8>* %x, <4 x i32>* %z) {
; CHECK-LABEL: sext_v4i8_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v25
-; CHECK-NEXT: vse32.v v26, (a1)
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vse32.v v9, (a1)
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = sext <4 x i8> %a to <4 x i32>
@@ -25,10 +25,10 @@ define void @zext_v4i8_v4i32(<4 x i8>* %x, <4 x i32>* %z) {
; CHECK-LABEL: zext_v4i8_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v25
-; CHECK-NEXT: vse32.v v26, (a1)
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vse32.v v9, (a1)
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = zext <4 x i8> %a to <4 x i32>
@@ -40,33 +40,33 @@ define void @sext_v8i8_v8i32(<8 x i8>* %x, <8 x i32>* %z) {
; LMULMAX8-LABEL: sext_v8i8_v8i32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX8-NEXT: vle8.v v25, (a0)
+; LMULMAX8-NEXT: vle8.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX8-NEXT: vsext.vf4 v26, v25
-; LMULMAX8-NEXT: vse32.v v26, (a1)
+; LMULMAX8-NEXT: vsext.vf4 v10, v8
+; LMULMAX8-NEXT: vse32.v v10, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: sext_v8i8_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vle8.v v25, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; LMULMAX2-NEXT: vsext.vf4 v26, v25
-; LMULMAX2-NEXT: vse32.v v26, (a1)
+; LMULMAX2-NEXT: vsext.vf4 v10, v8
+; LMULMAX2-NEXT: vse32.v v10, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: sext_v8i8_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vle8.v v25, (a0)
+; LMULMAX1-NEXT: vle8.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v9, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v27, v26
-; LMULMAX1-NEXT: vsext.vf4 v26, v25
+; LMULMAX1-NEXT: vsext.vf4 v10, v9
+; LMULMAX1-NEXT: vsext.vf4 v9, v8
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse32.v v27, (a0)
-; LMULMAX1-NEXT: vse32.v v26, (a1)
+; LMULMAX1-NEXT: vse32.v v10, (a0)
+; LMULMAX1-NEXT: vse32.v v9, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = sext <8 x i8> %a to <8 x i32>
@@ -79,83 +79,83 @@ define void @sext_v32i8_v32i32(<32 x i8>* %x, <32 x i32>* %z) {
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a2, zero, 32
; LMULMAX8-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX8-NEXT: vle8.v v26, (a0)
+; LMULMAX8-NEXT: vle8.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; LMULMAX8-NEXT: vsext.vf4 v8, v26
-; LMULMAX8-NEXT: vse32.v v8, (a1)
+; LMULMAX8-NEXT: vsext.vf4 v16, v8
+; LMULMAX8-NEXT: vse32.v v16, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: sext_v32i8_v32i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v25, v26, 8
+; LMULMAX2-NEXT: vslidedown.vi v10, v8, 8
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vsext.vf4 v28, v25
+; LMULMAX2-NEXT: vsext.vf4 v12, v10
; LMULMAX2-NEXT: vsetivli zero, 16, e8, m2, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v30, v26, 16
+; LMULMAX2-NEXT: vslidedown.vi v10, v8, 16
; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX2-NEXT: vslidedown.vi v25, v30, 8
+; LMULMAX2-NEXT: vslidedown.vi v14, v10, 8
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vsext.vf4 v8, v25
-; LMULMAX2-NEXT: vsext.vf4 v10, v26
-; LMULMAX2-NEXT: vsext.vf4 v26, v30
+; LMULMAX2-NEXT: vsext.vf4 v16, v14
+; LMULMAX2-NEXT: vsext.vf4 v14, v8
+; LMULMAX2-NEXT: vsext.vf4 v8, v10
; LMULMAX2-NEXT: addi a0, a1, 64
-; LMULMAX2-NEXT: vse32.v v26, (a0)
-; LMULMAX2-NEXT: vse32.v v10, (a1)
-; LMULMAX2-NEXT: addi a0, a1, 96
; LMULMAX2-NEXT: vse32.v v8, (a0)
+; LMULMAX2-NEXT: vse32.v v14, (a1)
+; LMULMAX2-NEXT: addi a0, a1, 96
+; LMULMAX2-NEXT: vse32.v v16, (a0)
; LMULMAX2-NEXT: addi a0, a1, 32
-; LMULMAX2-NEXT: vse32.v v28, (a0)
+; LMULMAX2-NEXT: vse32.v v12, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: sext_v32i8_v32i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle8.v v25, (a2)
-; LMULMAX1-NEXT: vle8.v v26, (a0)
+; LMULMAX1-NEXT: vle8.v v8, (a2)
+; LMULMAX1-NEXT: vle8.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4
+; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v28, v27
+; LMULMAX1-NEXT: vsext.vf4 v11, v10
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v27, v25, 8
+; LMULMAX1-NEXT: vslidedown.vi v10, v8, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v27, 4
+; LMULMAX1-NEXT: vslidedown.vi v12, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v30, v29
+; LMULMAX1-NEXT: vsext.vf4 v13, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v26, 4
+; LMULMAX1-NEXT: vslidedown.vi v12, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v31, v29
+; LMULMAX1-NEXT: vsext.vf4 v14, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v29, v26, 8
+; LMULMAX1-NEXT: vslidedown.vi v12, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vslidedown.vi v8, v29, 4
+; LMULMAX1-NEXT: vslidedown.vi v15, v12, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vsext.vf4 v9, v8
-; LMULMAX1-NEXT: vsext.vf4 v8, v27
-; LMULMAX1-NEXT: vsext.vf4 v27, v29
-; LMULMAX1-NEXT: vsext.vf4 v29, v25
-; LMULMAX1-NEXT: vsext.vf4 v25, v26
+; LMULMAX1-NEXT: vsext.vf4 v16, v15
+; LMULMAX1-NEXT: vsext.vf4 v15, v10
+; LMULMAX1-NEXT: vsext.vf4 v10, v12
+; LMULMAX1-NEXT: vsext.vf4 v12, v8
+; LMULMAX1-NEXT: vsext.vf4 v8, v9
; LMULMAX1-NEXT: addi a0, a1, 32
-; LMULMAX1-NEXT: vse32.v v27, (a0)
-; LMULMAX1-NEXT: vse32.v v25, (a1)
+; LMULMAX1-NEXT: vse32.v v10, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a1, 96
-; LMULMAX1-NEXT: vse32.v v8, (a0)
+; LMULMAX1-NEXT: vse32.v v15, (a0)
; LMULMAX1-NEXT: addi a0, a1, 64
-; LMULMAX1-NEXT: vse32.v v29, (a0)
+; LMULMAX1-NEXT: vse32.v v12, (a0)
; LMULMAX1-NEXT: addi a0, a1, 48
-; LMULMAX1-NEXT: vse32.v v9, (a0)
+; LMULMAX1-NEXT: vse32.v v16, (a0)
; LMULMAX1-NEXT: addi a0, a1, 16
-; LMULMAX1-NEXT: vse32.v v31, (a0)
+; LMULMAX1-NEXT: vse32.v v14, (a0)
; LMULMAX1-NEXT: addi a0, a1, 112
-; LMULMAX1-NEXT: vse32.v v30, (a0)
+; LMULMAX1-NEXT: vse32.v v13, (a0)
; LMULMAX1-NEXT: addi a0, a1, 80
-; LMULMAX1-NEXT: vse32.v v28, (a0)
+; LMULMAX1-NEXT: vse32.v v11, (a0)
; LMULMAX1-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = sext <32 x i8> %a to <32 x i32>
@@ -167,12 +167,12 @@ define void @trunc_v4i8_v4i32(<4 x i32>* %x, <4 x i8>* %z) {
; CHECK-LABEL: trunc_v4i8_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
-; CHECK-NEXT: vse8.v v25, (a1)
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = trunc <4 x i32> %a to <4 x i8>
@@ -184,46 +184,46 @@ define void @trunc_v8i8_v8i32(<8 x i32>* %x, <8 x i8>* %z) {
; LMULMAX8-LABEL: trunc_v8i8_v8i32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vle32.v v26, (a0)
+; LMULMAX8-NEXT: vle32.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX8-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX8-NEXT: vse8.v v25, (a1)
+; LMULMAX8-NEXT: vnsrl.wi v8, v10, 0
+; LMULMAX8-NEXT: vse8.v v8, (a1)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: trunc_v8i8_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX2-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX2-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX2-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vnsrl.wi v25, v25, 0
-; LMULMAX2-NEXT: vse8.v v25, (a1)
+; LMULMAX2-NEXT: vnsrl.wi v8, v10, 0
+; LMULMAX2-NEXT: vse8.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: trunc_v8i8_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vle32.v v25, (a0)
+; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vle32.v v26, (a0)
+; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 0
+; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 0
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0
+; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; LMULMAX1-NEXT: vslideup.vi v27, v25, 4
-; LMULMAX1-NEXT: vse8.v v27, (a1)
+; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
+; LMULMAX1-NEXT: vse8.v v10, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = trunc <8 x i32> %a to <8 x i8>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
index 6ad98d1b1f534..254ff627d054c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
@@ -10,12 +10,12 @@ define void @seteq_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: seteq_vv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmseq.vv v0, v25, v26
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmseq.vv v0, v8, v9
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -30,12 +30,12 @@ define void @setne_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vle8.v v28, (a1)
-; CHECK-NEXT: vmsne.vv v0, v26, v28
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT: vse8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vmsne.vv v0, v8, v10
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -50,10 +50,10 @@ define void @setgt_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vle8.v v8, (a1)
-; CHECK-NEXT: vmslt.vv v25, v8, v28
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v12, (a1)
+; CHECK-NEXT: vmslt.vv v16, v12, v8
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -69,8 +69,8 @@ define void @setlt_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v16, (a1)
-; CHECK-NEXT: vmslt.vv v25, v8, v16
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmslt.vv v24, v8, v16
+; CHECK-NEXT: vsm.v v24, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = load <128 x i8>, <128 x i8>* %y
@@ -83,10 +83,10 @@ define void @setge_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
; CHECK-LABEL: setge_vv_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmsle.vv v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -99,10 +99,10 @@ define void @setle_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y, <16 x i1>* %z) {
; CHECK-LABEL: setle_vv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmsle.vv v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -116,10 +116,10 @@ define void @setugt_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vle8.v v28, (a1)
-; CHECK-NEXT: vmsltu.vv v25, v28, v26
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vmsltu.vv v12, v10, v8
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -133,10 +133,10 @@ define void @setult_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vle8.v v8, (a1)
-; CHECK-NEXT: vmsltu.vv v25, v28, v8
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v12, (a1)
+; CHECK-NEXT: vmsltu.vv v16, v8, v12
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -152,8 +152,8 @@ define void @setuge_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v16, (a1)
-; CHECK-NEXT: vmsleu.vv v25, v16, v8
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsleu.vv v24, v16, v8
+; CHECK-NEXT: vsm.v v24, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = load <128 x i8>, <128 x i8>* %y
@@ -166,10 +166,10 @@ define void @setule_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
; CHECK-LABEL: setule_vv_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmsleu.vv v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -182,9 +182,9 @@ define void @seteq_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-LABEL: seteq_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vx v25, v25, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vx v8, v8, a1
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -199,9 +199,9 @@ define void @setne_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmsne.vx v25, v26, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsne.vx v10, v8, a1
+; CHECK-NEXT: vsm.v v10, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -216,9 +216,9 @@ define void @setgt_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmsgt.vx v25, v28, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsgt.vx v12, v8, a1
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -234,8 +234,8 @@ define void @setlt_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: addi a3, zero, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vmslt.vx v25, v8, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmslt.vx v16, v8, a1
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -249,10 +249,10 @@ define void @setge_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-LABEL: setge_vx_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.v.x v26, a1
-; CHECK-NEXT: vmsle.vv v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.v.x v9, a1
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -266,9 +266,9 @@ define void @setle_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-LABEL: setle_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmsle.vx v25, v25, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsle.vx v8, v8, a1
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -283,9 +283,9 @@ define void @setugt_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmsgtu.vx v25, v26, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsgtu.vx v10, v8, a1
+; CHECK-NEXT: vsm.v v10, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -300,9 +300,9 @@ define void @setult_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmsltu.vx v25, v28, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsltu.vx v12, v8, a1
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -319,8 +319,8 @@ define void @setuge_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.x v16, a1
-; CHECK-NEXT: vmsleu.vv v25, v16, v8
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsleu.vv v24, v16, v8
+; CHECK-NEXT: vsm.v v24, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -334,9 +334,9 @@ define void @setule_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-LABEL: setule_vx_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmsleu.vx v25, v25, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsleu.vx v8, v8, a1
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -350,9 +350,9 @@ define void @seteq_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-LABEL: seteq_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vx v25, v25, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vx v8, v8, a1
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -367,9 +367,9 @@ define void @setne_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmsne.vx v25, v26, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsne.vx v10, v8, a1
+; CHECK-NEXT: vsm.v v10, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -384,9 +384,9 @@ define void @setgt_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmslt.vx v25, v28, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmslt.vx v12, v8, a1
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -402,8 +402,8 @@ define void @setlt_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: addi a3, zero, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vmsgt.vx v25, v8, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsgt.vx v16, v8, a1
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -417,9 +417,9 @@ define void @setge_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-LABEL: setge_xv_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmsle.vx v25, v25, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsle.vx v8, v8, a1
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -433,10 +433,10 @@ define void @setle_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-LABEL: setle_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.v.x v26, a1
-; CHECK-NEXT: vmsle.vv v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.v.x v9, a1
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -451,9 +451,9 @@ define void @setugt_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmsltu.vx v25, v26, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsltu.vx v10, v8, a1
+; CHECK-NEXT: vsm.v v10, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -468,9 +468,9 @@ define void @setult_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmsgtu.vx v25, v28, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsgtu.vx v12, v8, a1
+; CHECK-NEXT: vsm.v v12, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -486,8 +486,8 @@ define void @setuge_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: addi a3, zero, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vmsleu.vx v25, v8, a1
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vmsleu.vx v16, v8, a1
+; CHECK-NEXT: vsm.v v16, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -501,10 +501,10 @@ define void @setule_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-LABEL: setule_xv_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.v.x v26, a1
-; CHECK-NEXT: vmsleu.vv v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.v.x v9, a1
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -518,9 +518,9 @@ define void @seteq_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
; CHECK-LABEL: seteq_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmseq.vi v25, v25, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmseq.vi v8, v8, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 0, i32 0
@@ -535,9 +535,9 @@ define void @setne_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsne.vi v10, v8, 0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 0, i32 0
@@ -552,9 +552,9 @@ define void @setgt_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmsgt.vx v25, v28, zero
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsgt.vx v12, v8, zero
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 0, i32 0
@@ -570,8 +570,8 @@ define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-NEXT: addi a2, zero, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vmsle.vi v25, v8, -1
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsle.vi v16, v8, -1
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 0, i32 0
@@ -585,9 +585,9 @@ define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
; CHECK-LABEL: setge_vi_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmsgt.vi v25, v25, -1
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsgt.vi v8, v8, -1
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 0, i32 0
@@ -601,9 +601,9 @@ define void @setle_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
; CHECK-LABEL: setle_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmsle.vi v25, v25, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsle.vi v8, v8, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 0, i32 0
@@ -618,10 +618,10 @@ define void @setugt_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 5
-; CHECK-NEXT: vmsgtu.vx v25, v26, a0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0
+; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 5, i32 0
@@ -636,9 +636,9 @@ define void @setult_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmsleu.vi v25, v28, 4
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsleu.vi v12, v8, 4
+; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 5, i32 0
@@ -654,8 +654,8 @@ define void @setuge_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-NEXT: addi a2, zero, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vmsgtu.vi v25, v8, 4
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsgtu.vi v16, v8, 4
+; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 5, i32 0
@@ -669,9 +669,9 @@ define void @setule_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
; CHECK-LABEL: setule_vi_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmsleu.vi v25, v25, 5
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmsleu.vi v8, v8, 5
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 5, i32 0
@@ -685,12 +685,12 @@ define void @seteq_vv_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: seteq_vv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmseq.vv v0, v25, v26
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vmseq.vv v0, v8, v9
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -704,12 +704,12 @@ define void @setne_vv_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: setne_vv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmsne.vv v0, v25, v26
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmsne.vv v0, v8, v9
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -723,12 +723,12 @@ define void @setgt_vv_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: setgt_vv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmslt.vv v0, v26, v25
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vmslt.vv v0, v9, v8
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -742,12 +742,12 @@ define void @setlt_vv_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; CHECK-LABEL: setlt_vv_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vmslt.vv v0, v26, v28
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT: vse16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vmslt.vv v0, v8, v10
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -761,12 +761,12 @@ define void @setugt_vv_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; CHECK-LABEL: setugt_vv_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vmsltu.vv v0, v28, v26
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vmsltu.vv v0, v10, v8
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -780,12 +780,12 @@ define void @setult_vv_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; CHECK-LABEL: setult_vv_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vle64.v v28, (a1)
-; CHECK-NEXT: vmsltu.vv v0, v26, v28
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT: vse64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v10, (a1)
+; CHECK-NEXT: vmsltu.vv v0, v8, v10
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
index d9ad41291a7c8..f01eeefa18ed2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
@@ -60,9 +60,9 @@ define <4 x i16> @vrgather_permute_shuffle_vu_v4i16(<4 x i16> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%s = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 1>
ret <4 x i16> %s
@@ -74,9 +74,9 @@ define <4 x i16> @vrgather_permute_shuffle_uv_v4i16(<4 x i16> %x) {
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%s = shufflevector <4 x i16> undef, <4 x i16> %x, <4 x i32> <i32 5, i32 6, i32 4, i32 5>
ret <4 x i16> %s
@@ -88,14 +88,14 @@ define <4 x i16> @vrgather_shuffle_vv_v4i16(<4 x i16> %x, <4 x i16> %y) {
; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vrgather.vv v25, v8, v26
+; CHECK-NEXT: vle16.v v11, (a0)
+; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: addi a0, zero, 8
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v9, 1, v0.t
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
ret <4 x i16> %s
@@ -108,11 +108,11 @@ define <4 x i16> @vrgather_shuffle_xv_v4i16(<4 x i16> %x) {
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vi v26, v25, 4
-; CHECK-NEXT: vmv.v.i v25, 5
-; CHECK-NEXT: vrgather.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vi v10, v9, 4
+; CHECK-NEXT: vmv.v.i v9, 5
+; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%s = shufflevector <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i16> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x i16> %s
@@ -122,15 +122,15 @@ define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) {
; CHECK-LABEL: vrgather_shuffle_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
+; CHECK-NEXT: vid.v v9
; CHECK-NEXT: addi a0, zero, 3
-; CHECK-NEXT: vmul.vx v26, v25, a0
+; CHECK-NEXT: vmul.vx v10, v9, a0
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 5
-; CHECK-NEXT: vrgather.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vmv.v.i v9, 5
+; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%s = shufflevector <4 x i16> %x, <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x i16> %s
@@ -142,10 +142,10 @@ define <8 x i64> @vrgather_permute_shuffle_vu_v8i64(<8 x i64> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI9_0)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v28, v8, v25
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vrgatherei16.vv v12, v8, v16
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_permute_shuffle_vu_v8i64:
@@ -153,9 +153,9 @@ define <8 x i64> @vrgather_permute_shuffle_vu_v8i64(<8 x i64> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI9_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI9_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v12, (a0)
-; RV64-NEXT: vrgather.vv v28, v8, v12
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vrgather.vv v12, v8, v16
+; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> undef, <8 x i32> <i32 1, i32 2, i32 0, i32 1, i32 7, i32 6, i32 0, i32 1>
ret <8 x i64> %s
@@ -167,10 +167,10 @@ define <8 x i64> @vrgather_permute_shuffle_uv_v8i64(<8 x i64> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v28, v8, v25
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vrgatherei16.vv v12, v8, v16
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_permute_shuffle_uv_v8i64:
@@ -178,9 +178,9 @@ define <8 x i64> @vrgather_permute_shuffle_uv_v8i64(<8 x i64> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI10_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v12, (a0)
-; RV64-NEXT: vrgather.vv v28, v8, v12
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vrgather.vv v12, v8, v16
+; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%s = shufflevector <8 x i64> undef, <8 x i64> %x, <8 x i32> <i32 9, i32 10, i32 8, i32 9, i32 15, i32 8, i32 8, i32 11>
ret <8 x i64> %s
@@ -191,43 +191,43 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 5
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
-; RV32-NEXT: vmv.v.i v26, 2
+; RV32-NEXT: vmv.s.x v16, a0
+; RV32-NEXT: vmv.v.i v20, 2
; RV32-NEXT: vsetvli zero, zero, e16, m1, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 7
+; RV32-NEXT: vslideup.vi v20, v16, 7
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v21, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v28, v8, v25
+; RV32-NEXT: vrgatherei16.vv v16, v8, v21
; RV32-NEXT: addi a0, zero, 164
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v28, v12, v26, v0.t
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vrgatherei16.vv v16, v12, v20, v0.t
+; RV32-NEXT: vmv4r.v v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_vv_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: addi a0, zero, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vmv.s.x v28, a0
-; RV64-NEXT: vmv.v.i v16, 2
+; RV64-NEXT: vmv.s.x v16, a0
+; RV64-NEXT: vmv.v.i v20, 2
; RV64-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; RV64-NEXT: vslideup.vi v16, v28, 7
+; RV64-NEXT: vslideup.vi v20, v16, 7
; RV64-NEXT: lui a0, %hi(.LCPI11_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v20, (a0)
-; RV64-NEXT: vrgather.vv v28, v8, v20
+; RV64-NEXT: vle64.v v24, (a0)
+; RV64-NEXT: vrgather.vv v16, v8, v24
; RV64-NEXT: addi a0, zero, 164
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vrgather.vv v28, v12, v16, v0.t
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vrgather.vv v16, v12, v20, v0.t
+; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
ret <8 x i64> %s
@@ -239,20 +239,20 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vmv.v.i v12, -1
-; RV32-NEXT: vrgatherei16.vv v28, v12, v25
+; RV32-NEXT: vmv.v.i v20, -1
+; RV32-NEXT: vrgatherei16.vv v12, v20, v16
; RV32-NEXT: addi a0, zero, 113
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v28, v8, v25, v0.t
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_xv_v8i64:
@@ -263,10 +263,10 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI12_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v12, (a0)
-; RV64-NEXT: vmv.v.i v28, -1
-; RV64-NEXT: vrgather.vv v28, v8, v12, v0.t
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vmv.v.i v12, -1
+; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t
+; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%s = shufflevector <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> %x, <8 x i32> <i32 8, i32 3, i32 6, i32 5, i32 8, i32 12, i32 14, i32 3>
ret <8 x i64> %s
@@ -278,20 +278,20 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
-; RV32-NEXT: vmv4r.v v28, v8
+; RV32-NEXT: vle16.v v16, (a0)
+; RV32-NEXT: vmv4r.v v12, v8
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v8, v28, v25
+; RV32-NEXT: vrgatherei16.vv v8, v12, v16
; RV32-NEXT: addi a0, zero, 140
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v12, (a0)
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vmv.v.i v28, 5
-; RV32-NEXT: vrgatherei16.vv v8, v28, v25, v0.t
+; RV32-NEXT: vmv.v.i v16, 5
+; RV32-NEXT: vrgatherei16.vv v8, v16, v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_vx_v8i64:
@@ -302,10 +302,10 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV64-NEXT: lui a0, %hi(.LCPI13_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v12, (a0)
-; RV64-NEXT: vmv.v.i v28, 5
-; RV64-NEXT: vrgather.vv v28, v8, v12, v0.t
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vmv.v.i v12, 5
+; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t
+; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> <i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5, i64 5>, <8 x i32> <i32 0, i32 3, i32 10, i32 9, i32 4, i32 1, i32 7, i32 14>
ret <8 x i64> %s
@@ -317,15 +317,15 @@ define <4 x i8> @interleave_shuffles(<4 x i8> %x) {
; CHECK-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 1
+; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: addi a1, zero, 10
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vsrl.vi v26, v26, 1
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsrl.vi v10, v8, 1
; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vrgather.vv v8, v25, v26, v0.t
+; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%y = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
%z = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -337,8 +337,8 @@ define <8 x i8> @splat_ve4(<8 x i8> %v) {
; CHECK-LABEL: splat_ve4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 4
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 4
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff
@@ -348,13 +348,13 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
; CHECK-LABEL: splat_ve4_ins_i0ve2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 4
+; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: addi a0, zero, 2
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 2, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff
@@ -365,13 +365,13 @@ define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 3
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 4
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 1
+; CHECK-NEXT: vslideup.vi v10, v9, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff
@@ -384,9 +384,9 @@ define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 2
-; CHECK-NEXT: vrgather.vi v25, v9, 0, v0.t
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v10, v8, 2
+; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
@@ -396,18 +396,18 @@ define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i0ve4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 2
+; CHECK-NEXT: vmv.v.i v11, 2
; CHECK-NEXT: addi a0, zero, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v11, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v26
+; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: addi a0, zero, 66
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v9, 0, v0.t
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
@@ -420,12 +420,12 @@ define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 2
+; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 4
+; CHECK-NEXT: vmv.v.i v8, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
@@ -437,15 +437,15 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 514
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vmv.v.x v26, a0
+; RV32-NEXT: vmv.v.x v11, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vrgather.vv v25, v8, v26
+; RV32-NEXT: vrgather.vv v10, v8, v11
; RV32-NEXT: addi a0, zero, 66
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vrgather.vi v25, v9, 0, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vrgather.vi v10, v9, 0, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: splat_ve2_we0_ins_i2ve4:
@@ -453,15 +453,15 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 514
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v11, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vrgather.vv v25, v8, v26
+; RV64-NEXT: vrgather.vv v10, v8, v11
; RV64-NEXT: addi a0, zero, 66
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vrgather.vi v25, v9, 0, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vrgather.vi v10, v9, 0, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
@@ -472,17 +472,17 @@ define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 2
+; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: addi a0, zero, 70
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 2
-; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v10, v8, 2
+; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
@@ -493,44 +493,44 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 6
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.s.x v10, a0
+; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 5
+; RV32-NEXT: vslideup.vi v11, v10, 5
; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 2
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vmv.v.x v27, a0
+; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vrgather.vv v25, v8, v27
+; RV32-NEXT: vrgather.vv v10, v8, v12
; RV32-NEXT: addi a0, zero, 98
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vrgather.vv v25, v9, v26, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV64: # %bb.0:
; RV64-NEXT: addi a0, zero, 6
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.s.x v25, a0
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.s.x v10, a0
+; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v25, 5
+; RV64-NEXT: vslideup.vi v11, v10, 5
; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 2
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vmv.v.x v27, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vrgather.vv v25, v8, v27
+; RV64-NEXT: vrgather.vv v10, v8, v12
; RV64-NEXT: addi a0, zero, 98
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vrgather.vv v25, v9, v26, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2>
ret <8 x i8> %shuff
@@ -540,15 +540,15 @@ define <8 x i8> @widen_splat_ve3(<4 x i8> %v) {
; CHECK-LABEL: widen_splat_ve3:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v25, v8, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v25, v26, 4
+; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v8, v25, 3
+; CHECK-NEXT: vrgather.vi v8, v9, 3
; CHECK-NEXT: ret
%shuf = shufflevector <4 x i8> %v, <4 x i8> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
ret <8 x i8> %shuf
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
index 4098ff88cc14a..024725bd1a5a9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
@@ -10,8 +10,8 @@ define void @splat_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: splat_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 %y, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -23,8 +23,8 @@ define void @splat_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: splat_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 %y, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -36,8 +36,8 @@ define void @splat_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: splat_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 %y, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -54,8 +54,8 @@ define void @splat_v2i64(<2 x i64>* %x, i64 %y) {
; LMULMAX8-RV32-NEXT: sw a1, 8(sp)
; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX8-RV32-NEXT: addi a1, sp, 8
-; LMULMAX8-RV32-NEXT: vlse64.v v25, (a1), zero
-; LMULMAX8-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero
+; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: addi sp, sp, 16
; LMULMAX8-RV32-NEXT: ret
;
@@ -67,8 +67,8 @@ define void @splat_v2i64(<2 x i64>* %x, i64 %y) {
; LMULMAX2-RV32-NEXT: sw a1, 8(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 8
-; LMULMAX2-RV32-NEXT: vlse64.v v25, (a1), zero
-; LMULMAX2-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 16
; LMULMAX2-RV32-NEXT: ret
;
@@ -80,30 +80,30 @@ define void @splat_v2i64(<2 x i64>* %x, i64 %y) {
; LMULMAX1-RV32-NEXT: sw a1, 8(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 8
-; LMULMAX1-RV32-NEXT: vlse64.v v25, (a1), zero
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vlse64.v v8, (a1), zero
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 16
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX8-RV64-LABEL: splat_v2i64:
; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX8-RV64-NEXT: vmv.v.x v25, a1
-; LMULMAX8-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX8-RV64-NEXT: vmv.v.x v8, a1
+; LMULMAX8-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV64-NEXT: ret
;
; LMULMAX2-RV64-LABEL: splat_v2i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.x v25, a1
-; LMULMAX2-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_v2i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <2 x i64> undef, i64 %y, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -116,25 +116,25 @@ define void @splat_v32i8(<32 x i8>* %x, i8 %y) {
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a2, zero, 32
; LMULMAX8-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.x v26, a1
-; LMULMAX8-NEXT: vse8.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.x v8, a1
+; LMULMAX8-NEXT: vse8.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.x v26, a1
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.x v8, a1
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.x v25, a1
+; LMULMAX1-NEXT: vmv.v.x v8, a1
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse8.v v25, (a1)
-; LMULMAX1-NEXT: vse8.v v25, (a0)
+; LMULMAX1-NEXT: vse8.v v8, (a1)
+; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 %y, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
@@ -146,24 +146,24 @@ define void @splat_v16i16(<16 x i16>* %x, i16 %y) {
; LMULMAX8-LABEL: splat_v16i16:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.x v26, a1
-; LMULMAX8-NEXT: vse16.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.x v8, a1
+; LMULMAX8-NEXT: vse16.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.x v26, a1
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.x v8, a1
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.x v25, a1
+; LMULMAX1-NEXT: vmv.v.x v8, a1
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse16.v v25, (a1)
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a1)
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 %y, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
@@ -175,24 +175,24 @@ define void @splat_v8i32(<8 x i32>* %x, i32 %y) {
; LMULMAX8-LABEL: splat_v8i32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.x v26, a1
-; LMULMAX8-NEXT: vse32.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.x v8, a1
+; LMULMAX8-NEXT: vse32.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.x v26, a1
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.x v8, a1
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.x v25, a1
+; LMULMAX1-NEXT: vmv.v.x v8, a1
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vse32.v v25, (a1)
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 %y, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
@@ -209,8 +209,8 @@ define void @splat_v4i64(<4 x i64>* %x, i64 %y) {
; LMULMAX8-RV32-NEXT: sw a1, 8(sp)
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX8-RV32-NEXT: addi a1, sp, 8
-; LMULMAX8-RV32-NEXT: vlse64.v v26, (a1), zero
-; LMULMAX8-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero
+; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: addi sp, sp, 16
; LMULMAX8-RV32-NEXT: ret
;
@@ -222,8 +222,8 @@ define void @splat_v4i64(<4 x i64>* %x, i64 %y) {
; LMULMAX2-RV32-NEXT: sw a1, 8(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 8
-; LMULMAX2-RV32-NEXT: vlse64.v v26, (a1), zero
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 16
; LMULMAX2-RV32-NEXT: ret
;
@@ -233,34 +233,34 @@ define void @splat_v4i64(<4 x i64>* %x, i64 %y) {
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a3
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v25, a2
-; LMULMAX1-RV32-NEXT: vmerge.vxm v25, v25, a1, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v8, a2
+; LMULMAX1-RV32-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX8-RV64-LABEL: splat_v4i64:
; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX8-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX8-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX8-RV64-NEXT: vmv.v.x v8, a1
+; LMULMAX8-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV64-NEXT: ret
;
; LMULMAX2-RV64-LABEL: splat_v4i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
+; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <4 x i64> undef, i64 %y, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
@@ -272,8 +272,8 @@ define void @splat_zero_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: splat_zero_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 0, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -285,8 +285,8 @@ define void @splat_zero_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: splat_zero_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 0, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -298,8 +298,8 @@ define void @splat_zero_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: splat_zero_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 0, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -311,8 +311,8 @@ define void @splat_zero_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: splat_zero_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i64> undef, i64 0, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -325,25 +325,25 @@ define void @splat_zero_v32i8(<32 x i8>* %x) {
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a1, zero, 32
; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, 0
-; LMULMAX8-NEXT: vse8.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vse8.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_zero_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vse8.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse8.v v25, (a0)
+; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 0, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
@@ -355,24 +355,24 @@ define void @splat_zero_v16i16(<16 x i16>* %x) {
; LMULMAX8-LABEL: splat_zero_v16i16:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, 0
-; LMULMAX8-NEXT: vse16.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vse16.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_zero_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 0, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
@@ -384,24 +384,24 @@ define void @splat_zero_v8i32(<8 x i32>* %x) {
; LMULMAX8-LABEL: splat_zero_v8i32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, 0
-; LMULMAX8-NEXT: vse32.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vse32.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_zero_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_zero_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, 0
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, 0
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 0, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
@@ -413,33 +413,33 @@ define void @splat_zero_v4i64(<4 x i64>* %x) {
; LMULMAX8-LABEL: splat_zero_v4i64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, 0
-; LMULMAX8-NEXT: vse64.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, 0
+; LMULMAX8-NEXT: vse64.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_zero_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, 0
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, 0
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_zero_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.i v25, 0
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a0, 16
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_zero_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.i v25, 0
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a0, 16
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <4 x i64> undef, i64 0, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
@@ -451,8 +451,8 @@ define void @splat_allones_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: splat_allones_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, -1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i8> undef, i8 -1, i32 0
%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -464,8 +464,8 @@ define void @splat_allones_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: splat_allones_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, -1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i16> undef, i16 -1, i32 0
%b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -477,8 +477,8 @@ define void @splat_allones_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: splat_allones_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, -1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i32> undef, i32 -1, i32 0
%b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -490,8 +490,8 @@ define void @splat_allones_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: splat_allones_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vmv.v.i v8, -1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <2 x i64> undef, i64 -1, i32 0
%b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -504,25 +504,25 @@ define void @splat_allones_v32i8(<32 x i8>* %x) {
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a1, zero, 32
; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, -1
-; LMULMAX8-NEXT: vse8.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, -1
+; LMULMAX8-NEXT: vse8.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_allones_v32i8:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, -1
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, -1
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, -1
-; LMULMAX1-NEXT: vse8.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, -1
+; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse8.v v25, (a0)
+; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> undef, i8 -1, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
@@ -534,24 +534,24 @@ define void @splat_allones_v16i16(<16 x i16>* %x) {
; LMULMAX8-LABEL: splat_allones_v16i16:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, -1
-; LMULMAX8-NEXT: vse16.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, -1
+; LMULMAX8-NEXT: vse16.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_allones_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, -1
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, -1
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, -1
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, -1
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse16.v v25, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> undef, i16 -1, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
@@ -563,24 +563,24 @@ define void @splat_allones_v8i32(<8 x i32>* %x) {
; LMULMAX8-LABEL: splat_allones_v8i32:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, -1
-; LMULMAX8-NEXT: vse32.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, -1
+; LMULMAX8-NEXT: vse32.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_allones_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, -1
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, -1
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: splat_allones_v8i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v25, -1
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vmv.v.i v8, -1
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16
-; LMULMAX1-NEXT: vse32.v v25, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> undef, i32 -1, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
@@ -592,33 +592,33 @@ define void @splat_allones_v4i64(<4 x i64>* %x) {
; LMULMAX8-LABEL: splat_allones_v4i64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX8-NEXT: vmv.v.i v26, -1
-; LMULMAX8-NEXT: vse64.v v26, (a0)
+; LMULMAX8-NEXT: vmv.v.i v8, -1
+; LMULMAX8-NEXT: vse64.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_allones_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v26, -1
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v8, -1
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_allones_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.i v25, -1
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vmv.v.i v8, -1
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a0, 16
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_allones_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.i v25, -1
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vmv.v.i v8, -1
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a0, 16
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <4 x i64> undef, i64 -1, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
@@ -634,44 +634,44 @@ define void @splat_allones_with_use_v4i64(<4 x i64>* %x) {
; LMULMAX8-LABEL: splat_allones_with_use_v4i64:
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX8-NEXT: vle64.v v26, (a0)
-; LMULMAX8-NEXT: vadd.vi v26, v26, -1
-; LMULMAX8-NEXT: vse64.v v26, (a0)
+; LMULMAX8-NEXT: vle64.v v8, (a0)
+; LMULMAX8-NEXT: vadd.vi v8, v8, -1
+; LMULMAX8-NEXT: vse64.v v8, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX2-LABEL: splat_allones_with_use_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vadd.vi v26, v26, -1
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vadd.vi v8, v8, -1
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_allones_with_use_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.i v27, -1
+; LMULMAX1-RV32-NEXT: vmv.v.i v10, -1
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_allones_with_use_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vadd.vi v25, v25, -1
-; LMULMAX1-RV64-NEXT: vadd.vi v26, v26, -1
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vadd.vi v8, v8, -1
+; LMULMAX1-RV64-NEXT: vadd.vi v9, v9, -1
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = add <4 x i64> %a, <i64 -1, i64 -1, i64 -1, i64 -1>
@@ -703,80 +703,80 @@ define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) {
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: addi a4, a0, 64
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a4)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a4)
; LMULMAX2-RV32-NEXT: addi a4, a0, 96
-; LMULMAX2-RV32-NEXT: vle64.v v28, (a4)
-; LMULMAX2-RV32-NEXT: vle64.v v30, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v10, (a4)
+; LMULMAX2-RV32-NEXT: vle64.v v12, (a0)
; LMULMAX2-RV32-NEXT: addi a0, a0, 32
-; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v14, (a0)
; LMULMAX2-RV32-NEXT: addi a0, zero, 85
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a0
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2
-; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0
+; LMULMAX2-RV32-NEXT: vmv.v.x v16, a2
+; LMULMAX2-RV32-NEXT: vmerge.vxm v16, v16, a1, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
-; LMULMAX2-RV32-NEXT: vadd.vv v30, v30, v10
-; LMULMAX2-RV32-NEXT: vadd.vv v28, v28, v10
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v10
+; LMULMAX2-RV32-NEXT: vadd.vv v14, v14, v16
+; LMULMAX2-RV32-NEXT: vadd.vv v12, v12, v16
+; LMULMAX2-RV32-NEXT: vadd.vv v10, v10, v16
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v16
; LMULMAX2-RV32-NEXT: addi a0, a3, 64
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi a0, a3, 96
-; LMULMAX2-RV32-NEXT: vse64.v v28, (a0)
-; LMULMAX2-RV32-NEXT: vse64.v v30, (a3)
+; LMULMAX2-RV32-NEXT: vse64.v v10, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v12, (a3)
; LMULMAX2-RV32-NEXT: addi a0, a3, 32
-; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX2-RV32-NEXT: vse64.v v14, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX1-RV32-LABEL: vadd_vx_v16i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a4, a0, 96
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a4)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a4)
; LMULMAX1-RV32-NEXT: addi a4, a0, 112
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a4)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a4)
; LMULMAX1-RV32-NEXT: addi a4, a0, 64
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a4)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a4)
; LMULMAX1-RV32-NEXT: addi a4, a0, 80
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a4)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a4)
; LMULMAX1-RV32-NEXT: addi a4, a0, 32
-; LMULMAX1-RV32-NEXT: vle64.v v29, (a4)
+; LMULMAX1-RV32-NEXT: vle64.v v12, (a4)
; LMULMAX1-RV32-NEXT: addi a4, a0, 48
-; LMULMAX1-RV32-NEXT: vle64.v v30, (a4)
-; LMULMAX1-RV32-NEXT: vle64.v v31, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v13, (a4)
+; LMULMAX1-RV32-NEXT: vle64.v v14, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v15, (a0)
; LMULMAX1-RV32-NEXT: addi a0, zero, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a0
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v9, a2
-; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a1, v0
+; LMULMAX1-RV32-NEXT: vmv.v.x v16, a2
+; LMULMAX1-RV32-NEXT: vmerge.vxm v16, v16, a1, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT: vadd.vv v31, v31, v9
-; LMULMAX1-RV32-NEXT: vadd.vv v30, v30, v9
-; LMULMAX1-RV32-NEXT: vadd.vv v29, v29, v9
-; LMULMAX1-RV32-NEXT: vadd.vv v28, v28, v9
-; LMULMAX1-RV32-NEXT: vadd.vv v27, v27, v9
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v9
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v9
+; LMULMAX1-RV32-NEXT: vadd.vv v15, v15, v16
+; LMULMAX1-RV32-NEXT: vadd.vv v14, v14, v16
+; LMULMAX1-RV32-NEXT: vadd.vv v13, v13, v16
+; LMULMAX1-RV32-NEXT: vadd.vv v12, v12, v16
+; LMULMAX1-RV32-NEXT: vadd.vv v11, v11, v16
+; LMULMAX1-RV32-NEXT: vadd.vv v10, v10, v16
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v16
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v16
; LMULMAX1-RV32-NEXT: addi a0, a3, 96
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a3, 112
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a3, 64
-; LMULMAX1-RV32-NEXT: vse64.v v27, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v10, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a3, 80
-; LMULMAX1-RV32-NEXT: vse64.v v28, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v11, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a3, 32
-; LMULMAX1-RV32-NEXT: vse64.v v29, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v12, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a3, 48
-; LMULMAX1-RV32-NEXT: vse64.v v30, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v31, (a3)
+; LMULMAX1-RV32-NEXT: vse64.v v13, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v14, (a3)
; LMULMAX1-RV32-NEXT: addi a0, a3, 16
-; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v15, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX8-RV64-LABEL: vadd_vx_v16i64:
@@ -791,66 +791,66 @@ define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) {
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: addi a3, a0, 96
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a3)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a3)
; LMULMAX2-RV64-NEXT: addi a3, a0, 32
-; LMULMAX2-RV64-NEXT: vle64.v v28, (a3)
+; LMULMAX2-RV64-NEXT: vle64.v v10, (a3)
; LMULMAX2-RV64-NEXT: addi a3, a0, 64
-; LMULMAX2-RV64-NEXT: vle64.v v30, (a3)
-; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV64-NEXT: vadd.vx v28, v28, a1
-; LMULMAX2-RV64-NEXT: vadd.vx v26, v26, a1
-; LMULMAX2-RV64-NEXT: vadd.vx v30, v30, a1
+; LMULMAX2-RV64-NEXT: vle64.v v12, (a3)
+; LMULMAX2-RV64-NEXT: vle64.v v14, (a0)
+; LMULMAX2-RV64-NEXT: vadd.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vadd.vx v8, v8, a1
-; LMULMAX2-RV64-NEXT: vse64.v v8, (a2)
+; LMULMAX2-RV64-NEXT: vadd.vx v12, v12, a1
+; LMULMAX2-RV64-NEXT: vadd.vx v14, v14, a1
+; LMULMAX2-RV64-NEXT: vse64.v v14, (a2)
; LMULMAX2-RV64-NEXT: addi a0, a2, 64
-; LMULMAX2-RV64-NEXT: vse64.v v30, (a0)
+; LMULMAX2-RV64-NEXT: vse64.v v12, (a0)
; LMULMAX2-RV64-NEXT: addi a0, a2, 96
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi a0, a2, 32
-; LMULMAX2-RV64-NEXT: vse64.v v28, (a0)
+; LMULMAX2-RV64-NEXT: vse64.v v10, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV64-LABEL: vadd_vx_v16i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a3, a0, 96
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a3)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a3)
; LMULMAX1-RV64-NEXT: addi a3, a0, 112
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a3)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a3)
; LMULMAX1-RV64-NEXT: addi a3, a0, 64
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a3)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a3)
; LMULMAX1-RV64-NEXT: addi a3, a0, 48
-; LMULMAX1-RV64-NEXT: vle64.v v29, (a3)
+; LMULMAX1-RV64-NEXT: vle64.v v12, (a3)
; LMULMAX1-RV64-NEXT: addi a3, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v30, (a3)
+; LMULMAX1-RV64-NEXT: vle64.v v13, (a3)
; LMULMAX1-RV64-NEXT: addi a3, a0, 80
; LMULMAX1-RV64-NEXT: addi a0, a0, 32
-; LMULMAX1-RV64-NEXT: vle64.v v31, (a0)
-; LMULMAX1-RV64-NEXT: vle64.v v8, (a3)
-; LMULMAX1-RV64-NEXT: vadd.vx v30, v30, a1
-; LMULMAX1-RV64-NEXT: vadd.vx v29, v29, a1
-; LMULMAX1-RV64-NEXT: vadd.vx v31, v31, a1
+; LMULMAX1-RV64-NEXT: vle64.v v14, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v15, (a3)
+; LMULMAX1-RV64-NEXT: vadd.vx v13, v13, a1
+; LMULMAX1-RV64-NEXT: vadd.vx v12, v12, a1
+; LMULMAX1-RV64-NEXT: vadd.vx v14, v14, a1
+; LMULMAX1-RV64-NEXT: vadd.vx v15, v15, a1
+; LMULMAX1-RV64-NEXT: vadd.vx v11, v11, a1
+; LMULMAX1-RV64-NEXT: vadd.vx v10, v10, a1
+; LMULMAX1-RV64-NEXT: vadd.vx v9, v9, a1
; LMULMAX1-RV64-NEXT: vadd.vx v8, v8, a1
-; LMULMAX1-RV64-NEXT: vadd.vx v28, v28, a1
-; LMULMAX1-RV64-NEXT: vadd.vx v27, v27, a1
-; LMULMAX1-RV64-NEXT: vadd.vx v26, v26, a1
-; LMULMAX1-RV64-NEXT: vadd.vx v25, v25, a1
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a2)
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a2)
; LMULMAX1-RV64-NEXT: addi a0, a2, 96
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a2, 112
-; LMULMAX1-RV64-NEXT: vse64.v v27, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v10, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a2, 64
-; LMULMAX1-RV64-NEXT: vse64.v v28, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v11, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a2, 80
-; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v15, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a2, 32
-; LMULMAX1-RV64-NEXT: vse64.v v31, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v14, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a2, 48
-; LMULMAX1-RV64-NEXT: vse64.v v29, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v12, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a2, 16
-; LMULMAX1-RV64-NEXT: vse64.v v30, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v13, (a0)
; LMULMAX1-RV64-NEXT: ret
%va = load <16 x i64>, <16 x i64>* %a
%head = insertelement <16 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
index adc0b67a05b8e..aff029fe1df30 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
@@ -9,8 +9,8 @@ define void @gather_const_v16i8(<16 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 12
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vlse8.v v25, (a1), zero
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vlse8.v v8, (a1), zero
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = extractelement <16 x i8> %a, i32 12
@@ -25,8 +25,8 @@ define void @gather_const_v8i16(<8 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 10
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vlse16.v v25, (a1), zero
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vlse16.v v8, (a1), zero
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = extractelement <8 x i16> %a, i32 5
@@ -41,8 +41,8 @@ define void @gather_const_v4i32(<4 x i32>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 12
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vlse32.v v25, (a1), zero
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vlse32.v v8, (a1), zero
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = extractelement <4 x i32> %a, i32 3
@@ -57,8 +57,8 @@ define void @gather_const_v2i64(<2 x i64>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 8
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vlse64.v v25, (a1), zero
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vlse64.v v8, (a1), zero
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = extractelement <2 x i64> %a, i32 1
@@ -74,21 +74,21 @@ define void @gather_const_v64i8(<64 x i8>* %x) {
; LMULMAX4-NEXT: addi a1, a0, 32
; LMULMAX4-NEXT: addi a2, zero, 64
; LMULMAX4-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; LMULMAX4-NEXT: vlse8.v v28, (a1), zero
-; LMULMAX4-NEXT: vse8.v v28, (a0)
+; LMULMAX4-NEXT: vlse8.v v8, (a1), zero
+; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret
;
; LMULMAX1-LABEL: gather_const_v64i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vlse8.v v25, (a1), zero
+; LMULMAX1-NEXT: vlse8.v v8, (a1), zero
; LMULMAX1-NEXT: addi a2, a0, 16
; LMULMAX1-NEXT: addi a3, a0, 48
-; LMULMAX1-NEXT: vse8.v v25, (a1)
-; LMULMAX1-NEXT: vse8.v v25, (a3)
-; LMULMAX1-NEXT: vse8.v v25, (a0)
-; LMULMAX1-NEXT: vse8.v v25, (a2)
+; LMULMAX1-NEXT: vse8.v v8, (a1)
+; LMULMAX1-NEXT: vse8.v v8, (a3)
+; LMULMAX1-NEXT: vse8.v v8, (a0)
+; LMULMAX1-NEXT: vse8.v v8, (a2)
; LMULMAX1-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = extractelement <64 x i8> %a, i32 32
@@ -104,22 +104,22 @@ define void @gather_const_v16i16(<32 x i16>* %x) {
; LMULMAX4-NEXT: addi a1, a0, 50
; LMULMAX4-NEXT: addi a2, zero, 32
; LMULMAX4-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; LMULMAX4-NEXT: vlse16.v v28, (a1), zero
-; LMULMAX4-NEXT: vse16.v v28, (a0)
+; LMULMAX4-NEXT: vlse16.v v8, (a1), zero
+; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret
;
; LMULMAX1-LABEL: gather_const_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 50
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vlse16.v v25, (a1), zero
+; LMULMAX1-NEXT: vlse16.v v8, (a1), zero
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32
-; LMULMAX1-NEXT: vse16.v v25, (a3)
-; LMULMAX1-NEXT: vse16.v v25, (a2)
-; LMULMAX1-NEXT: vse16.v v25, (a0)
-; LMULMAX1-NEXT: vse16.v v25, (a1)
+; LMULMAX1-NEXT: vse16.v v8, (a3)
+; LMULMAX1-NEXT: vse16.v v8, (a2)
+; LMULMAX1-NEXT: vse16.v v8, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = extractelement <32 x i16> %a, i32 25
@@ -134,22 +134,22 @@ define void @gather_const_v16i32(<16 x i32>* %x) {
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi a1, a0, 36
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; LMULMAX4-NEXT: vlse32.v v28, (a1), zero
-; LMULMAX4-NEXT: vse32.v v28, (a0)
+; LMULMAX4-NEXT: vlse32.v v8, (a1), zero
+; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: ret
;
; LMULMAX1-LABEL: gather_const_v16i32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 36
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vlse32.v v25, (a1), zero
+; LMULMAX1-NEXT: vlse32.v v8, (a1), zero
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32
-; LMULMAX1-NEXT: vse32.v v25, (a3)
-; LMULMAX1-NEXT: vse32.v v25, (a2)
-; LMULMAX1-NEXT: vse32.v v25, (a0)
-; LMULMAX1-NEXT: vse32.v v25, (a1)
+; LMULMAX1-NEXT: vse32.v v8, (a3)
+; LMULMAX1-NEXT: vse32.v v8, (a2)
+; LMULMAX1-NEXT: vse32.v v8, (a0)
+; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = extractelement <16 x i32> %a, i32 9
@@ -164,22 +164,22 @@ define void @gather_const_v8i64(<8 x i64>* %x) {
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi a1, a0, 24
; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; LMULMAX4-NEXT: vlse64.v v28, (a1), zero
-; LMULMAX4-NEXT: vse64.v v28, (a0)
+; LMULMAX4-NEXT: vlse64.v v8, (a1), zero
+; LMULMAX4-NEXT: vse64.v v8, (a0)
; LMULMAX4-NEXT: ret
;
; LMULMAX1-LABEL: gather_const_v8i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a1, a0, 24
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vlse64.v v25, (a1), zero
+; LMULMAX1-NEXT: vlse64.v v8, (a1), zero
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32
-; LMULMAX1-NEXT: vse64.v v25, (a3)
-; LMULMAX1-NEXT: vse64.v v25, (a2)
-; LMULMAX1-NEXT: vse64.v v25, (a0)
-; LMULMAX1-NEXT: vse64.v v25, (a1)
+; LMULMAX1-NEXT: vse64.v v8, (a3)
+; LMULMAX1-NEXT: vse64.v v8, (a2)
+; LMULMAX1-NEXT: vse64.v v8, (a0)
+; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x
%b = extractelement <8 x i64> %a, i32 3
@@ -194,8 +194,8 @@ define void @splat_concat_low(<4 x i16>* %x, <4 x i16>* %y, <8 x i16>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a0, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vlse16.v v25, (a0), zero
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vlse16.v v8, (a0), zero
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load <4 x i16>, <4 x i16>* %y
@@ -210,8 +210,8 @@ define void @splat_concat_high(<4 x i16>* %x, <4 x i16>* %y, <8 x i16>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, a1, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vlse16.v v25, (a0), zero
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vlse16.v v8, (a0), zero
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load <4 x i16>, <4 x i16>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
index 81435f224ab70..94cbc0c75ebea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -8,10 +8,10 @@ define void @add_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: add_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -24,10 +24,10 @@ define void @add_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: add_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -40,10 +40,10 @@ define void @add_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: add_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -56,10 +56,10 @@ define void @add_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: add_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -72,10 +72,10 @@ define void @sub_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: sub_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vsub.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vsub.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -88,10 +88,10 @@ define void @sub_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: sub_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vsub.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vsub.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -104,10 +104,10 @@ define void @sub_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: sub_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vsub.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vsub.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -120,10 +120,10 @@ define void @sub_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: sub_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vsub.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vsub.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -136,10 +136,10 @@ define void @mul_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: mul_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmul.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -152,10 +152,10 @@ define void @mul_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: mul_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmul.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -168,10 +168,10 @@ define void @mul_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: mul_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmul.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -184,10 +184,10 @@ define void @mul_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: mul_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmul.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -200,10 +200,10 @@ define void @and_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: and_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vand.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vand.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -216,10 +216,10 @@ define void @and_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: and_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vand.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vand.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -232,10 +232,10 @@ define void @and_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: and_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vand.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vand.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -248,10 +248,10 @@ define void @and_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: and_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vand.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vand.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -264,10 +264,10 @@ define void @or_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: or_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vor.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -280,10 +280,10 @@ define void @or_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: or_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vor.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -296,10 +296,10 @@ define void @or_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: or_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vor.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -312,10 +312,10 @@ define void @or_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: or_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vor.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vor.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -328,10 +328,10 @@ define void @xor_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: xor_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vxor.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vxor.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -344,10 +344,10 @@ define void @xor_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: xor_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vxor.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vxor.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -360,10 +360,10 @@ define void @xor_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: xor_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vxor.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vxor.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -376,10 +376,10 @@ define void @xor_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: xor_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vxor.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vxor.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -392,10 +392,10 @@ define void @lshr_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: lshr_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vsrl.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vsrl.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -408,10 +408,10 @@ define void @lshr_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: lshr_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vsrl.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vsrl.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -424,10 +424,10 @@ define void @lshr_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: lshr_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vsrl.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vsrl.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -440,10 +440,10 @@ define void @lshr_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: lshr_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vsrl.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vsrl.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -456,10 +456,10 @@ define void @ashr_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: ashr_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vsra.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vsra.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -472,10 +472,10 @@ define void @ashr_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: ashr_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vsra.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vsra.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -488,10 +488,10 @@ define void @ashr_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: ashr_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vsra.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vsra.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -504,10 +504,10 @@ define void @ashr_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: ashr_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vsra.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vsra.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -520,10 +520,10 @@ define void @shl_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: shl_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vsll.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vsll.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -536,10 +536,10 @@ define void @shl_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: shl_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vsll.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vsll.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -552,10 +552,10 @@ define void @shl_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: shl_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vsll.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vsll.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -568,10 +568,10 @@ define void @shl_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: shl_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vsll.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vsll.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -584,10 +584,10 @@ define void @sdiv_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: sdiv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vdiv.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -600,10 +600,10 @@ define void @sdiv_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: sdiv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vdiv.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -616,10 +616,10 @@ define void @sdiv_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: sdiv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vdiv.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -632,10 +632,10 @@ define void @sdiv_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: sdiv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vdiv.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -648,10 +648,10 @@ define void @srem_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: srem_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vrem.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -664,10 +664,10 @@ define void @srem_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: srem_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vrem.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -680,10 +680,10 @@ define void @srem_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: srem_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vrem.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -696,10 +696,10 @@ define void @srem_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: srem_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vrem.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -712,10 +712,10 @@ define void @udiv_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: udiv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vdivu.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -728,10 +728,10 @@ define void @udiv_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: udiv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vdivu.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -744,10 +744,10 @@ define void @udiv_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: udiv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vdivu.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -760,10 +760,10 @@ define void @udiv_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: udiv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vdivu.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -776,10 +776,10 @@ define void @urem_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: urem_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vremu.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -792,10 +792,10 @@ define void @urem_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: urem_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vremu.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -808,10 +808,10 @@ define void @urem_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: urem_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vremu.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -824,10 +824,10 @@ define void @urem_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: urem_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vremu.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -840,95 +840,95 @@ define void @mulhu_v16i8(<16 x i8>* %x) {
; RV32-LABEL: mulhu_v16i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vle8.v v25, (a0)
+; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: addi a1, zero, 513
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, 4
-; RV32-NEXT: vmerge.vim v26, v26, 1, v0
+; RV32-NEXT: vmv.v.i v9, 4
+; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: lui a1, 1
; RV32-NEXT: addi a2, a1, 78
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vmerge.vim v26, v26, 3, v0
+; RV32-NEXT: vmerge.vim v9, v9, 3, v0
; RV32-NEXT: lui a2, 8
; RV32-NEXT: addi a2, a2, 304
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vmerge.vim v26, v26, 2, v0
+; RV32-NEXT: vmerge.vim v9, v9, 2, v0
; RV32-NEXT: lui a2, 3
; RV32-NEXT: addi a2, a2, -2044
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vmv.v.i v27, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: addi a2, zero, -128
-; RV32-NEXT: vmerge.vxm v28, v27, a2, v0
+; RV32-NEXT: vmerge.vxm v11, v10, a2, v0
; RV32-NEXT: addi a1, a1, 32
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: lui a1, %hi(.LCPI52_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI52_0)
-; RV32-NEXT: vle8.v v29, (a1)
-; RV32-NEXT: vmerge.vim v27, v27, 1, v0
-; RV32-NEXT: vsrl.vv v27, v25, v27
-; RV32-NEXT: vmulhu.vv v27, v27, v29
-; RV32-NEXT: vsub.vv v25, v25, v27
-; RV32-NEXT: vmulhu.vv v25, v25, v28
-; RV32-NEXT: vadd.vv v25, v25, v27
-; RV32-NEXT: vsrl.vv v25, v25, v26
-; RV32-NEXT: vse8.v v25, (a0)
+; RV32-NEXT: vle8.v v12, (a1)
+; RV32-NEXT: vmerge.vim v10, v10, 1, v0
+; RV32-NEXT: vsrl.vv v10, v8, v10
+; RV32-NEXT: vmulhu.vv v10, v10, v12
+; RV32-NEXT: vsub.vv v8, v8, v10
+; RV32-NEXT: vmulhu.vv v8, v8, v11
+; RV32-NEXT: vadd.vv v8, v8, v10
+; RV32-NEXT: vsrl.vv v8, v8, v9
+; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhu_v16i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vle8.v v25, (a0)
+; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: addi a1, zero, 513
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, 4
-; RV64-NEXT: vmerge.vim v26, v26, 1, v0
+; RV64-NEXT: vmv.v.i v9, 4
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: lui a1, 1
; RV64-NEXT: addiw a2, a1, 78
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vmerge.vim v26, v26, 3, v0
+; RV64-NEXT: vmerge.vim v9, v9, 3, v0
; RV64-NEXT: lui a2, 8
; RV64-NEXT: addiw a2, a2, 304
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vmerge.vim v26, v26, 2, v0
+; RV64-NEXT: vmerge.vim v9, v9, 2, v0
; RV64-NEXT: lui a2, 3
; RV64-NEXT: addiw a2, a2, -2044
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vmv.v.i v27, 0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: addi a2, zero, -128
-; RV64-NEXT: vmerge.vxm v28, v27, a2, v0
+; RV64-NEXT: vmerge.vxm v11, v10, a2, v0
; RV64-NEXT: addiw a1, a1, 32
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: lui a1, %hi(.LCPI52_0)
; RV64-NEXT: addi a1, a1, %lo(.LCPI52_0)
-; RV64-NEXT: vle8.v v29, (a1)
-; RV64-NEXT: vmerge.vim v27, v27, 1, v0
-; RV64-NEXT: vsrl.vv v27, v25, v27
-; RV64-NEXT: vmulhu.vv v27, v27, v29
-; RV64-NEXT: vsub.vv v25, v25, v27
-; RV64-NEXT: vmulhu.vv v25, v25, v28
-; RV64-NEXT: vadd.vv v25, v25, v27
-; RV64-NEXT: vsrl.vv v25, v25, v26
-; RV64-NEXT: vse8.v v25, (a0)
+; RV64-NEXT: vle8.v v12, (a1)
+; RV64-NEXT: vmerge.vim v10, v10, 1, v0
+; RV64-NEXT: vsrl.vv v10, v8, v10
+; RV64-NEXT: vmulhu.vv v10, v10, v12
+; RV64-NEXT: vsub.vv v8, v8, v10
+; RV64-NEXT: vmulhu.vv v8, v8, v11
+; RV64-NEXT: vadd.vv v8, v8, v10
+; RV64-NEXT: vsrl.vv v8, v8, v9
+; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25>
@@ -940,36 +940,36 @@ define void @mulhu_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: mulhu_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a1, zero, 1
-; CHECK-NEXT: vmv.s.x v26, a1
+; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: addi a1, zero, 33
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v27, 3
-; CHECK-NEXT: vmerge.vim v27, v27, 2, v0
+; CHECK-NEXT: vmv.v.i v10, 3
+; CHECK-NEXT: vmerge.vim v10, v10, 2, v0
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v27, v26, 6
+; CHECK-NEXT: vslideup.vi v10, v9, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
+; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, mu
-; CHECK-NEXT: vmv1r.v v29, v28
-; CHECK-NEXT: vmv.s.x v29, a1
+; CHECK-NEXT: vmv1r.v v12, v11
+; CHECK-NEXT: vmv.s.x v12, a1
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v28, v26, 6
+; CHECK-NEXT: vslideup.vi v11, v9, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: lui a1, %hi(.LCPI53_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vsrl.vv v28, v25, v28
-; CHECK-NEXT: vmulhu.vv v26, v28, v26
-; CHECK-NEXT: vsub.vv v25, v25, v26
-; CHECK-NEXT: vmulhu.vv v25, v25, v29
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vsrl.vv v25, v25, v27
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vsrl.vv v11, v8, v11
+; CHECK-NEXT: vmulhu.vv v9, v11, v9
+; CHECK-NEXT: vsub.vv v8, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v12
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vv v8, v8, v10
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
@@ -981,28 +981,28 @@ define void @mulhu_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: mulhu_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 524288
-; CHECK-NEXT: vmv.s.x v26, a1
-; CHECK-NEXT: vmv.v.i v27, 0
+; CHECK-NEXT: vmv.s.x v9, a1
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v27, v26, 2
+; CHECK-NEXT: vslideup.vi v10, v9, 2
; CHECK-NEXT: lui a1, %hi(.LCPI54_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmulhu.vv v26, v25, v26
-; CHECK-NEXT: vsub.vv v25, v25, v26
-; CHECK-NEXT: vmulhu.vv v25, v25, v27
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmulhu.vv v9, v8, v9
+; CHECK-NEXT: vsub.vv v8, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v10
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: addi a1, zero, 1
-; CHECK-NEXT: vmv.s.x v26, a1
-; CHECK-NEXT: vmv.v.i v27, 2
+; CHECK-NEXT: vmv.s.x v9, a1
+; CHECK-NEXT: vmv.v.i v10, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v27, v26, 3
+; CHECK-NEXT: vslideup.vi v10, v9, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsrl.vv v25, v25, v27
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vsrl.vv v8, v8, v10
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = udiv <4 x i32> %a, <i32 5, i32 6, i32 7, i32 9>
@@ -1014,26 +1014,26 @@ define void @mulhu_v2i64(<2 x i64>* %x) {
; RV32-LABEL: mulhu_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a1, %hi(.LCPI55_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI55_0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v26, (a1)
+; RV32-NEXT: vle32.v v9, (a1)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vmulhu.vv v25, v25, v26
+; RV32-NEXT: vmulhu.vv v8, v8, v9
; RV32-NEXT: lui a1, %hi(.LCPI55_1)
; RV32-NEXT: addi a1, a1, %lo(.LCPI55_1)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v26, (a1)
+; RV32-NEXT: vle32.v v9, (a1)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vv v25, v25, v26
-; RV32-NEXT: vse64.v v25, (a0)
+; RV32-NEXT: vsrl.vv v8, v8, v9
+; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhu_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: lui a1, 1035469
; RV64-NEXT: addiw a1, a1, -819
; RV64-NEXT: slli a1, a1, 12
@@ -1042,7 +1042,7 @@ define void @mulhu_v2i64(<2 x i64>* %x) {
; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -819
-; RV64-NEXT: vmv.v.x v26, a1
+; RV64-NEXT: vmv.v.x v9, a1
; RV64-NEXT: lui a1, 1026731
; RV64-NEXT: addiw a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12
@@ -1052,13 +1052,13 @@ define void @mulhu_v2i64(<2 x i64>* %x) {
; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; RV64-NEXT: vmv.s.x v26, a1
+; RV64-NEXT: vmv.s.x v9, a1
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT: vmulhu.vv v25, v25, v26
-; RV64-NEXT: vid.v v26
-; RV64-NEXT: vadd.vi v26, v26, 1
-; RV64-NEXT: vsrl.vv v25, v25, v26
-; RV64-NEXT: vse64.v v25, (a0)
+; RV64-NEXT: vmulhu.vv v8, v8, v9
+; RV64-NEXT: vid.v v9
+; RV64-NEXT: vadd.vi v9, v9, 1
+; RV64-NEXT: vsrl.vv v8, v8, v9
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = udiv <2 x i64> %a, <i64 3, i64 5>
@@ -1070,41 +1070,41 @@ define void @mulhs_v16i8(<16 x i8>* %x) {
; RV32-LABEL: mulhs_v16i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vle8.v v25, (a0)
+; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: lui a1, 5
; RV32-NEXT: addi a1, a1, -1452
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, 7
-; RV32-NEXT: vmerge.vim v26, v26, 1, v0
+; RV32-NEXT: vmv.v.i v9, 7
+; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a1, zero, -123
-; RV32-NEXT: vmv.v.x v27, a1
+; RV32-NEXT: vmv.v.x v10, a1
; RV32-NEXT: addi a1, zero, 57
-; RV32-NEXT: vmerge.vxm v27, v27, a1, v0
-; RV32-NEXT: vmulhu.vv v25, v25, v27
-; RV32-NEXT: vsrl.vv v25, v25, v26
-; RV32-NEXT: vse8.v v25, (a0)
+; RV32-NEXT: vmerge.vxm v10, v10, a1, v0
+; RV32-NEXT: vmulhu.vv v8, v8, v10
+; RV32-NEXT: vsrl.vv v8, v8, v9
+; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhs_v16i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vle8.v v25, (a0)
+; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: lui a1, 5
; RV64-NEXT: addiw a1, a1, -1452
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, 7
-; RV64-NEXT: vmerge.vim v26, v26, 1, v0
+; RV64-NEXT: vmv.v.i v9, 7
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: addi a1, zero, -123
-; RV64-NEXT: vmv.v.x v27, a1
+; RV64-NEXT: vmv.v.x v10, a1
; RV64-NEXT: addi a1, zero, 57
-; RV64-NEXT: vmerge.vxm v27, v27, a1, v0
-; RV64-NEXT: vmulhu.vv v25, v25, v27
-; RV64-NEXT: vsrl.vv v25, v25, v26
-; RV64-NEXT: vse8.v v25, (a0)
+; RV64-NEXT: vmerge.vxm v10, v10, a1, v0
+; RV64-NEXT: vmulhu.vv v8, v8, v10
+; RV64-NEXT: vsrl.vv v8, v8, v9
+; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>
@@ -1116,43 +1116,43 @@ define void @mulhs_v8i16(<8 x i16>* %x) {
; RV32-LABEL: mulhs_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: addi a1, zero, 105
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: lui a1, 5
; RV32-NEXT: addi a1, a1, -1755
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a1
+; RV32-NEXT: vmv.v.x v9, a1
; RV32-NEXT: lui a1, 1048571
; RV32-NEXT: addi a1, a1, 1755
-; RV32-NEXT: vmerge.vxm v26, v26, a1, v0
-; RV32-NEXT: vmulh.vv v25, v25, v26
-; RV32-NEXT: vsra.vi v25, v25, 1
-; RV32-NEXT: vsrl.vi v26, v25, 15
-; RV32-NEXT: vadd.vv v25, v25, v26
-; RV32-NEXT: vse16.v v25, (a0)
+; RV32-NEXT: vmerge.vxm v9, v9, a1, v0
+; RV32-NEXT: vmulh.vv v8, v8, v9
+; RV32-NEXT: vsra.vi v8, v8, 1
+; RV32-NEXT: vsrl.vi v9, v8, 15
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: vse16.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhs_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64-NEXT: vle16.v v25, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: addi a1, zero, 105
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: lui a1, 5
; RV64-NEXT: addiw a1, a1, -1755
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a1
+; RV64-NEXT: vmv.v.x v9, a1
; RV64-NEXT: lui a1, 1048571
; RV64-NEXT: addiw a1, a1, 1755
-; RV64-NEXT: vmerge.vxm v26, v26, a1, v0
-; RV64-NEXT: vmulh.vv v25, v25, v26
-; RV64-NEXT: vsra.vi v25, v25, 1
-; RV64-NEXT: vsrl.vi v26, v25, 15
-; RV64-NEXT: vadd.vv v25, v25, v26
-; RV64-NEXT: vse16.v v25, (a0)
+; RV64-NEXT: vmerge.vxm v9, v9, a1, v0
+; RV64-NEXT: vmulh.vv v8, v8, v9
+; RV64-NEXT: vsra.vi v8, v8, 1
+; RV64-NEXT: vsrl.vi v9, v8, 15
+; RV64-NEXT: vadd.vv v8, v8, v9
+; RV64-NEXT: vse16.v v8, (a0)
; RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = sdiv <8 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>
@@ -1164,28 +1164,28 @@ define void @mulhs_v4i32(<4 x i32>* %x) {
; RV32-LABEL: mulhs_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: addi a1, zero, 5
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: lui a1, 419430
; RV32-NEXT: addi a1, a1, 1639
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a1
+; RV32-NEXT: vmv.v.x v9, a1
; RV32-NEXT: lui a1, 629146
; RV32-NEXT: addi a1, a1, -1639
-; RV32-NEXT: vmerge.vxm v26, v26, a1, v0
-; RV32-NEXT: vmulh.vv v25, v25, v26
-; RV32-NEXT: vsrl.vi v26, v25, 31
-; RV32-NEXT: vsra.vi v25, v25, 1
-; RV32-NEXT: vadd.vv v25, v25, v26
-; RV32-NEXT: vse32.v v25, (a0)
+; RV32-NEXT: vmerge.vxm v9, v9, a1, v0
+; RV32-NEXT: vmulh.vv v8, v8, v9
+; RV32-NEXT: vsrl.vi v9, v8, 31
+; RV32-NEXT: vsra.vi v8, v8, 1
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhs_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: lui a1, 13107
; RV64-NEXT: addiw a1, a1, 819
; RV64-NEXT: slli a1, a1, 12
@@ -1195,13 +1195,13 @@ define void @mulhs_v4i32(<4 x i32>* %x) {
; RV64-NEXT: slli a1, a1, 13
; RV64-NEXT: addi a1, a1, -1639
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a1
+; RV64-NEXT: vmv.v.x v9, a1
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vmulh.vv v25, v25, v26
-; RV64-NEXT: vsra.vi v25, v25, 1
-; RV64-NEXT: vsrl.vi v26, v25, 31
-; RV64-NEXT: vadd.vv v25, v25, v26
-; RV64-NEXT: vse32.v v25, (a0)
+; RV64-NEXT: vmulh.vv v8, v8, v9
+; RV64-NEXT: vsra.vi v8, v8, 1
+; RV64-NEXT: vsrl.vi v9, v8, 31
+; RV64-NEXT: vadd.vv v8, v8, v9
+; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = sdiv <4 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5>
@@ -1213,40 +1213,40 @@ define void @mulhs_v2i64(<2 x i64>* %x) {
; RV32-LABEL: mulhs_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a2, a1, 1365
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a2
+; RV32-NEXT: vmv.v.x v9, a2
; RV32-NEXT: addi a1, a1, 1366
; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; RV32-NEXT: vmv.s.x v26, a1
+; RV32-NEXT: vmv.s.x v9, a1
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vmulh.vv v26, v25, v26
+; RV32-NEXT: vmulh.vv v9, v8, v9
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vid.v v27
-; RV32-NEXT: vsrl.vi v27, v27, 1
-; RV32-NEXT: vrsub.vi v27, v27, 0
+; RV32-NEXT: vid.v v10
+; RV32-NEXT: vsrl.vi v10, v10, 1
+; RV32-NEXT: vrsub.vi v10, v10, 0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vmadd.vv v27, v25, v26
+; RV32-NEXT: vmadd.vv v10, v8, v9
; RV32-NEXT: addi a1, zero, 1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vmv.s.x v25, a1
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.s.x v8, a1
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 2
+; RV32-NEXT: vslideup.vi v9, v8, 2
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vsra.vv v25, v27, v26
+; RV32-NEXT: vsra.vv v8, v10, v9
; RV32-NEXT: addi a1, zero, 63
-; RV32-NEXT: vsrl.vx v26, v27, a1
-; RV32-NEXT: vadd.vv v25, v25, v26
-; RV32-NEXT: vse64.v v25, (a0)
+; RV32-NEXT: vsrl.vx v9, v10, a1
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhs_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: lui a1, 21845
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12
@@ -1255,20 +1255,20 @@ define void @mulhs_v2i64(<2 x i64>* %x) {
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a2, a1, 1365
-; RV64-NEXT: vmv.v.x v26, a2
+; RV64-NEXT: vmv.v.x v9, a2
; RV64-NEXT: addi a1, a1, 1366
; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; RV64-NEXT: vmv.s.x v26, a1
+; RV64-NEXT: vmv.s.x v9, a1
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT: vmulh.vv v26, v25, v26
-; RV64-NEXT: vid.v v27
-; RV64-NEXT: vrsub.vi v28, v27, 0
-; RV64-NEXT: vmadd.vv v28, v25, v26
+; RV64-NEXT: vmulh.vv v9, v8, v9
+; RV64-NEXT: vid.v v10
+; RV64-NEXT: vrsub.vi v11, v10, 0
+; RV64-NEXT: vmadd.vv v11, v8, v9
; RV64-NEXT: addi a1, zero, 63
-; RV64-NEXT: vsrl.vx v25, v28, a1
-; RV64-NEXT: vsra.vv v26, v28, v27
-; RV64-NEXT: vadd.vv v25, v26, v25
-; RV64-NEXT: vse64.v v25, (a0)
+; RV64-NEXT: vsrl.vx v8, v11, a1
+; RV64-NEXT: vsra.vv v9, v11, v10
+; RV64-NEXT: vadd.vv v8, v9, v8
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = sdiv <2 x i64> %a, <i64 3, i64 -3>
@@ -1280,10 +1280,10 @@ define void @smin_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: smin_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmin.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmin.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -1297,10 +1297,10 @@ define void @smin_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: smin_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmin.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vmin.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -1314,10 +1314,10 @@ define void @smin_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: smin_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmin.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmin.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -1331,10 +1331,10 @@ define void @smin_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: smin_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmin.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vmin.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -1348,10 +1348,10 @@ define void @smax_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: smax_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -1365,10 +1365,10 @@ define void @smax_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: smax_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -1382,10 +1382,10 @@ define void @smax_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: smax_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -1399,10 +1399,10 @@ define void @smax_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: smax_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmax.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vmax.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -1416,10 +1416,10 @@ define void @umin_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: umin_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vminu.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vminu.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -1433,10 +1433,10 @@ define void @umin_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: umin_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vminu.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vminu.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -1450,10 +1450,10 @@ define void @umin_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: umin_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vminu.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vminu.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -1467,10 +1467,10 @@ define void @umin_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: umin_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vminu.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vminu.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -1484,10 +1484,10 @@ define void @umax_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: umax_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmaxu.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v9, (a1)
+; CHECK-NEXT: vmaxu.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -1501,10 +1501,10 @@ define void @umax_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: umax_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmaxu.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: vmaxu.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -1518,10 +1518,10 @@ define void @umax_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: umax_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmaxu.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vmaxu.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -1535,10 +1535,10 @@ define void @umax_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; CHECK-LABEL: umax_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmaxu.vv v25, v25, v26
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v9, (a1)
+; CHECK-NEXT: vmaxu.vv v8, v8, v9
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y
@@ -1553,40 +1553,40 @@ define void @add_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: add_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: add_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -1599,40 +1599,40 @@ define void @add_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: add_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: add_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: add_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -1645,40 +1645,40 @@ define void @add_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: add_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: add_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: add_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -1691,40 +1691,40 @@ define void @add_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: add_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: add_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: add_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -1738,40 +1738,40 @@ define void @sub_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sub_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sub_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -1784,40 +1784,40 @@ define void @sub_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: sub_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sub_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sub_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -1830,40 +1830,40 @@ define void @sub_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: sub_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sub_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sub_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -1876,40 +1876,40 @@ define void @sub_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: sub_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sub_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sub_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -1923,40 +1923,40 @@ define void @mul_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vmul.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vmul.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mul_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mul_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -1969,40 +1969,40 @@ define void @mul_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: mul_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vmul.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vmul.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mul_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mul_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -2015,40 +2015,40 @@ define void @mul_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: mul_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vmul.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vmul.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mul_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mul_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -2061,40 +2061,40 @@ define void @mul_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: mul_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vmul.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vmul.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mul_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mul_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -2108,40 +2108,40 @@ define void @and_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vand.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: and_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: and_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -2154,40 +2154,40 @@ define void @and_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: and_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vand.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: and_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: and_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -2200,40 +2200,40 @@ define void @and_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: and_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vand.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: and_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: and_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -2246,40 +2246,40 @@ define void @and_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: and_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vand.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vand.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: and_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: and_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -2293,40 +2293,40 @@ define void @or_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: or_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: or_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -2339,40 +2339,40 @@ define void @or_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: or_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: or_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: or_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -2385,40 +2385,40 @@ define void @or_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: or_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: or_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: or_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -2431,40 +2431,40 @@ define void @or_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: or_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: or_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: or_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -2478,40 +2478,40 @@ define void @xor_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vxor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vxor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: xor_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: xor_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -2524,40 +2524,40 @@ define void @xor_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: xor_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vxor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vxor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: xor_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: xor_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -2570,40 +2570,40 @@ define void @xor_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: xor_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vxor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vxor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: xor_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: xor_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -2616,40 +2616,40 @@ define void @xor_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: xor_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vxor.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vxor.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: xor_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: xor_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -2663,40 +2663,40 @@ define void @lshr_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: lshr_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: lshr_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -2709,40 +2709,40 @@ define void @lshr_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: lshr_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: lshr_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: lshr_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -2755,40 +2755,40 @@ define void @lshr_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: lshr_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: lshr_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: lshr_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -2801,40 +2801,40 @@ define void @lshr_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: lshr_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: lshr_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: lshr_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -2848,40 +2848,40 @@ define void @ashr_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vsra.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vsra.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ashr_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ashr_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -2894,40 +2894,40 @@ define void @ashr_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: ashr_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vsra.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vsra.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ashr_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ashr_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -2940,40 +2940,40 @@ define void @ashr_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: ashr_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vsra.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vsra.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ashr_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ashr_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -2986,40 +2986,40 @@ define void @ashr_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: ashr_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vsra.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vsra.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: ashr_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: ashr_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -3033,40 +3033,40 @@ define void @shl_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vsll.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vsll.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: shl_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: shl_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -3079,40 +3079,40 @@ define void @shl_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: shl_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vsll.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vsll.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: shl_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: shl_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -3125,40 +3125,40 @@ define void @shl_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: shl_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vsll.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vsll.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: shl_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: shl_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -3171,40 +3171,40 @@ define void @shl_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: shl_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vsll.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vsll.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: shl_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: shl_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -3218,40 +3218,40 @@ define void @sdiv_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vdiv.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vdiv.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sdiv_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sdiv_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -3264,40 +3264,40 @@ define void @sdiv_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: sdiv_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vdiv.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vdiv.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sdiv_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sdiv_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -3310,40 +3310,40 @@ define void @sdiv_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: sdiv_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vdiv.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vdiv.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sdiv_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sdiv_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -3356,40 +3356,40 @@ define void @sdiv_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: sdiv_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vdiv.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vdiv.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: sdiv_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: sdiv_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -3403,40 +3403,40 @@ define void @srem_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vrem.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vrem.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: srem_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: srem_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -3449,40 +3449,40 @@ define void @srem_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: srem_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vrem.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vrem.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: srem_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: srem_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -3495,40 +3495,40 @@ define void @srem_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: srem_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vrem.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vrem.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: srem_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: srem_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -3541,40 +3541,40 @@ define void @srem_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: srem_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vrem.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vrem.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: srem_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: srem_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -3588,40 +3588,40 @@ define void @udiv_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vdivu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vdivu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: udiv_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: udiv_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -3634,40 +3634,40 @@ define void @udiv_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: udiv_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vdivu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vdivu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: udiv_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: udiv_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -3680,40 +3680,40 @@ define void @udiv_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: udiv_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vdivu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vdivu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: udiv_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: udiv_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -3726,40 +3726,40 @@ define void @udiv_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: udiv_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vdivu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vdivu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: udiv_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: udiv_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -3773,40 +3773,40 @@ define void @urem_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vremu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vremu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: urem_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: urem_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -3819,40 +3819,40 @@ define void @urem_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: urem_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vremu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vremu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: urem_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: urem_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -3865,40 +3865,40 @@ define void @urem_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: urem_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vremu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vremu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: urem_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: urem_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -3911,40 +3911,40 @@ define void @urem_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: urem_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vremu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vremu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: urem_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: urem_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -3957,25 +3957,25 @@ define void @extract_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: extract_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v4i64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-NEXT: vle64.v v25, (a0)
+; LMULMAX1-NEXT: vle64.v v8, (a0)
; LMULMAX1-NEXT: addi a2, a0, 16
-; LMULMAX1-NEXT: vle64.v v26, (a2)
-; LMULMAX1-NEXT: vle64.v v27, (a1)
+; LMULMAX1-NEXT: vle64.v v9, (a2)
+; LMULMAX1-NEXT: vle64.v v10, (a1)
; LMULMAX1-NEXT: addi a1, a1, 16
-; LMULMAX1-NEXT: vle64.v v28, (a1)
-; LMULMAX1-NEXT: vadd.vv v26, v26, v28
-; LMULMAX1-NEXT: vadd.vv v25, v25, v27
-; LMULMAX1-NEXT: vse64.v v25, (a0)
-; LMULMAX1-NEXT: vse64.v v26, (a2)
+; LMULMAX1-NEXT: vle64.v v11, (a1)
+; LMULMAX1-NEXT: vadd.vv v9, v9, v11
+; LMULMAX1-NEXT: vadd.vv v8, v8, v10
+; LMULMAX1-NEXT: vse64.v v8, (a0)
+; LMULMAX1-NEXT: vse64.v v9, (a2)
; LMULMAX1-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -3991,7 +3991,7 @@ define void @mulhu_v32i8(<32 x i8>* %x) {
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: addi a1, zero, 32
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle8.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV32-NEXT: lui a2, 66049
; LMULMAX2-RV32-NEXT: addi a2, a2, 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
@@ -3999,49 +3999,49 @@ define void @mulhu_v32i8(<32 x i8>* %x) {
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; LMULMAX2-RV32-NEXT: lui a2, %hi(.LCPI129_0)
; LMULMAX2-RV32-NEXT: addi a2, a2, %lo(.LCPI129_0)
-; LMULMAX2-RV32-NEXT: vle8.v v28, (a2)
-; LMULMAX2-RV32-NEXT: vmv.v.i v30, 0
-; LMULMAX2-RV32-NEXT: vmerge.vim v8, v30, 1, v0
-; LMULMAX2-RV32-NEXT: vsrl.vv v8, v26, v8
-; LMULMAX2-RV32-NEXT: vmulhu.vv v28, v8, v28
-; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vle8.v v10, (a2)
+; LMULMAX2-RV32-NEXT: vmv.v.i v12, 0
+; LMULMAX2-RV32-NEXT: vmerge.vim v14, v12, 1, v0
+; LMULMAX2-RV32-NEXT: vsrl.vv v14, v8, v14
+; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v14, v10
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a2, 163907
; LMULMAX2-RV32-NEXT: addi a2, a2, -2044
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: addi a2, zero, -128
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmerge.vxm v30, v30, a2, v0
-; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vmerge.vxm v12, v12, a2, v0
+; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v12
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a2, 8208
; LMULMAX2-RV32-NEXT: addi a2, a2, 513
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.i v28, 4
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0
+; LMULMAX2-RV32-NEXT: vmv.v.i v10, 4
+; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV32-NEXT: lui a2, 66785
; LMULMAX2-RV32-NEXT: addi a2, a2, 78
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 3, v0
+; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 3, v0
; LMULMAX2-RV32-NEXT: lui a2, 529160
; LMULMAX2-RV32-NEXT: addi a2, a2, 304
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 2, v0
-; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 2, v0
+; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: mulhu_v32i8:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: addi a1, zero, 32
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle8.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV64-NEXT: lui a2, 66049
; LMULMAX2-RV64-NEXT: addiw a2, a2, 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
@@ -4049,57 +4049,57 @@ define void @mulhu_v32i8(<32 x i8>* %x) {
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI129_0)
; LMULMAX2-RV64-NEXT: addi a2, a2, %lo(.LCPI129_0)
-; LMULMAX2-RV64-NEXT: vle8.v v28, (a2)
-; LMULMAX2-RV64-NEXT: vmv.v.i v30, 0
-; LMULMAX2-RV64-NEXT: vmerge.vim v8, v30, 1, v0
-; LMULMAX2-RV64-NEXT: vsrl.vv v8, v26, v8
-; LMULMAX2-RV64-NEXT: vmulhu.vv v28, v8, v28
-; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0
+; LMULMAX2-RV64-NEXT: vmerge.vim v14, v12, 1, v0
+; LMULMAX2-RV64-NEXT: vsrl.vv v14, v8, v14
+; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v14, v10
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a2, 163907
; LMULMAX2-RV64-NEXT: addiw a2, a2, -2044
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: addi a2, zero, -128
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmerge.vxm v30, v30, a2, v0
-; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v12, a2, v0
+; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v12
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a2, 8208
; LMULMAX2-RV64-NEXT: addiw a2, a2, 513
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.i v28, 4
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 1, v0
+; LMULMAX2-RV64-NEXT: vmv.v.i v10, 4
+; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV64-NEXT: lui a2, 66785
; LMULMAX2-RV64-NEXT: addiw a2, a2, 78
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 3, v0
+; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 3, v0
; LMULMAX2-RV64-NEXT: lui a2, 529160
; LMULMAX2-RV64-NEXT: addiw a2, a2, 304
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 2, v0
-; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 2, v0
+; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-LABEL: mulhu_v32i8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle8.v v25, (a1)
+; LMULMAX1-NEXT: vle8.v v8, (a1)
; LMULMAX1-NEXT: lui a2, %hi(.LCPI129_0)
; LMULMAX1-NEXT: addi a2, a2, %lo(.LCPI129_0)
-; LMULMAX1-NEXT: vle8.v v26, (a2)
-; LMULMAX1-NEXT: vle8.v v27, (a0)
-; LMULMAX1-NEXT: vdivu.vv v25, v25, v26
-; LMULMAX1-NEXT: vdivu.vv v26, v27, v26
-; LMULMAX1-NEXT: vse8.v v26, (a0)
-; LMULMAX1-NEXT: vse8.v v25, (a1)
+; LMULMAX1-NEXT: vle8.v v9, (a2)
+; LMULMAX1-NEXT: vle8.v v10, (a0)
+; LMULMAX1-NEXT: vdivu.vv v8, v8, v9
+; LMULMAX1-NEXT: vdivu.vv v9, v10, v9
+; LMULMAX1-NEXT: vse8.v v9, (a0)
+; LMULMAX1-NEXT: vse8.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = udiv <32 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25>
@@ -4111,94 +4111,94 @@ define void @mulhu_v16i16(<16 x i16>* %x) {
; LMULMAX2-RV32-LABEL: mulhu_v16i16:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV32-NEXT: lui a1, 2
; LMULMAX2-RV32-NEXT: addi a1, a1, 289
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.i v28, 3
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 2, v0
+; LMULMAX2-RV32-NEXT: vmv.v.i v8, 3
+; LMULMAX2-RV32-NEXT: vmerge.vim v12, v8, 2, v0
; LMULMAX2-RV32-NEXT: lui a1, 4
; LMULMAX2-RV32-NEXT: addi a1, a1, 64
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.s.x v25, a1
+; LMULMAX2-RV32-NEXT: vmv.s.x v8, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv1r.v v0, v25
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0
+; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
+; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV32-NEXT: addi a1, zero, 257
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.i v30, 0
+; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI130_0)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI130_0)
-; LMULMAX2-RV32-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV32-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV32-NEXT: lui a1, 1048568
-; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v30, a1, v0
-; LMULMAX2-RV32-NEXT: vmv1r.v v0, v25
-; LMULMAX2-RV32-NEXT: vmerge.vim v30, v30, 1, v0
-; LMULMAX2-RV32-NEXT: vsrl.vv v30, v26, v30
-; LMULMAX2-RV32-NEXT: vmulhu.vv v30, v30, v8
-; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v10
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v30
-; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vmerge.vxm v18, v14, a1, v0
+; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
+; LMULMAX2-RV32-NEXT: vmerge.vim v8, v14, 1, v0
+; LMULMAX2-RV32-NEXT: vsrl.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v16
+; LMULMAX2-RV32-NEXT: vsub.vv v10, v10, v8
+; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v18
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v12
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: mulhu_v16i16:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV64-NEXT: lui a1, 2
; LMULMAX2-RV64-NEXT: addiw a1, a1, 289
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.i v28, 3
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 2, v0
+; LMULMAX2-RV64-NEXT: vmv.v.i v8, 3
+; LMULMAX2-RV64-NEXT: vmerge.vim v12, v8, 2, v0
; LMULMAX2-RV64-NEXT: lui a1, 4
; LMULMAX2-RV64-NEXT: addiw a1, a1, 64
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.s.x v25, a1
+; LMULMAX2-RV64-NEXT: vmv.s.x v8, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv1r.v v0, v25
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 1, v0
+; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8
+; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV64-NEXT: addi a1, zero, 257
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.i v30, 0
+; LMULMAX2-RV64-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI130_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI130_0)
-; LMULMAX2-RV64-NEXT: vle16.v v8, (a1)
+; LMULMAX2-RV64-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV64-NEXT: lui a1, 1048568
-; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v30, a1, v0
-; LMULMAX2-RV64-NEXT: vmv1r.v v0, v25
-; LMULMAX2-RV64-NEXT: vmerge.vim v30, v30, 1, v0
-; LMULMAX2-RV64-NEXT: vsrl.vv v30, v26, v30
-; LMULMAX2-RV64-NEXT: vmulhu.vv v30, v30, v8
-; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v10
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmerge.vxm v18, v14, a1, v0
+; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8
+; LMULMAX2-RV64-NEXT: vmerge.vim v8, v14, 1, v0
+; LMULMAX2-RV64-NEXT: vsrl.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v16
+; LMULMAX2-RV64-NEXT: vsub.vv v10, v10, v8
+; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v18
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v12
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-LABEL: mulhu_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle16.v v25, (a1)
+; LMULMAX1-NEXT: vle16.v v8, (a1)
; LMULMAX1-NEXT: lui a2, %hi(.LCPI130_0)
; LMULMAX1-NEXT: addi a2, a2, %lo(.LCPI130_0)
-; LMULMAX1-NEXT: vle16.v v26, (a2)
-; LMULMAX1-NEXT: vle16.v v27, (a0)
-; LMULMAX1-NEXT: vdivu.vv v25, v25, v26
-; LMULMAX1-NEXT: vdivu.vv v26, v27, v26
-; LMULMAX1-NEXT: vse16.v v26, (a0)
-; LMULMAX1-NEXT: vse16.v v25, (a1)
+; LMULMAX1-NEXT: vle16.v v9, (a2)
+; LMULMAX1-NEXT: vle16.v v10, (a0)
+; LMULMAX1-NEXT: vdivu.vv v8, v8, v9
+; LMULMAX1-NEXT: vdivu.vv v9, v10, v9
+; LMULMAX1-NEXT: vse16.v v9, (a0)
+; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = udiv <16 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
@@ -4210,79 +4210,79 @@ define void @mulhu_v8i32(<8 x i32>* %x) {
; LMULMAX2-LABEL: mulhu_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: addi a1, zero, 68
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.s.x v0, a1
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: lui a1, %hi(.LCPI131_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI131_0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vmv.v.i v30, 0
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vmv.v.i v12, 0
; LMULMAX2-NEXT: lui a1, 524288
-; LMULMAX2-NEXT: vmerge.vxm v30, v30, a1, v0
-; LMULMAX2-NEXT: vmulhu.vv v28, v26, v28
-; LMULMAX2-NEXT: vsub.vv v26, v26, v28
-; LMULMAX2-NEXT: vmulhu.vv v26, v26, v30
-; LMULMAX2-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-NEXT: vmerge.vxm v12, v12, a1, v0
+; LMULMAX2-NEXT: vmulhu.vv v10, v8, v10
+; LMULMAX2-NEXT: vsub.vv v8, v8, v10
+; LMULMAX2-NEXT: vmulhu.vv v8, v8, v12
+; LMULMAX2-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-NEXT: addi a1, zero, 136
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.s.x v0, a1
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.i v28, 2
-; LMULMAX2-NEXT: vmerge.vim v28, v28, 1, v0
-; LMULMAX2-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vmv.v.i v10, 2
+; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
+; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhu_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: lui a2, 524288
-; LMULMAX1-RV32-NEXT: vmv.s.x v27, a2
-; LMULMAX1-RV32-NEXT: vmv.v.i v28, 0
+; LMULMAX1-RV32-NEXT: vmv.s.x v10, a2
+; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0
; LMULMAX1-RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; LMULMAX1-RV32-NEXT: vslideup.vi v28, v27, 2
+; LMULMAX1-RV32-NEXT: vslideup.vi v11, v10, 2
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_0)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV32-NEXT: vmulhu.vv v29, v26, v27
-; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v29
-; LMULMAX1-RV32-NEXT: vmulhu.vv v26, v26, v28
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v29
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV32-NEXT: vmulhu.vv v12, v9, v10
+; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v12
+; LMULMAX1-RV32-NEXT: vmulhu.vv v9, v9, v11
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: addi a2, zero, 1
-; LMULMAX1-RV32-NEXT: vmv.s.x v29, a2
-; LMULMAX1-RV32-NEXT: vmv.v.i v30, 2
+; LMULMAX1-RV32-NEXT: vmv.s.x v12, a2
+; LMULMAX1-RV32-NEXT: vmv.v.i v13, 2
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; LMULMAX1-RV32-NEXT: vslideup.vi v30, v29, 3
+; LMULMAX1-RV32-NEXT: vslideup.vi v13, v12, 3
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v30
-; LMULMAX1-RV32-NEXT: vmulhu.vv v27, v25, v27
-; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vmulhu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v30
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v13
+; LMULMAX1-RV32-NEXT: vmulhu.vv v10, v8, v10
+; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vmulhu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v13
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI131_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI131_0)
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a0)
-; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v26
-; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a0)
+; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v9
+; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = udiv <8 x i32> %a, <i32 5, i32 6, i32 7, i32 9, i32 5, i32 6, i32 7, i32 9>
@@ -4294,90 +4294,90 @@ define void @mulhu_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV32-LABEL: mulhu_v4i64:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_0)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_0)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v28, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v10, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmulhu.vv v28, v26, v28
-; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v8, v10
+; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 524288
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.s.x v30, a1
-; LMULMAX2-RV32-NEXT: vmv.v.i v8, 0
+; LMULMAX2-RV32-NEXT: vmv.s.x v12, a1
+; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: vsetivli zero, 6, e32, m2, tu, mu
-; LMULMAX2-RV32-NEXT: vslideup.vi v8, v30, 5
+; LMULMAX2-RV32-NEXT: vslideup.vi v14, v12, 5
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v8
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
+; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v14
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_1)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v28, (a1)
+; LMULMAX2-RV32-NEXT: vle32.v v10, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: mulhu_v4i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi a1, zero, -1
; LMULMAX2-RV64-NEXT: slli a1, a1, 63
-; LMULMAX2-RV64-NEXT: vmv.s.x v28, a1
-; LMULMAX2-RV64-NEXT: vmv.v.i v30, 0
+; LMULMAX2-RV64-NEXT: vmv.s.x v10, a1
+; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0
; LMULMAX2-RV64-NEXT: vsetivli zero, 3, e64, m2, tu, mu
-; LMULMAX2-RV64-NEXT: vslideup.vi v30, v28, 2
+; LMULMAX2-RV64-NEXT: vslideup.vi v12, v10, 2
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX2-RV64-NEXT: vmulhu.vv v28, v26, v28
+; LMULMAX2-RV64-NEXT: vle64.v v10, (a1)
+; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_1)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_1)
-; LMULMAX2-RV64-NEXT: vle64.v v8, (a1)
-; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v30
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v8
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v14, (a1)
+; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v12
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v14
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhu_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI132_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI132_0)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a2)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27
+; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI132_1)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI132_1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a2)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhu_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a1)
-; LMULMAX1-RV64-NEXT: vmv.v.i v27, 0
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a1)
+; LMULMAX1-RV64-NEXT: vmv.v.i v10, 0
; LMULMAX1-RV64-NEXT: addi a2, zero, -1
; LMULMAX1-RV64-NEXT: slli a2, a2, 63
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
+; LMULMAX1-RV64-NEXT: vmv.s.x v10, a2
; LMULMAX1-RV64-NEXT: lui a2, 1044935
; LMULMAX1-RV64-NEXT: addiw a2, a2, 455
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
@@ -4387,7 +4387,7 @@ define void @mulhu_v4i64(<4 x i64>* %x) {
; LMULMAX1-RV64-NEXT: slli a2, a2, 13
; LMULMAX1-RV64-NEXT: addi a2, a2, 911
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2
+; LMULMAX1-RV64-NEXT: vmv.v.x v11, a2
; LMULMAX1-RV64-NEXT: lui a2, 4681
; LMULMAX1-RV64-NEXT: addiw a2, a2, 585
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
@@ -4397,15 +4397,15 @@ define void @mulhu_v4i64(<4 x i64>* %x) {
; LMULMAX1-RV64-NEXT: slli a2, a2, 13
; LMULMAX1-RV64-NEXT: addi a2, a2, 1171
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2
+; LMULMAX1-RV64-NEXT: vmv.s.x v11, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmulhu.vv v28, v26, v28
-; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v28
-; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28
-; LMULMAX1-RV64-NEXT: vid.v v27
-; LMULMAX1-RV64-NEXT: vadd.vi v28, v27, 2
-; LMULMAX1-RV64-NEXT: vsrl.vv v26, v26, v28
+; LMULMAX1-RV64-NEXT: vmulhu.vv v11, v9, v11
+; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v11
+; LMULMAX1-RV64-NEXT: vmulhu.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v11
+; LMULMAX1-RV64-NEXT: vid.v v10
+; LMULMAX1-RV64-NEXT: vadd.vi v11, v10, 2
+; LMULMAX1-RV64-NEXT: vsrl.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: lui a2, 1035469
; LMULMAX1-RV64-NEXT: addiw a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
@@ -4414,7 +4414,7 @@ define void @mulhu_v4i64(<4 x i64>* %x) {
; LMULMAX1-RV64-NEXT: addi a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -819
-; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2
+; LMULMAX1-RV64-NEXT: vmv.v.x v11, a2
; LMULMAX1-RV64-NEXT: lui a2, 1026731
; LMULMAX1-RV64-NEXT: addiw a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
@@ -4424,13 +4424,13 @@ define void @mulhu_v4i64(<4 x i64>* %x) {
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -1365
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2
+; LMULMAX1-RV64-NEXT: vmv.s.x v11, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vadd.vi v27, v27, 1
-; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vmulhu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vadd.vi v10, v10, 1
+; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>
@@ -4443,80 +4443,80 @@ define void @mulhs_v32i8(<32 x i8>* %x) {
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: addi a1, zero, 32
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle8.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi a2, zero, -123
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a2
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX2-RV32-NEXT: lui a2, 304453
; LMULMAX2-RV32-NEXT: addi a2, a2, -1452
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: addi a2, zero, 57
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a2, v0
-; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vmv.v.i v28, 7
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0
-; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a2, v0
+; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vmv.v.i v10, 7
+; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
+; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: mulhs_v32i8:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: addi a1, zero, 32
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle8.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi a2, zero, -123
-; LMULMAX2-RV64-NEXT: vmv.v.x v28, a2
+; LMULMAX2-RV64-NEXT: vmv.v.x v10, a2
; LMULMAX2-RV64-NEXT: lui a2, 304453
; LMULMAX2-RV64-NEXT: addiw a2, a2, -1452
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: addi a2, zero, 57
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmerge.vxm v28, v28, a2, v0
-; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vmv.v.i v28, 7
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 1, v0
-; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vse8.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a2, v0
+; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vmv.v.i v10, 7
+; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0
+; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhs_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a1)
; LMULMAX1-RV32-NEXT: lui a2, 5
; LMULMAX1-RV32-NEXT: addi a2, a2, -1452
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.i v27, -9
-; LMULMAX1-RV32-NEXT: vmerge.vim v27, v27, 9, v0
-; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vmv.v.i v10, -9
+; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 9, v0
+; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a1)
; LMULMAX1-RV64-NEXT: lui a2, 5
; LMULMAX1-RV64-NEXT: addiw a2, a2, -1452
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; LMULMAX1-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.i v27, -9
-; LMULMAX1-RV64-NEXT: vmerge.vim v27, v27, 9, v0
-; LMULMAX1-RV64-NEXT: vdivu.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vmv.v.i v10, -9
+; LMULMAX1-RV64-NEXT: vmerge.vim v10, v10, 9, v0
+; LMULMAX1-RV64-NEXT: vdivu.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = udiv <32 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9>
@@ -4528,7 +4528,7 @@ define void @mulhs_v16i16(<16 x i16>* %x) {
; LMULMAX2-RV32-LABEL: mulhs_v16i16:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX2-RV32-NEXT: lui a1, 7
; LMULMAX2-RV32-NEXT: addi a1, a1, -1687
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
@@ -4536,21 +4536,21 @@ define void @mulhs_v16i16(<16 x i16>* %x) {
; LMULMAX2-RV32-NEXT: lui a1, 5
; LMULMAX2-RV32-NEXT: addi a1, a1, -1755
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: lui a1, 1048571
; LMULMAX2-RV32-NEXT: addi a1, a1, 1755
-; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a1, v0
-; LMULMAX2-RV32-NEXT: vmulh.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vsra.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 15
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0
+; LMULMAX2-RV32-NEXT: vmulh.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vsra.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 15
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: mulhs_v16i16:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX2-RV64-NEXT: lui a1, 7
; LMULMAX2-RV64-NEXT: addiw a1, a1, -1687
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
@@ -4558,33 +4558,33 @@ define void @mulhs_v16i16(<16 x i16>* %x) {
; LMULMAX2-RV64-NEXT: lui a1, 5
; LMULMAX2-RV64-NEXT: addiw a1, a1, -1755
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.x v28, a1
+; LMULMAX2-RV64-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64-NEXT: lui a1, 1048571
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1755
-; LMULMAX2-RV64-NEXT: vmerge.vxm v28, v28, a1, v0
-; LMULMAX2-RV64-NEXT: vmulh.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vsra.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 15
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vse16.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a1, v0
+; LMULMAX2-RV64-NEXT: vmulh.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vsra.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 15
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-LABEL: mulhs_v16i16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vle16.v v25, (a0)
+; LMULMAX1-NEXT: vle16.v v8, (a0)
; LMULMAX1-NEXT: addi a1, a0, 16
-; LMULMAX1-NEXT: vle16.v v26, (a1)
+; LMULMAX1-NEXT: vle16.v v9, (a1)
; LMULMAX1-NEXT: addi a2, zero, 105
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.s.x v0, a2
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-NEXT: vmv.v.i v27, 7
-; LMULMAX1-NEXT: vmerge.vim v27, v27, -7, v0
-; LMULMAX1-NEXT: vdiv.vv v26, v26, v27
-; LMULMAX1-NEXT: vdiv.vv v25, v25, v27
-; LMULMAX1-NEXT: vse16.v v25, (a0)
-; LMULMAX1-NEXT: vse16.v v26, (a1)
+; LMULMAX1-NEXT: vmv.v.i v10, 7
+; LMULMAX1-NEXT: vmerge.vim v10, v10, -7, v0
+; LMULMAX1-NEXT: vdiv.vv v9, v9, v10
+; LMULMAX1-NEXT: vdiv.vv v8, v8, v10
+; LMULMAX1-NEXT: vse16.v v8, (a0)
+; LMULMAX1-NEXT: vse16.v v9, (a1)
; LMULMAX1-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = sdiv <16 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7, i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>
@@ -4596,28 +4596,28 @@ define void @mulhs_v8i32(<8 x i32>* %x) {
; LMULMAX2-RV32-LABEL: mulhs_v8i32:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle32.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi a1, zero, 85
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: lui a1, 419430
; LMULMAX2-RV32-NEXT: addi a1, a1, 1639
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: lui a1, 629146
; LMULMAX2-RV32-NEXT: addi a1, a1, -1639
-; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a1, v0
-; LMULMAX2-RV32-NEXT: vmulh.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 31
-; LMULMAX2-RV32-NEXT: vsra.vi v26, v26, 1
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0
+; LMULMAX2-RV32-NEXT: vmulh.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 31
+; LMULMAX2-RV32-NEXT: vsra.vi v8, v8, 1
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: mulhs_v8i32:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: lui a1, 13107
; LMULMAX2-RV64-NEXT: addiw a1, a1, 819
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -4627,59 +4627,59 @@ define void @mulhs_v8i32(<8 x i32>* %x) {
; LMULMAX2-RV64-NEXT: slli a1, a1, 13
; LMULMAX2-RV64-NEXT: addi a1, a1, -1639
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.x v28, a1
+; LMULMAX2-RV64-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmulh.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vsra.vi v26, v26, 1
-; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 31
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
-; LMULMAX2-RV64-NEXT: vse32.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vmulh.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vsra.vi v8, v8, 1
+; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 31
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
+; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhs_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: addi a2, zero, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX1-RV32-NEXT: lui a2, 419430
; LMULMAX1-RV32-NEXT: addi a2, a2, 1639
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v27, a2
+; LMULMAX1-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX1-RV32-NEXT: lui a2, 629146
; LMULMAX1-RV32-NEXT: addi a2, a2, -1639
-; LMULMAX1-RV32-NEXT: vmerge.vxm v27, v27, a2, v0
-; LMULMAX1-RV32-NEXT: vmulh.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v28, v26, 31
-; LMULMAX1-RV32-NEXT: vsra.vi v26, v26, 1
-; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v28
-; LMULMAX1-RV32-NEXT: vmulh.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 31
-; LMULMAX1-RV32-NEXT: vsra.vi v25, v25, 1
-; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vmerge.vxm v10, v10, a2, v0
+; LMULMAX1-RV32-NEXT: vmulh.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 31
+; LMULMAX1-RV32-NEXT: vsra.vi v9, v9, 1
+; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v11
+; LMULMAX1-RV32-NEXT: vmulh.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 31
+; LMULMAX1-RV32-NEXT: vsra.vi v8, v8, 1
+; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV64-NEXT: addi a2, zero, 3
; LMULMAX1-RV64-NEXT: slli a2, a2, 33
; LMULMAX1-RV64-NEXT: addi a2, a2, -5
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v27, a2
+; LMULMAX1-RV64-NEXT: vmv.v.x v10, a2
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vdiv.vv v26, v26, v27
-; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v27
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vdiv.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = sdiv <8 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5>
@@ -4691,50 +4691,50 @@ define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV32-LABEL: mulhs_v4i64:
; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi a1, zero, 17
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a2, a1, 1365
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.x v28, a2
+; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX2-RV32-NEXT: addi a1, a1, 1366
-; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a1, v0
+; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmulh.vv v28, v26, v28
+; LMULMAX2-RV32-NEXT: vmulh.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: addi a1, zero, 51
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.i v30, -1
-; LMULMAX2-RV32-NEXT: vmerge.vim v30, v30, 0, v0
+; LMULMAX2-RV32-NEXT: vmv.v.i v12, -1
+; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmadd.vv v30, v26, v28
+; LMULMAX2-RV32-NEXT: vmadd.vv v12, v8, v10
; LMULMAX2-RV32-NEXT: addi a1, zero, 63
-; LMULMAX2-RV32-NEXT: vsrl.vx v26, v30, a1
+; LMULMAX2-RV32-NEXT: vsrl.vx v8, v12, a1
; LMULMAX2-RV32-NEXT: addi a1, zero, 68
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vmv.v.i v28, 0
-; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0
+; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0
+; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV32-NEXT: vsra.vv v28, v30, v28
-; LMULMAX2-RV32-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT: vsra.vv v10, v12, v10
+; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret
;
; LMULMAX2-RV64-LABEL: mulhs_v4i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: addi a1, zero, 5
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vmv.v.i v28, -1
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 0, v0
+; LMULMAX2-RV64-NEXT: vmv.v.i v10, -1
+; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX2-RV64-NEXT: lui a1, 21845
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
@@ -4743,43 +4743,43 @@ define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV64-NEXT: addi a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a1, a1, 12
; LMULMAX2-RV64-NEXT: addi a2, a1, 1365
-; LMULMAX2-RV64-NEXT: vmv.v.x v30, a2
+; LMULMAX2-RV64-NEXT: vmv.v.x v12, a2
; LMULMAX2-RV64-NEXT: addi a1, a1, 1366
-; LMULMAX2-RV64-NEXT: vmerge.vxm v30, v30, a1, v0
-; LMULMAX2-RV64-NEXT: vmulh.vv v30, v26, v30
-; LMULMAX2-RV64-NEXT: vmacc.vv v30, v26, v28
+; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v12, a1, v0
+; LMULMAX2-RV64-NEXT: vmulh.vv v12, v8, v12
+; LMULMAX2-RV64-NEXT: vmacc.vv v12, v8, v10
; LMULMAX2-RV64-NEXT: addi a1, zero, 63
-; LMULMAX2-RV64-NEXT: vsrl.vx v26, v30, a1
-; LMULMAX2-RV64-NEXT: vmv.v.i v28, 1
-; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 0, v0
-; LMULMAX2-RV64-NEXT: vsra.vv v28, v30, v28
-; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26
-; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
+; LMULMAX2-RV64-NEXT: vsrl.vx v8, v12, a1
+; LMULMAX2-RV64-NEXT: vmv.v.i v10, 1
+; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0
+; LMULMAX2-RV64-NEXT: vsra.vv v10, v12, v10
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
; LMULMAX1-RV32-LABEL: mulhs_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI136_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI136_0)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a2)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a1)
+; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v10
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: mulhs_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV64-NEXT: lui a2, 21845
; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
@@ -4788,26 +4788,26 @@ define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX1-RV64-NEXT: addi a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a3, a2, 1365
-; LMULMAX1-RV64-NEXT: vmv.v.x v27, a3
+; LMULMAX1-RV64-NEXT: vmv.v.x v10, a3
; LMULMAX1-RV64-NEXT: addi a2, a2, 1366
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
+; LMULMAX1-RV64-NEXT: vmv.s.x v10, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmulh.vv v28, v26, v27
-; LMULMAX1-RV64-NEXT: vid.v v29
-; LMULMAX1-RV64-NEXT: vrsub.vi v30, v29, 0
-; LMULMAX1-RV64-NEXT: vmacc.vv v28, v30, v26
+; LMULMAX1-RV64-NEXT: vmulh.vv v11, v9, v10
+; LMULMAX1-RV64-NEXT: vid.v v12
+; LMULMAX1-RV64-NEXT: vrsub.vi v13, v12, 0
+; LMULMAX1-RV64-NEXT: vmacc.vv v11, v13, v9
; LMULMAX1-RV64-NEXT: addi a2, zero, 63
-; LMULMAX1-RV64-NEXT: vsrl.vx v26, v28, a2
-; LMULMAX1-RV64-NEXT: vsra.vv v28, v28, v29
-; LMULMAX1-RV64-NEXT: vadd.vv v26, v28, v26
-; LMULMAX1-RV64-NEXT: vmulh.vv v27, v25, v27
-; LMULMAX1-RV64-NEXT: vmacc.vv v27, v25, v30
-; LMULMAX1-RV64-NEXT: vsrl.vx v25, v27, a2
-; LMULMAX1-RV64-NEXT: vsra.vv v27, v27, v29
-; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a1)
+; LMULMAX1-RV64-NEXT: vsrl.vx v9, v11, a2
+; LMULMAX1-RV64-NEXT: vsra.vv v11, v11, v12
+; LMULMAX1-RV64-NEXT: vadd.vv v9, v11, v9
+; LMULMAX1-RV64-NEXT: vmulh.vv v10, v8, v10
+; LMULMAX1-RV64-NEXT: vmacc.vv v10, v8, v13
+; LMULMAX1-RV64-NEXT: vsrl.vx v8, v10, a2
+; LMULMAX1-RV64-NEXT: vsra.vv v10, v10, v12
+; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>
@@ -4820,40 +4820,40 @@ define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vmin.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vmin.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smin_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smin_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -4867,40 +4867,40 @@ define void @smin_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: smin_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vmin.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vmin.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smin_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smin_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -4914,40 +4914,40 @@ define void @smin_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: smin_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vmin.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vmin.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smin_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smin_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -4961,40 +4961,40 @@ define void @smin_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: smin_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vmin.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vmin.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smin_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smin_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -5009,40 +5009,40 @@ define void @smax_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smax_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smax_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -5056,40 +5056,40 @@ define void @smax_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: smax_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smax_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smax_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -5103,40 +5103,40 @@ define void @smax_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: smax_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smax_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smax_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -5150,40 +5150,40 @@ define void @smax_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: smax_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vmax.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vmax.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: smax_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: smax_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -5198,40 +5198,40 @@ define void @umin_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vminu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vminu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umin_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umin_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -5245,40 +5245,40 @@ define void @umin_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: umin_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vminu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vminu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umin_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umin_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -5292,40 +5292,40 @@ define void @umin_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: umin_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vminu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vminu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umin_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umin_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -5339,40 +5339,40 @@ define void @umin_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: umin_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vminu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vminu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umin_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umin_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -5387,40 +5387,40 @@ define void @umax_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle8.v v26, (a0)
-; LMULMAX2-NEXT: vle8.v v28, (a1)
-; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse8.v v26, (a0)
+; LMULMAX2-NEXT: vle8.v v8, (a0)
+; LMULMAX2-NEXT: vle8.v v10, (a1)
+; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umax_v32i8:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle8.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle8.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umax_v32i8:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle8.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle8.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle8.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse8.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse8.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle8.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse8.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse8.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -5434,40 +5434,40 @@ define void @umax_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
; LMULMAX2-LABEL: umax_v16i16:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; LMULMAX2-NEXT: vle16.v v26, (a0)
-; LMULMAX2-NEXT: vle16.v v28, (a1)
-; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse16.v v26, (a0)
+; LMULMAX2-NEXT: vle16.v v8, (a0)
+; LMULMAX2-NEXT: vle16.v v10, (a1)
+; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umax_v16i16:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle16.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle16.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umax_v16i16:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle16.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle16.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle16.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle16.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse16.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse16.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle16.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse16.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse16.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -5481,40 +5481,40 @@ define void @umax_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX2-LABEL: umax_v8i32:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; LMULMAX2-NEXT: vle32.v v26, (a0)
-; LMULMAX2-NEXT: vle32.v v28, (a1)
-; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse32.v v26, (a0)
+; LMULMAX2-NEXT: vle32.v v8, (a0)
+; LMULMAX2-NEXT: vle32.v v10, (a1)
+; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umax_v8i32:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle32.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle32.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umax_v8i32:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle32.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle32.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle32.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse32.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse32.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle32.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse32.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -5528,40 +5528,40 @@ define void @umax_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-LABEL: umax_v4i64:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-NEXT: vle64.v v26, (a0)
-; LMULMAX2-NEXT: vle64.v v28, (a1)
-; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28
-; LMULMAX2-NEXT: vse64.v v26, (a0)
+; LMULMAX2-NEXT: vle64.v v8, (a0)
+; LMULMAX2-NEXT: vle64.v v10, (a1)
+; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10
+; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: umax_v4i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a2, a0, 16
-; LMULMAX1-RV32-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV32-NEXT: addi a3, a1, 16
-; LMULMAX1-RV32-NEXT: vle64.v v27, (a3)
-; LMULMAX1-RV32-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27
-; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV32-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV32-NEXT: vle64.v v10, (a3)
+; LMULMAX1-RV32-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10
+; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV32-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: umax_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a2, a1, 16
-; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v9, (a2)
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
-; LMULMAX1-RV64-NEXT: vle64.v v27, (a2)
-; LMULMAX1-RV64-NEXT: vle64.v v28, (a1)
-; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26
-; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28
-; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
+; LMULMAX1-RV64-NEXT: vle64.v v11, (a1)
+; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9
+; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
+; LMULMAX1-RV64-NEXT: vse64.v v9, (a2)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y
@@ -5575,9 +5575,9 @@ define void @add_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: add_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, -1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, -1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 -1, i32 0
@@ -5591,9 +5591,9 @@ define void @add_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: add_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, -1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, -1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 -1, i32 0
@@ -5607,9 +5607,9 @@ define void @add_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: add_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, -1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, -1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 -1, i32 0
@@ -5623,9 +5623,9 @@ define void @add_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: add_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, -1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, -1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 -1, i32 0
@@ -5639,9 +5639,9 @@ define void @add_iv_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: add_iv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, 1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, 1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 1, i32 0
@@ -5655,9 +5655,9 @@ define void @add_iv_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: add_iv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, 1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, 1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 1, i32 0
@@ -5671,9 +5671,9 @@ define void @add_iv_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: add_iv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, 1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, 1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 1, i32 0
@@ -5687,9 +5687,9 @@ define void @add_iv_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: add_iv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vadd.vi v25, v25, 1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vadd.vi v8, v8, 1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 1, i32 0
@@ -5703,9 +5703,9 @@ define void @add_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: add_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -5719,9 +5719,9 @@ define void @add_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: add_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -5735,9 +5735,9 @@ define void @add_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: add_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -5751,9 +5751,9 @@ define void @add_xv_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: add_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -5767,9 +5767,9 @@ define void @add_xv_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: add_xv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -5783,9 +5783,9 @@ define void @add_xv_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: add_xv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -5799,10 +5799,10 @@ define void @sub_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: sub_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a1, zero, -1
-; CHECK-NEXT: vsub.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 -1, i32 0
@@ -5816,10 +5816,10 @@ define void @sub_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: sub_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a1, zero, -1
-; CHECK-NEXT: vsub.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 -1, i32 0
@@ -5833,10 +5833,10 @@ define void @sub_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: sub_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a1, zero, -1
-; CHECK-NEXT: vsub.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 -1, i32 0
@@ -5850,10 +5850,10 @@ define void @sub_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: sub_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a1, zero, -1
-; CHECK-NEXT: vsub.vx v25, v25, a1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 -1, i32 0
@@ -5867,9 +5867,9 @@ define void @sub_iv_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: sub_iv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v25, v25, 1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v8, v8, 1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 1, i32 0
@@ -5883,9 +5883,9 @@ define void @sub_iv_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: sub_iv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v25, v25, 1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v8, v8, 1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 1, i32 0
@@ -5899,9 +5899,9 @@ define void @sub_iv_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: sub_iv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v25, v25, 1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v8, v8, 1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 1, i32 0
@@ -5915,9 +5915,9 @@ define void @sub_iv_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: sub_iv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vrsub.vi v25, v25, 1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vrsub.vi v8, v8, 1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 1, i32 0
@@ -5931,9 +5931,9 @@ define void @sub_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: sub_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsub.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -5947,9 +5947,9 @@ define void @sub_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: sub_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vsub.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -5963,9 +5963,9 @@ define void @sub_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: sub_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsub.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -5979,9 +5979,9 @@ define void @sub_xv_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: sub_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vrsub.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vrsub.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -5995,9 +5995,9 @@ define void @sub_xv_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: sub_xv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vrsub.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vrsub.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6011,9 +6011,9 @@ define void @sub_xv_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: sub_xv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vrsub.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vrsub.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6027,9 +6027,9 @@ define void @mul_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: mul_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6043,9 +6043,9 @@ define void @mul_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: mul_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6059,9 +6059,9 @@ define void @mul_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: mul_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6075,9 +6075,9 @@ define void @mul_xv_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: mul_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6091,9 +6091,9 @@ define void @mul_xv_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: mul_xv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6107,9 +6107,9 @@ define void @mul_xv_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: mul_xv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6123,9 +6123,9 @@ define void @and_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: and_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, -2
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, -2
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 -2, i32 0
@@ -6139,9 +6139,9 @@ define void @and_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: and_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, -2
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, -2
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 -2, i32 0
@@ -6155,9 +6155,9 @@ define void @and_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: and_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, -2
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, -2
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 -2, i32 0
@@ -6171,9 +6171,9 @@ define void @and_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: and_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, -2
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, -2
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 -2, i32 0
@@ -6187,9 +6187,9 @@ define void @and_iv_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: and_iv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 1, i32 0
@@ -6203,9 +6203,9 @@ define void @and_iv_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: and_iv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 1, i32 0
@@ -6219,9 +6219,9 @@ define void @and_iv_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: and_iv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 1, i32 0
@@ -6235,9 +6235,9 @@ define void @and_iv_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: and_iv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 1, i32 0
@@ -6251,9 +6251,9 @@ define void @and_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: and_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6267,9 +6267,9 @@ define void @and_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: and_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6283,9 +6283,9 @@ define void @and_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: and_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6299,9 +6299,9 @@ define void @and_xv_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: and_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6315,9 +6315,9 @@ define void @and_xv_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: and_xv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6331,9 +6331,9 @@ define void @and_xv_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: and_xv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6347,9 +6347,9 @@ define void @or_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: or_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, -2
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, -2
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 -2, i32 0
@@ -6363,9 +6363,9 @@ define void @or_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: or_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, -2
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, -2
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 -2, i32 0
@@ -6379,9 +6379,9 @@ define void @or_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: or_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, -2
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, -2
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 -2, i32 0
@@ -6395,9 +6395,9 @@ define void @or_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: or_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, -2
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, -2
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 -2, i32 0
@@ -6411,9 +6411,9 @@ define void @or_iv_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: or_iv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, 1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, 1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 1, i32 0
@@ -6427,9 +6427,9 @@ define void @or_iv_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: or_iv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, 1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, 1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 1, i32 0
@@ -6443,9 +6443,9 @@ define void @or_iv_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: or_iv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, 1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, 1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 1, i32 0
@@ -6459,9 +6459,9 @@ define void @or_iv_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: or_iv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vor.vi v25, v25, 1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vor.vi v8, v8, 1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 1, i32 0
@@ -6475,9 +6475,9 @@ define void @or_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: or_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vor.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6491,9 +6491,9 @@ define void @or_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: or_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vor.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6507,9 +6507,9 @@ define void @or_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: or_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vor.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6523,9 +6523,9 @@ define void @or_xv_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: or_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vor.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6539,9 +6539,9 @@ define void @or_xv_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: or_xv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vor.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6555,9 +6555,9 @@ define void @or_xv_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: or_xv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vor.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6571,9 +6571,9 @@ define void @xor_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: xor_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, -1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, -1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 -1, i32 0
@@ -6587,9 +6587,9 @@ define void @xor_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: xor_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, -1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, -1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 -1, i32 0
@@ -6603,9 +6603,9 @@ define void @xor_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: xor_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, -1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, -1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 -1, i32 0
@@ -6619,9 +6619,9 @@ define void @xor_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: xor_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, -1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, -1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 -1, i32 0
@@ -6635,9 +6635,9 @@ define void @xor_iv_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: xor_iv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, 1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, 1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 1, i32 0
@@ -6651,9 +6651,9 @@ define void @xor_iv_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: xor_iv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, 1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, 1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 1, i32 0
@@ -6667,9 +6667,9 @@ define void @xor_iv_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: xor_iv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, 1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, 1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 1, i32 0
@@ -6683,9 +6683,9 @@ define void @xor_iv_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: xor_iv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vxor.vi v25, v25, 1
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vxor.vi v8, v8, 1
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 1, i32 0
@@ -6699,9 +6699,9 @@ define void @xor_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: xor_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vxor.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6715,9 +6715,9 @@ define void @xor_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: xor_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vxor.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6731,9 +6731,9 @@ define void @xor_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: xor_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vxor.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6747,9 +6747,9 @@ define void @xor_xv_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: xor_xv_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vxor.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6763,9 +6763,9 @@ define void @xor_xv_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: xor_xv_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vxor.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6779,9 +6779,9 @@ define void @xor_xv_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: xor_xv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vxor.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6795,9 +6795,9 @@ define void @lshr_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: lshr_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsrl.vi v25, v25, 7
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsrl.vi v8, v8, 7
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 7, i32 0
@@ -6811,9 +6811,9 @@ define void @lshr_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: lshr_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vsrl.vi v25, v25, 15
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsrl.vi v8, v8, 15
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 15, i32 0
@@ -6827,9 +6827,9 @@ define void @lshr_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: lshr_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsrl.vi v25, v25, 31
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsrl.vi v8, v8, 31
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 31, i32 0
@@ -6843,9 +6843,9 @@ define void @lshr_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: lshr_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vsrl.vi v25, v25, 31
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsrl.vi v8, v8, 31
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 31, i32 0
@@ -6859,9 +6859,9 @@ define void @lshr_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: lshr_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6875,9 +6875,9 @@ define void @lshr_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: lshr_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -6891,9 +6891,9 @@ define void @lshr_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: lshr_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -6907,9 +6907,9 @@ define void @ashr_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: ashr_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsra.vi v25, v25, 7
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsra.vi v8, v8, 7
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 7, i32 0
@@ -6923,9 +6923,9 @@ define void @ashr_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: ashr_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vsra.vi v25, v25, 15
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsra.vi v8, v8, 15
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 15, i32 0
@@ -6939,9 +6939,9 @@ define void @ashr_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: ashr_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsra.vi v25, v25, 31
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsra.vi v8, v8, 31
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 31, i32 0
@@ -6955,9 +6955,9 @@ define void @ashr_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: ashr_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vsra.vi v25, v25, 31
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsra.vi v8, v8, 31
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 31, i32 0
@@ -6971,9 +6971,9 @@ define void @ashr_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: ashr_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsra.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsra.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -6987,9 +6987,9 @@ define void @ashr_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: ashr_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vsra.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsra.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -7003,9 +7003,9 @@ define void @ashr_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: ashr_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsra.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsra.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -7019,9 +7019,9 @@ define void @shl_vi_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: shl_vi_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsll.vi v25, v25, 7
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsll.vi v8, v8, 7
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 7, i32 0
@@ -7035,9 +7035,9 @@ define void @shl_vi_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: shl_vi_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vsll.vi v25, v25, 15
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsll.vi v8, v8, 15
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 15, i32 0
@@ -7051,9 +7051,9 @@ define void @shl_vi_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: shl_vi_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsll.vi v25, v25, 31
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsll.vi v8, v8, 31
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 31, i32 0
@@ -7067,9 +7067,9 @@ define void @shl_vi_v2i64(<2 x i64>* %x) {
; CHECK-LABEL: shl_vi_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vsll.vi v25, v25, 31
-; CHECK-NEXT: vse64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsll.vi v8, v8, 31
+; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = insertelement <2 x i64> undef, i64 31, i32 0
@@ -7083,9 +7083,9 @@ define void @shl_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: shl_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vsll.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -7099,9 +7099,9 @@ define void @shl_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: shl_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vsll.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -7115,9 +7115,9 @@ define void @shl_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: shl_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsll.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -7131,9 +7131,9 @@ define void @sdiv_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: sdiv_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vdiv.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vdiv.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -7147,9 +7147,9 @@ define void @sdiv_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: sdiv_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vdiv.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vdiv.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -7163,9 +7163,9 @@ define void @sdiv_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: sdiv_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vdiv.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vdiv.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -7179,9 +7179,9 @@ define void @srem_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: srem_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vrem.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vrem.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -7195,9 +7195,9 @@ define void @srem_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: srem_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vrem.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vrem.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -7211,9 +7211,9 @@ define void @srem_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: srem_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vrem.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vrem.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -7227,9 +7227,9 @@ define void @udiv_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: udiv_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vdivu.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vdivu.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -7243,9 +7243,9 @@ define void @udiv_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: udiv_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vdivu.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vdivu.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -7259,9 +7259,9 @@ define void @udiv_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: udiv_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vdivu.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vdivu.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -7275,9 +7275,9 @@ define void @urem_vx_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: urem_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vremu.vx v25, v25, a1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vremu.vx v8, v8, a1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -7291,9 +7291,9 @@ define void @urem_vx_v8i16(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: urem_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vremu.vx v25, v25, a1
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vremu.vx v8, v8, a1
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -7307,9 +7307,9 @@ define void @urem_vx_v4i32(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: urem_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vremu.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vremu.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i32 0
@@ -7323,11 +7323,11 @@ define void @mulhu_vx_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: mulhu_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a1, zero, 57
-; CHECK-NEXT: vmulhu.vx v25, v25, a1
-; CHECK-NEXT: vsrl.vi v25, v25, 1
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vmulhu.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9>
@@ -7339,29 +7339,29 @@ define void @mulhu_vx_v8i16(<8 x i16>* %x) {
; RV32-LABEL: mulhu_vx_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: lui a1, 2
; RV32-NEXT: addi a1, a1, 1171
-; RV32-NEXT: vmulhu.vx v26, v25, a1
-; RV32-NEXT: vsub.vv v25, v25, v26
-; RV32-NEXT: vsrl.vi v25, v25, 1
-; RV32-NEXT: vadd.vv v25, v25, v26
-; RV32-NEXT: vsrl.vi v25, v25, 2
-; RV32-NEXT: vse16.v v25, (a0)
+; RV32-NEXT: vmulhu.vx v9, v8, a1
+; RV32-NEXT: vsub.vv v8, v8, v9
+; RV32-NEXT: vsrl.vi v8, v8, 1
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: vsrl.vi v8, v8, 2
+; RV32-NEXT: vse16.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhu_vx_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64-NEXT: vle16.v v25, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: lui a1, 2
; RV64-NEXT: addiw a1, a1, 1171
-; RV64-NEXT: vmulhu.vx v26, v25, a1
-; RV64-NEXT: vsub.vv v25, v25, v26
-; RV64-NEXT: vsrl.vi v25, v25, 1
-; RV64-NEXT: vadd.vv v25, v25, v26
-; RV64-NEXT: vsrl.vi v25, v25, 2
-; RV64-NEXT: vse16.v v25, (a0)
+; RV64-NEXT: vmulhu.vx v9, v8, a1
+; RV64-NEXT: vsub.vv v8, v8, v9
+; RV64-NEXT: vsrl.vi v8, v8, 1
+; RV64-NEXT: vadd.vv v8, v8, v9
+; RV64-NEXT: vsrl.vi v8, v8, 2
+; RV64-NEXT: vse16.v v8, (a0)
; RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -7373,23 +7373,23 @@ define void @mulhu_vx_v4i32(<4 x i32>* %x) {
; RV32-LABEL: mulhu_vx_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: lui a1, 838861
; RV32-NEXT: addi a1, a1, -819
-; RV32-NEXT: vmulhu.vx v25, v25, a1
-; RV32-NEXT: vsrl.vi v25, v25, 2
-; RV32-NEXT: vse32.v v25, (a0)
+; RV32-NEXT: vmulhu.vx v8, v8, a1
+; RV32-NEXT: vsrl.vi v8, v8, 2
+; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhu_vx_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: lui a1, 838861
; RV64-NEXT: addiw a1, a1, -819
-; RV64-NEXT: vmulhu.vx v25, v25, a1
-; RV64-NEXT: vsrl.vi v25, v25, 2
-; RV64-NEXT: vse32.v v25, (a0)
+; RV64-NEXT: vmulhu.vx v8, v8, a1
+; RV64-NEXT: vsrl.vi v8, v8, 2
+; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = udiv <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
@@ -7403,24 +7403,24 @@ define void @mulhu_vx_v2i64(<2 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a1, 699051
; RV32-NEXT: addi a2, a1, -1366
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: addi a1, a1, -1365
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a1, sp, 8
-; RV32-NEXT: vlse64.v v26, (a1), zero
-; RV32-NEXT: vmulhu.vv v25, v25, v26
-; RV32-NEXT: vsrl.vi v25, v25, 1
-; RV32-NEXT: vse64.v v25, (a0)
+; RV32-NEXT: vlse64.v v9, (a1), zero
+; RV32-NEXT: vmulhu.vv v8, v8, v9
+; RV32-NEXT: vsrl.vi v8, v8, 1
+; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: mulhu_vx_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: lui a1, 1026731
; RV64-NEXT: addiw a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12
@@ -7429,9 +7429,9 @@ define void @mulhu_vx_v2i64(<2 x i64>* %x) {
; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365
-; RV64-NEXT: vmulhu.vx v25, v25, a1
-; RV64-NEXT: vsrl.vi v25, v25, 1
-; RV64-NEXT: vse64.v v25, (a0)
+; RV64-NEXT: vmulhu.vx v8, v8, a1
+; RV64-NEXT: vsrl.vi v8, v8, 1
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = udiv <2 x i64> %a, <i64 3, i64 3>
@@ -7443,11 +7443,11 @@ define void @mulhs_vx_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: mulhs_vx_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a1, zero, -123
-; CHECK-NEXT: vmulhu.vx v25, v25, a1
-; CHECK-NEXT: vsrl.vi v25, v25, 7
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vmulhu.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vi v8, v8, 7
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9>
@@ -7459,27 +7459,27 @@ define void @mulhs_vx_v8i16(<8 x i16>* %x) {
; RV32-LABEL: mulhs_vx_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: lui a1, 5
; RV32-NEXT: addi a1, a1, -1755
-; RV32-NEXT: vmulh.vx v25, v25, a1
-; RV32-NEXT: vsra.vi v25, v25, 1
-; RV32-NEXT: vsrl.vi v26, v25, 15
-; RV32-NEXT: vadd.vv v25, v25, v26
-; RV32-NEXT: vse16.v v25, (a0)
+; RV32-NEXT: vmulh.vx v8, v8, a1
+; RV32-NEXT: vsra.vi v8, v8, 1
+; RV32-NEXT: vsrl.vi v9, v8, 15
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: vse16.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhs_vx_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64-NEXT: vle16.v v25, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: lui a1, 5
; RV64-NEXT: addiw a1, a1, -1755
-; RV64-NEXT: vmulh.vx v25, v25, a1
-; RV64-NEXT: vsra.vi v25, v25, 1
-; RV64-NEXT: vsrl.vi v26, v25, 15
-; RV64-NEXT: vadd.vv v25, v25, v26
-; RV64-NEXT: vse16.v v25, (a0)
+; RV64-NEXT: vmulh.vx v8, v8, a1
+; RV64-NEXT: vsra.vi v8, v8, 1
+; RV64-NEXT: vsrl.vi v9, v8, 15
+; RV64-NEXT: vadd.vv v8, v8, v9
+; RV64-NEXT: vse16.v v8, (a0)
; RV64-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
@@ -7491,27 +7491,27 @@ define void @mulhs_vx_v4i32(<4 x i32>* %x) {
; RV32-LABEL: mulhs_vx_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: lui a1, 629146
; RV32-NEXT: addi a1, a1, -1639
-; RV32-NEXT: vmulh.vx v25, v25, a1
-; RV32-NEXT: vsrl.vi v26, v25, 31
-; RV32-NEXT: vsra.vi v25, v25, 1
-; RV32-NEXT: vadd.vv v25, v25, v26
-; RV32-NEXT: vse32.v v25, (a0)
+; RV32-NEXT: vmulh.vx v8, v8, a1
+; RV32-NEXT: vsrl.vi v9, v8, 31
+; RV32-NEXT: vsra.vi v8, v8, 1
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: mulhs_vx_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: lui a1, 629146
; RV64-NEXT: addiw a1, a1, -1639
-; RV64-NEXT: vmulh.vx v25, v25, a1
-; RV64-NEXT: vsra.vi v25, v25, 1
-; RV64-NEXT: vsrl.vi v26, v25, 31
-; RV64-NEXT: vadd.vv v25, v25, v26
-; RV64-NEXT: vse32.v v25, (a0)
+; RV64-NEXT: vmulh.vx v8, v8, a1
+; RV64-NEXT: vsra.vi v8, v8, 1
+; RV64-NEXT: vsrl.vi v9, v8, 31
+; RV64-NEXT: vadd.vv v8, v8, v9
+; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = sdiv <4 x i32> %a, <i32 -5, i32 -5, i32 -5, i32 -5>
@@ -7525,26 +7525,26 @@ define void @mulhs_vx_v2i64(<2 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a2, a1, 1365
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: addi a1, a1, 1366
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a1, sp, 8
-; RV32-NEXT: vlse64.v v26, (a1), zero
-; RV32-NEXT: vmulh.vv v25, v25, v26
+; RV32-NEXT: vlse64.v v9, (a1), zero
+; RV32-NEXT: vmulh.vv v8, v8, v9
; RV32-NEXT: addi a1, zero, 63
-; RV32-NEXT: vsrl.vx v26, v25, a1
-; RV32-NEXT: vadd.vv v25, v25, v26
-; RV32-NEXT: vse64.v v25, (a0)
+; RV32-NEXT: vsrl.vx v9, v8, a1
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: mulhs_vx_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: lui a1, 21845
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12
@@ -7553,11 +7553,11 @@ define void @mulhs_vx_v2i64(<2 x i64>* %x) {
; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, 1366
-; RV64-NEXT: vmulh.vx v25, v25, a1
+; RV64-NEXT: vmulh.vx v8, v8, a1
; RV64-NEXT: addi a1, zero, 63
-; RV64-NEXT: vsrl.vx v26, v25, a1
-; RV64-NEXT: vadd.vv v25, v25, v26
-; RV64-NEXT: vse64.v v25, (a0)
+; RV64-NEXT: vsrl.vx v9, v8, a1
+; RV64-NEXT: vadd.vv v8, v8, v9
+; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x
%b = sdiv <2 x i64> %a, <i64 3, i64 3>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
index cb81fc9fa5ae2..6b45283d3b84d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -13,8 +13,8 @@ define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%1 = insertelement <1 x i1> undef, i1 %x, i32 0
ret <1 x i1> %1
@@ -25,8 +25,8 @@ define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%1 = insertelement <1 x i1> undef, i1 %x, i32 0
ret <1 x i1> %1
@@ -36,12 +36,12 @@ define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%1 = insertelement <2 x i1> undef, i1 %x, i32 0
%2 = insertelement <2 x i1> %1, i1 %y, i32 1
@@ -58,9 +58,9 @@ define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize {
; CHECK-NEXT: sb a0, 14(sp)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: addi a0, sp, 14
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%1 = insertelement <2 x i1> undef, i1 %x, i32 0
@@ -105,10 +105,10 @@ define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%1 = insertelement <4 x i1> undef, i1 %x, i32 0
%2 = insertelement <4 x i1> %1, i1 %x, i32 1
@@ -129,9 +129,9 @@ define <4 x i1> @buildvec_mask_optsize_nonconst_v4i1(i1 %x, i1 %y) optsize {
; CHECK-NEXT: sb a0, 12(sp)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 12
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%1 = insertelement <4 x i1> undef, i1 %x, i32 0
@@ -153,9 +153,9 @@ define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) {
; CHECK-NEXT: sb zero, 12(sp)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 12
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%1 = insertelement <4 x i1> undef, i1 0, i32 0
@@ -182,10 +182,10 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1
@@ -214,9 +214,9 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) {
; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0
@@ -246,9 +246,9 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %
; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0
@@ -277,9 +277,9 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize {
; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0
@@ -459,12 +459,12 @@ define <64 x i1> @buildvec_mask_v64i1() {
; RV32-LMULMAX4-NEXT: lui a0, 748388
; RV32-LMULMAX4-NEXT: addi a0, a0, -1793
; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-LMULMAX4-NEXT: vmv.s.x v25, a0
+; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX4-NEXT: lui a0, 748384
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; RV32-LMULMAX4-NEXT: vslideup.vi v0, v25, 1
+; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX4-NEXT: ret
;
; RV64-LMULMAX4-LABEL: buildvec_mask_v64i1:
@@ -486,12 +486,12 @@ define <64 x i1> @buildvec_mask_v64i1() {
; RV32-LMULMAX8-NEXT: lui a0, 748388
; RV32-LMULMAX8-NEXT: addi a0, a0, -1793
; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0
+; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: lui a0, 748384
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 1
+; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX8-NEXT: ret
;
; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1:
@@ -594,21 +594,21 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV32-LMULMAX4-NEXT: lui a0, 748388
; RV32-LMULMAX4-NEXT: addi a0, a0, -1793
; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-LMULMAX4-NEXT: vmv.s.x v25, a0
+; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX4-NEXT: lui a0, 748384
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; RV32-LMULMAX4-NEXT: vslideup.vi v0, v25, 1
+; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX4-NEXT: lui a0, 945060
; RV32-LMULMAX4-NEXT: addi a0, a0, -1793
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV32-LMULMAX4-NEXT: vmv.s.x v25, a0
+; RV32-LMULMAX4-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX4-NEXT: lui a0, 551776
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; RV32-LMULMAX4-NEXT: vslideup.vi v8, v25, 1
+; RV32-LMULMAX4-NEXT: vslideup.vi v8, v9, 1
; RV32-LMULMAX4-NEXT: ret
;
; RV64-LMULMAX4-LABEL: buildvec_mask_v128i1:
@@ -637,24 +637,24 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV32-LMULMAX8-NEXT: lui a0, 748388
; RV32-LMULMAX8-NEXT: addi a0, a0, -1793
; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0
+; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: lui a0, 748384
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 1
+; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX8-NEXT: lui a0, 551776
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0
+; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 2
+; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 2
; RV32-LMULMAX8-NEXT: lui a0, 945060
; RV32-LMULMAX8-NEXT: addi a0, a0, -1793
; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0
+; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 3
+; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 3
; RV32-LMULMAX8-NEXT: ret
;
; RV64-LMULMAX8-LABEL: buildvec_mask_v128i1:
@@ -666,7 +666,7 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV64-LMULMAX8-NEXT: slli a0, a0, 17
; RV64-LMULMAX8-NEXT: addi a0, a0, 1776
; RV64-LMULMAX8-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-LMULMAX8-NEXT: vmv.s.x v25, a0
+; RV64-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX8-NEXT: lui a0, 1048429
; RV64-LMULMAX8-NEXT: addiw a0, a0, 1735
; RV64-LMULMAX8-NEXT: slli a0, a0, 13
@@ -677,7 +677,7 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV64-LMULMAX8-NEXT: addi a0, a0, 1776
; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX8-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; RV64-LMULMAX8-NEXT: vslideup.vi v0, v25, 1
+; RV64-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV64-LMULMAX8-NEXT: ret
ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
index e60a1da17f843..6b58ecd313b67 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
@@ -9,15 +9,15 @@ define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <1 x i1>, <1 x i1>* %x
store <1 x i1> %a, <1 x i1>* %y
@@ -29,15 +29,15 @@ define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x i1>, <2 x i1>* %x
store <2 x i1> %a, <2 x i1>* %y
@@ -49,15 +49,15 @@ define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x i1>, <4 x i1>* %x
store <4 x i1> %a, <4 x i1>* %y
@@ -68,8 +68,8 @@ define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: load_store_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
store <8 x i1> %a, <8 x i1>* %y
@@ -80,8 +80,8 @@ define void @load_store_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: load_store_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
store <16 x i1> %a, <16 x i1>* %y
@@ -93,8 +93,8 @@ define void @load_store_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vlm.v v25, (a0)
-; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vlm.v v8, (a0)
+; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: load_store_v32i1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
index b4164beebb376..fc19cee141e64 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
@@ -8,10 +8,10 @@ define void @and_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: and_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmand.mm v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmand.mm v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
@@ -24,10 +24,10 @@ define void @or_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: or_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmor.mm v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmor.mm v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
@@ -41,10 +41,10 @@ define void @xor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmxor.mm v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmxor.mm v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
@@ -58,9 +58,9 @@ define void @not_v64i1(<64 x i1>* %x, <64 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vmnand.mm v8, v8, v8
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%b = load <64 x i1>, <64 x i1>* %y
@@ -73,10 +73,10 @@ define void @andnot_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: andnot_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmandnot.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmandnot.mm v8, v9, v8
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
@@ -90,10 +90,10 @@ define void @ornot_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: ornot_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmornot.mm v25, v26, v25
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmornot.mm v8, v9, v8
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
@@ -108,10 +108,10 @@ define void @xornot_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmxnor.mm v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmxnor.mm v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
@@ -125,10 +125,10 @@ define void @nand_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: nand_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmnand.mm v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmnand.mm v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
@@ -142,10 +142,10 @@ define void @nor_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: nor_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmnor.mm v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmnor.mm v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
@@ -160,10 +160,10 @@ define void @xnor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vlm.v v26, (a1)
-; CHECK-NEXT: vmxnor.mm v25, v25, v26
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v9, (a1)
+; CHECK-NEXT: vmxnor.mm v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
index 015f6d31ea473..17300e9eb36cb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
@@ -9,15 +9,15 @@ define void @splat_ones_v1i1(<1 x i1>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmset.m v0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
store <1 x i1> <i1 1>, <1 x i1>* %x
ret void
@@ -28,15 +28,15 @@ define void @splat_zeros_v2i1(<2 x i1>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmclr.m v0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
store <2 x i1> zeroinitializer, <2 x i1>* %x
ret void
@@ -47,17 +47,17 @@ define void @splat_v1i1(<1 x i1>* %x, i1 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <1 x i1> undef, i1 %y, i32 0
%b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer
@@ -71,17 +71,17 @@ define void @splat_v1i1_icmp(<1 x i1>* %x, i32 signext %y, i32 signext %z) {
; CHECK-NEXT: xor a1, a1, a2
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%c = icmp eq i32 %y, %z
%a = insertelement <1 x i1> undef, i1 %c, i32 0
@@ -95,15 +95,15 @@ define void @splat_ones_v4i1(<4 x i1>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmset.m v0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
ret void
@@ -114,17 +114,17 @@ define void @splat_v4i1(<4 x i1>* %x, i1 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i1> undef, i1 %y, i32 0
%b = shufflevector <4 x i1> %a, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -136,8 +136,8 @@ define void @splat_zeros_v8i1(<8 x i1>* %x) {
; CHECK-LABEL: splat_zeros_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmclr.m v25
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmclr.m v8
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
store <8 x i1> zeroinitializer, <8 x i1>* %x
ret void
@@ -148,9 +148,9 @@ define void @splat_v8i1(<8 x i1>* %x, i1 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmsne.vi v8, v8, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i1> undef, i1 %y, i32 0
%b = shufflevector <8 x i1> %a, <8 x i1> undef, <8 x i32> zeroinitializer
@@ -162,8 +162,8 @@ define void @splat_ones_v16i1(<16 x i1>* %x) {
; CHECK-LABEL: splat_ones_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmset.m v25
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmset.m v8
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
store <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i1>* %x
ret void
@@ -174,9 +174,9 @@ define void @splat_v16i1(<16 x i1>* %x, i1 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a1
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmsne.vi v8, v8, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i1> undef, i1 %y, i32 0
%b = shufflevector <16 x i1> %a, <16 x i1> undef, <16 x i32> zeroinitializer
@@ -189,26 +189,26 @@ define void @splat_zeros_v32i1(<32 x i1>* %x) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-NEXT: vmclr.m v25
-; LMULMAX2-NEXT: vsm.v v25, (a0)
+; LMULMAX2-NEXT: vmclr.m v8
+; LMULMAX2-NEXT: vsm.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_zeros_v32i1:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmclr.m v25
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vmclr.m v8
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a0, 2
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_zeros_v32i1:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmclr.m v25
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vmclr.m v8
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a0, 2
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
store <32 x i1> zeroinitializer, <32 x i1>* %x
ret void
@@ -220,31 +220,31 @@ define void @splat_v32i1(<32 x i1>* %x, i1 %y) {
; LMULMAX2-NEXT: andi a1, a1, 1
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.x v26, a1
-; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vsm.v v25, (a0)
+; LMULMAX2-NEXT: vmv.v.x v8, a1
+; LMULMAX2-NEXT: vmsne.vi v10, v8, 0
+; LMULMAX2-NEXT: vsm.v v10, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_v32i1:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: andi a1, a1, 1
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1
-; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0
+; LMULMAX1-RV32-NEXT: vmv.v.x v8, a1
+; LMULMAX1-RV32-NEXT: vmsne.vi v8, v8, 0
; LMULMAX1-RV32-NEXT: addi a1, a0, 2
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_v32i1:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: andi a1, a1, 1
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
-; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0
+; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1
+; LMULMAX1-RV64-NEXT: vmsne.vi v8, v8, 0
; LMULMAX1-RV64-NEXT: addi a1, a0, 2
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <32 x i1> undef, i1 %y, i32 0
%b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> zeroinitializer
@@ -258,35 +258,35 @@ define void @splat_ones_v64i1(<64 x i1>* %x) {
; LMULMAX2-NEXT: addi a1, a0, 4
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vmset.m v25
-; LMULMAX2-NEXT: vsm.v v25, (a1)
-; LMULMAX2-NEXT: vsm.v v25, (a0)
+; LMULMAX2-NEXT: vmset.m v8
+; LMULMAX2-NEXT: vsm.v v8, (a1)
+; LMULMAX2-NEXT: vsm.v v8, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_ones_v64i1:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmset.m v25
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vmset.m v8
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 6
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, a0, 4
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a0, a0, 2
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_ones_v64i1:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmset.m v25
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vmset.m v8
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 6
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, a0, 4
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a0, a0, 2
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
store <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <64 x i1>* %x
ret void
@@ -298,41 +298,41 @@ define void @splat_v64i1(<64 x i1>* %x, i1 %y) {
; LMULMAX2-NEXT: andi a1, a1, 1
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vmv.v.x v26, a1
-; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
+; LMULMAX2-NEXT: vmv.v.x v8, a1
+; LMULMAX2-NEXT: vmsne.vi v10, v8, 0
; LMULMAX2-NEXT: addi a1, a0, 4
-; LMULMAX2-NEXT: vsm.v v25, (a1)
-; LMULMAX2-NEXT: vsm.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v10, (a1)
+; LMULMAX2-NEXT: vsm.v v10, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_v64i1:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: andi a1, a1, 1
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1
-; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0
+; LMULMAX1-RV32-NEXT: vmv.v.x v8, a1
+; LMULMAX1-RV32-NEXT: vmsne.vi v8, v8, 0
; LMULMAX1-RV32-NEXT: addi a1, a0, 6
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, a0, 4
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV32-NEXT: addi a1, a0, 2
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_v64i1:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: andi a1, a1, 1
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
-; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0
+; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1
+; LMULMAX1-RV64-NEXT: vmsne.vi v8, v8, 0
; LMULMAX1-RV64-NEXT: addi a1, a0, 6
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, a0, 4
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a1)
; LMULMAX1-RV64-NEXT: addi a1, a0, 2
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <64 x i1> undef, i1 %y, i32 0
%b = shufflevector <64 x i1> %a, <64 x i1> undef, <64 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index 590af5b9fc755..9fc5b5b368748 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -194,15 +194,15 @@ define <4 x i8> @mgather_truemask_v4i8(<4 x i8*> %ptrs, <4 x i8> %passthru) {
; RV32-LABEL: mgather_truemask_v4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_v4i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -248,18 +248,18 @@ define <8 x i8> @mgather_baseidx_v8i8(i8* %base, <8 x i8> %idxs, <8 x i1> %m, <8
; RV32-LABEL: mgather_baseidx_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
+; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
+; RV64-NEXT: vsext.vf8 v12, v8
; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs
@@ -415,15 +415,15 @@ define <4 x i16> @mgather_truemask_v4i16(<4 x i16*> %ptrs, <4 x i16> %passthru)
; RV32-LABEL: mgather_truemask_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_v4i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -469,20 +469,20 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 x i1
; RV32-LABEL: mgather_baseidx_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs
@@ -494,20 +494,20 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
@@ -520,20 +520,20 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
@@ -546,20 +546,20 @@ define <8 x i16> @mgather_baseidx_v8i16(i16* %base, <8 x i16> %idxs, <8 x i1> %m
; RV32-LABEL: mgather_baseidx_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs
@@ -679,8 +679,8 @@ define <4 x i32> @mgather_truemask_v4i32(<4 x i32*> %ptrs, <4 x i32> %passthru)
; RV64-LABEL: mgather_truemask_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -726,19 +726,19 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8 x i1
; RV32-LABEL: mgather_baseidx_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs
@@ -750,19 +750,19 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
@@ -775,19 +775,19 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
@@ -800,19 +800,19 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(i32* %base, <8 x i16> %idxs, <8 x
; RV32-LABEL: mgather_baseidx_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs
@@ -824,19 +824,19 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(i32* %base, <8 x i16> %idxs,
; RV32-LABEL: mgather_baseidx_sext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
@@ -849,19 +849,19 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(i32* %base, <8 x i16> %idxs,
; RV32-LABEL: mgather_baseidx_zext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
@@ -874,18 +874,18 @@ define <8 x i32> @mgather_baseidx_v8i32(i32* %base, <8 x i32> %idxs, <8 x i1> %m
; RV32-LABEL: mgather_baseidx_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs
@@ -957,8 +957,8 @@ define <4 x i64> @mgather_truemask_v4i64(<4 x i64*> %ptrs, <4 x i64> %passthru)
; RV32-LABEL: mgather_truemask_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_v4i64:
@@ -1010,19 +1010,19 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1
; RV32-LABEL: mgather_baseidx_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs
@@ -1034,18 +1034,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf8 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf8 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
@@ -1058,18 +1058,18 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf8 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf8 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf8 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
@@ -1082,19 +1082,19 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x
; RV32-LABEL: mgather_baseidx_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs
@@ -1106,18 +1106,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs,
; RV32-LABEL: mgather_baseidx_sext_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
@@ -1130,18 +1130,18 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs,
; RV32-LABEL: mgather_baseidx_zext_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf4 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
@@ -1154,18 +1154,18 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x
; RV32-LABEL: mgather_baseidx_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 3
+; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs
@@ -1177,18 +1177,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs,
; RV32-LABEL: mgather_baseidx_sext_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
@@ -1201,18 +1201,18 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs,
; RV32-LABEL: mgather_baseidx_zext_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf2 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
@@ -1225,16 +1225,16 @@ define <8 x i64> @mgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m
; RV32-LABEL: mgather_baseidx_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsll.vi v28, v8, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsll.vi v8, v8, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs
@@ -1306,15 +1306,15 @@ define <4 x half> @mgather_truemask_v4f16(<4 x half*> %ptrs, <4 x half> %passthr
; RV32-LABEL: mgather_truemask_v4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_v4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -1360,20 +1360,20 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(half* %base, <8 x i8> %idxs, <8 x
; RV32-LABEL: mgather_baseidx_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs
@@ -1385,20 +1385,20 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(half* %base, <8 x i8> %idxs,
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
@@ -1411,20 +1411,20 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(half* %base, <8 x i8> %idxs,
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
@@ -1437,20 +1437,20 @@ define <8 x half> @mgather_baseidx_v8f16(half* %base, <8 x i16> %idxs, <8 x i1>
; RV32-LABEL: mgather_baseidx_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs
@@ -1528,8 +1528,8 @@ define <4 x float> @mgather_truemask_v4f32(<4 x float*> %ptrs, <4 x float> %pass
; RV64-LABEL: mgather_truemask_v4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -1575,19 +1575,19 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(float* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mgather_baseidx_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs
@@ -1599,19 +1599,19 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(float* %base, <8 x i8> %idxs
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
@@ -1624,19 +1624,19 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(float* %base, <8 x i8> %idxs
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
@@ -1649,19 +1649,19 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(float* %base, <8 x i16> %idxs, <
; RV32-LABEL: mgather_baseidx_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs
@@ -1673,19 +1673,19 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(float* %base, <8 x i16> %id
; RV32-LABEL: mgather_baseidx_sext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
@@ -1698,19 +1698,19 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(float* %base, <8 x i16> %id
; RV32-LABEL: mgather_baseidx_zext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
@@ -1723,18 +1723,18 @@ define <8 x float> @mgather_baseidx_v8f32(float* %base, <8 x i32> %idxs, <8 x i1
; RV32-LABEL: mgather_baseidx_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 2
-; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs
@@ -1806,8 +1806,8 @@ define <4 x double> @mgather_truemask_v4f64(<4 x double*> %ptrs, <4 x double> %p
; RV32-LABEL: mgather_truemask_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_v4f64:
@@ -1859,19 +1859,19 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(double* %base, <8 x i8> %idxs, <
; RV32-LABEL: mgather_baseidx_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs
@@ -1883,18 +1883,18 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %id
; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf8 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf8 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
@@ -1907,18 +1907,18 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %id
; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf8 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf8 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf8 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
@@ -1931,19 +1931,19 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(double* %base, <8 x i16> %idxs,
; RV32-LABEL: mgather_baseidx_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs
@@ -1955,18 +1955,18 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> %
; RV32-LABEL: mgather_baseidx_sext_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
@@ -1979,18 +1979,18 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> %
; RV32-LABEL: mgather_baseidx_zext_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf4 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
@@ -2003,18 +2003,18 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(double* %base, <8 x i32> %idxs,
; RV32-LABEL: mgather_baseidx_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 3
+; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs
@@ -2026,18 +2026,18 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> %
; RV32-LABEL: mgather_baseidx_sext_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_sext_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
@@ -2050,18 +2050,18 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> %
; RV32-LABEL: mgather_baseidx_zext_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_zext_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf2 v16, v8
+; RV64-NEXT: vsll.vi v8, v16, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
@@ -2074,16 +2074,16 @@ define <8 x double> @mgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x
; RV32-LABEL: mgather_baseidx_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 3
-; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 3
+; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_baseidx_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsll.vi v28, v8, 3
-; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t
+; RV64-NEXT: vsll.vi v8, v8, 3
+; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs
@@ -2097,9 +2097,9 @@ define <16 x i8> @mgather_baseidx_v16i8(i8* %base, <16 x i8> %idxs, <16 x i1> %m
; RV32-LABEL: mgather_baseidx_v16i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
+; RV32-NEXT: vsext.vf4 v12, v8
; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v12, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
@@ -2131,20 +2131,20 @@ define <32 x i8> @mgather_baseidx_v32i8(i8* %base, <32 x i8> %idxs, <32 x i1> %m
;
; RV64-LABEL: mgather_baseidx_v32i8:
; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v25, v0
+; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, mu
-; RV64-NEXT: vslidedown.vi v26, v10, 16
-; RV64-NEXT: vslidedown.vi v28, v8, 16
+; RV64-NEXT: vslidedown.vi v14, v10, 16
+; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vsext.vf8 v16, v28
+; RV64-NEXT: vsext.vf8 v24, v16
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vluxei64.v v26, (a0), v16, v0.t
+; RV64-NEXT: vluxei64.v v14, (a0), v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV64-NEXT: vmv1r.v v0, v25
+; RV64-NEXT: vmv1r.v v0, v12
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: addi a0, zero, 32
; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -2152,7 +2152,7 @@ define <32 x i8> @mgather_baseidx_v32i8(i8* %base, <32 x i8> %idxs, <32 x i1> %m
; RV64-NEXT: vsetivli zero, 16, e8, m2, tu, mu
; RV64-NEXT: vslideup.vi v8, v10, 0
; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, mu
-; RV64-NEXT: vslideup.vi v8, v26, 16
+; RV64-NEXT: vslideup.vi v8, v14, 16
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs
%v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
index b235508bad16f..591f7a2bbc95d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
@@ -6,11 +6,11 @@ define void @masked_load_v1f16(<1 x half>* %a, <1 x half>* %m_ptr, <1 x half>* %
; CHECK-LABEL: masked_load_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <1 x half>, <1 x half>* %m_ptr
%mask = fcmp oeq <1 x half> %m, zeroinitializer
@@ -24,11 +24,11 @@ define void @masked_load_v1f32(<1 x float>* %a, <1 x float>* %m_ptr, <1 x float>
; CHECK-LABEL: masked_load_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vle32.v v25, (a0), v0.t
-; CHECK-NEXT: vse32.v v25, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <1 x float>, <1 x float>* %m_ptr
%mask = fcmp oeq <1 x float> %m, zeroinitializer
@@ -42,21 +42,21 @@ define void @masked_load_v1f64(<1 x double>* %a, <1 x double>* %m_ptr, <1 x doub
; RV32-LABEL: masked_load_v1f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a1)
+; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v25, ft0
-; RV32-NEXT: vle64.v v25, (a0), v0.t
-; RV32-NEXT: vse64.v v25, (a2)
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vle64.v v8, (a0), v0.t
+; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
;
; RV64-LABEL: masked_load_v1f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a1)
+; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v25, ft0
-; RV64-NEXT: vle64.v v25, (a0), v0.t
-; RV64-NEXT: vse64.v v25, (a2)
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vle64.v v8, (a0), v0.t
+; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
%m = load <1 x double>, <1 x double>* %m_ptr
%mask = fcmp oeq <1 x double> %m, zeroinitializer
@@ -70,11 +70,11 @@ define void @masked_load_v2f16(<2 x half>* %a, <2 x half>* %m_ptr, <2 x half>* %
; CHECK-LABEL: masked_load_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <2 x half>, <2 x half>* %m_ptr
%mask = fcmp oeq <2 x half> %m, zeroinitializer
@@ -88,11 +88,11 @@ define void @masked_load_v2f32(<2 x float>* %a, <2 x float>* %m_ptr, <2 x float>
; CHECK-LABEL: masked_load_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vle32.v v25, (a0), v0.t
-; CHECK-NEXT: vse32.v v25, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <2 x float>, <2 x float>* %m_ptr
%mask = fcmp oeq <2 x float> %m, zeroinitializer
@@ -106,21 +106,21 @@ define void @masked_load_v2f64(<2 x double>* %a, <2 x double>* %m_ptr, <2 x doub
; RV32-LABEL: masked_load_v2f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a1)
+; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v25, ft0
-; RV32-NEXT: vle64.v v25, (a0), v0.t
-; RV32-NEXT: vse64.v v25, (a2)
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vle64.v v8, (a0), v0.t
+; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
;
; RV64-LABEL: masked_load_v2f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a1)
+; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v25, ft0
-; RV64-NEXT: vle64.v v25, (a0), v0.t
-; RV64-NEXT: vse64.v v25, (a2)
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vle64.v v8, (a0), v0.t
+; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
%m = load <2 x double>, <2 x double>* %m_ptr
%mask = fcmp oeq <2 x double> %m, zeroinitializer
@@ -134,11 +134,11 @@ define void @masked_load_v4f16(<4 x half>* %a, <4 x half>* %m_ptr, <4 x half>* %
; CHECK-LABEL: masked_load_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <4 x half>, <4 x half>* %m_ptr
%mask = fcmp oeq <4 x half> %m, zeroinitializer
@@ -152,11 +152,11 @@ define void @masked_load_v4f32(<4 x float>* %a, <4 x float>* %m_ptr, <4 x float>
; CHECK-LABEL: masked_load_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vle32.v v25, (a0), v0.t
-; CHECK-NEXT: vse32.v v25, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <4 x float>, <4 x float>* %m_ptr
%mask = fcmp oeq <4 x float> %m, zeroinitializer
@@ -170,21 +170,21 @@ define void @masked_load_v4f64(<4 x double>* %a, <4 x double>* %m_ptr, <4 x doub
; RV32-LABEL: masked_load_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a1)
+; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v26, ft0
-; RV32-NEXT: vle64.v v26, (a0), v0.t
-; RV32-NEXT: vse64.v v26, (a2)
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vle64.v v8, (a0), v0.t
+; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
;
; RV64-LABEL: masked_load_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a1)
+; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v26, ft0
-; RV64-NEXT: vle64.v v26, (a0), v0.t
-; RV64-NEXT: vse64.v v26, (a2)
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vle64.v v8, (a0), v0.t
+; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
%m = load <4 x double>, <4 x double>* %m_ptr
%mask = fcmp oeq <4 x double> %m, zeroinitializer
@@ -198,11 +198,11 @@ define void @masked_load_v8f16(<8 x half>* %a, <8 x half>* %m_ptr, <8 x half>* %
; CHECK-LABEL: masked_load_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
+; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <8 x half>, <8 x half>* %m_ptr
%mask = fcmp oeq <8 x half> %m, zeroinitializer
@@ -216,11 +216,11 @@ define void @masked_load_v8f32(<8 x float>* %a, <8 x float>* %m_ptr, <8 x float>
; CHECK-LABEL: masked_load_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v26, ft0
-; CHECK-NEXT: vle32.v v26, (a0), v0.t
-; CHECK-NEXT: vse32.v v26, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <8 x float>, <8 x float>* %m_ptr
%mask = fcmp oeq <8 x float> %m, zeroinitializer
@@ -234,21 +234,21 @@ define void @masked_load_v8f64(<8 x double>* %a, <8 x double>* %m_ptr, <8 x doub
; RV32-LABEL: masked_load_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a1)
+; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v28, ft0
-; RV32-NEXT: vle64.v v28, (a0), v0.t
-; RV32-NEXT: vse64.v v28, (a2)
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vle64.v v8, (a0), v0.t
+; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: ret
;
; RV64-LABEL: masked_load_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a1)
+; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v28, ft0
-; RV64-NEXT: vle64.v v28, (a0), v0.t
-; RV64-NEXT: vse64.v v28, (a2)
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vle64.v v8, (a0), v0.t
+; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: ret
%m = load <8 x double>, <8 x double>* %m_ptr
%mask = fcmp oeq <8 x double> %m, zeroinitializer
@@ -262,11 +262,11 @@ define void @masked_load_v16f16(<16 x half>* %a, <16 x half>* %m_ptr, <16 x half
; CHECK-LABEL: masked_load_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a1)
+; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v26, ft0
-; CHECK-NEXT: vle16.v v26, (a0), v0.t
-; CHECK-NEXT: vse16.v v26, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <16 x half>, <16 x half>* %m_ptr
%mask = fcmp oeq <16 x half> %m, zeroinitializer
@@ -280,11 +280,11 @@ define void @masked_load_v16f32(<16 x float>* %a, <16 x float>* %m_ptr, <16 x fl
; CHECK-LABEL: masked_load_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a1)
+; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v28, ft0
-; CHECK-NEXT: vle32.v v28, (a0), v0.t
-; CHECK-NEXT: vse32.v v28, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <16 x float>, <16 x float>* %m_ptr
%mask = fcmp oeq <16 x float> %m, zeroinitializer
@@ -327,11 +327,11 @@ define void @masked_load_v32f16(<32 x half>* %a, <32 x half>* %m_ptr, <32 x half
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a1)
+; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v28, ft0
-; CHECK-NEXT: vle16.v v28, (a0), v0.t
-; CHECK-NEXT: vse16.v v28, (a2)
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <32 x half>, <32 x half>* %m_ptr
%mask = fcmp oeq <32 x half> %m, zeroinitializer
@@ -365,36 +365,36 @@ define void @masked_load_v32f64(<32 x double>* %a, <32 x double>* %m_ptr, <32 x
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a1, 128
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: vle64.v v16, (a3)
+; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: vle64.v v24, (a3)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v25, v8, ft0
-; RV32-NEXT: vmfeq.vf v0, v16, ft0
+; RV32-NEXT: vmfeq.vf v8, v16, ft0
+; RV32-NEXT: vmfeq.vf v0, v24, ft0
; RV32-NEXT: addi a1, a0, 128
-; RV32-NEXT: vle64.v v8, (a1), v0.t
-; RV32-NEXT: vmv1r.v v0, v25
-; RV32-NEXT: vle64.v v16, (a0), v0.t
-; RV32-NEXT: vse64.v v16, (a2)
+; RV32-NEXT: vle64.v v16, (a1), v0.t
+; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vle64.v v8, (a0), v0.t
+; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: addi a0, a2, 128
-; RV32-NEXT: vse64.v v8, (a0)
+; RV32-NEXT: vse64.v v16, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: masked_load_v32f64:
; RV64: # %bb.0:
; RV64-NEXT: addi a3, a1, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: vle64.v v16, (a3)
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: vle64.v v24, (a3)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v25, v8, ft0
-; RV64-NEXT: vmfeq.vf v0, v16, ft0
+; RV64-NEXT: vmfeq.vf v8, v16, ft0
+; RV64-NEXT: vmfeq.vf v0, v24, ft0
; RV64-NEXT: addi a1, a0, 128
-; RV64-NEXT: vle64.v v8, (a1), v0.t
-; RV64-NEXT: vmv1r.v v0, v25
-; RV64-NEXT: vle64.v v16, (a0), v0.t
-; RV64-NEXT: vse64.v v16, (a2)
+; RV64-NEXT: vle64.v v16, (a1), v0.t
+; RV64-NEXT: vmv1r.v v0, v8
+; RV64-NEXT: vle64.v v8, (a0), v0.t
+; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: addi a0, a2, 128
-; RV64-NEXT: vse64.v v8, (a0)
+; RV64-NEXT: vse64.v v16, (a0)
; RV64-NEXT: ret
%m = load <32 x double>, <32 x double>* %m_ptr
%mask = fcmp oeq <32 x double> %m, zeroinitializer
@@ -429,18 +429,18 @@ define void @masked_load_v64f32(<64 x float>* %a, <64 x float>* %m_ptr, <64 x fl
; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: addi a4, zero, 32
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, mu
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vle32.v v16, (a3)
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vle32.v v24, (a3)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0
-; CHECK-NEXT: vmfeq.vf v0, v16, ft0
+; CHECK-NEXT: vmfeq.vf v8, v16, ft0
+; CHECK-NEXT: vmfeq.vf v0, v24, ft0
; CHECK-NEXT: addi a1, a0, 128
-; CHECK-NEXT: vle32.v v8, (a1), v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vle32.v v16, (a0), v0.t
-; CHECK-NEXT: vse32.v v16, (a2)
+; CHECK-NEXT: vle32.v v16, (a1), v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: addi a0, a2, 128
-; CHECK-NEXT: vse32.v v8, (a0)
+; CHECK-NEXT: vse32.v v16, (a0)
; CHECK-NEXT: ret
%m = load <64 x float>, <64 x float>* %m_ptr
%mask = fcmp oeq <64 x float> %m, zeroinitializer
@@ -456,18 +456,18 @@ define void @masked_load_v128f16(<128 x half>* %a, <128 x half>* %m_ptr, <128 x
; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: addi a4, zero, 64
; CHECK-NEXT: vsetvli zero, a4, e16, m8, ta, mu
-; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: vle16.v v16, (a3)
+; CHECK-NEXT: vle16.v v16, (a1)
+; CHECK-NEXT: vle16.v v24, (a3)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0
-; CHECK-NEXT: vmfeq.vf v0, v16, ft0
+; CHECK-NEXT: vmfeq.vf v8, v16, ft0
+; CHECK-NEXT: vmfeq.vf v0, v24, ft0
; CHECK-NEXT: addi a1, a0, 128
-; CHECK-NEXT: vle16.v v8, (a1), v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vle16.v v16, (a0), v0.t
-; CHECK-NEXT: vse16.v v16, (a2)
+; CHECK-NEXT: vle16.v v16, (a1), v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: addi a0, a2, 128
-; CHECK-NEXT: vse16.v v8, (a0)
+; CHECK-NEXT: vse16.v v16, (a0)
; CHECK-NEXT: ret
%m = load <128 x half>, <128 x half>* %m_ptr
%mask = fcmp oeq <128 x half> %m, zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
index b87f54ddfa36f..c66e968de5c04 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
@@ -6,10 +6,10 @@ define void @masked_load_v1i8(<1 x i8>* %a, <1 x i8>* %m_ptr, <1 x i8>* %res_ptr
; CHECK-LABEL: masked_load_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle8.v v25, (a0), v0.t
-; CHECK-NEXT: vse8.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: ret
%m = load <1 x i8>, <1 x i8>* %m_ptr
%mask = icmp eq <1 x i8> %m, zeroinitializer
@@ -23,10 +23,10 @@ define void @masked_load_v1i16(<1 x i16>* %a, <1 x i16>* %m_ptr, <1 x i16>* %res
; CHECK-LABEL: masked_load_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <1 x i16>, <1 x i16>* %m_ptr
%mask = icmp eq <1 x i16> %m, zeroinitializer
@@ -40,10 +40,10 @@ define void @masked_load_v1i32(<1 x i32>* %a, <1 x i32>* %m_ptr, <1 x i32>* %res
; CHECK-LABEL: masked_load_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle32.v v25, (a0), v0.t
-; CHECK-NEXT: vse32.v v25, (a2)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <1 x i32>, <1 x i32>* %m_ptr
%mask = icmp eq <1 x i32> %m, zeroinitializer
@@ -57,10 +57,10 @@ define void @masked_load_v1i64(<1 x i64>* %a, <1 x i64>* %m_ptr, <1 x i64>* %res
; CHECK-LABEL: masked_load_v1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle64.v v25, (a0), v0.t
-; CHECK-NEXT: vse64.v v25, (a2)
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle64.v v8, (a0), v0.t
+; CHECK-NEXT: vse64.v v8, (a2)
; CHECK-NEXT: ret
%m = load <1 x i64>, <1 x i64>* %m_ptr
%mask = icmp eq <1 x i64> %m, zeroinitializer
@@ -74,10 +74,10 @@ define void @masked_load_v2i8(<2 x i8>* %a, <2 x i8>* %m_ptr, <2 x i8>* %res_ptr
; CHECK-LABEL: masked_load_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle8.v v25, (a0), v0.t
-; CHECK-NEXT: vse8.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: ret
%m = load <2 x i8>, <2 x i8>* %m_ptr
%mask = icmp eq <2 x i8> %m, zeroinitializer
@@ -91,10 +91,10 @@ define void @masked_load_v2i16(<2 x i16>* %a, <2 x i16>* %m_ptr, <2 x i16>* %res
; CHECK-LABEL: masked_load_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <2 x i16>, <2 x i16>* %m_ptr
%mask = icmp eq <2 x i16> %m, zeroinitializer
@@ -108,10 +108,10 @@ define void @masked_load_v2i32(<2 x i32>* %a, <2 x i32>* %m_ptr, <2 x i32>* %res
; CHECK-LABEL: masked_load_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle32.v v25, (a0), v0.t
-; CHECK-NEXT: vse32.v v25, (a2)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <2 x i32>, <2 x i32>* %m_ptr
%mask = icmp eq <2 x i32> %m, zeroinitializer
@@ -125,10 +125,10 @@ define void @masked_load_v2i64(<2 x i64>* %a, <2 x i64>* %m_ptr, <2 x i64>* %res
; CHECK-LABEL: masked_load_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle64.v v25, (a0), v0.t
-; CHECK-NEXT: vse64.v v25, (a2)
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle64.v v8, (a0), v0.t
+; CHECK-NEXT: vse64.v v8, (a2)
; CHECK-NEXT: ret
%m = load <2 x i64>, <2 x i64>* %m_ptr
%mask = icmp eq <2 x i64> %m, zeroinitializer
@@ -142,10 +142,10 @@ define void @masked_load_v4i8(<4 x i8>* %a, <4 x i8>* %m_ptr, <4 x i8>* %res_ptr
; CHECK-LABEL: masked_load_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle8.v v25, (a0), v0.t
-; CHECK-NEXT: vse8.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: ret
%m = load <4 x i8>, <4 x i8>* %m_ptr
%mask = icmp eq <4 x i8> %m, zeroinitializer
@@ -159,10 +159,10 @@ define void @masked_load_v4i16(<4 x i16>* %a, <4 x i16>* %m_ptr, <4 x i16>* %res
; CHECK-LABEL: masked_load_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <4 x i16>, <4 x i16>* %m_ptr
%mask = icmp eq <4 x i16> %m, zeroinitializer
@@ -176,10 +176,10 @@ define void @masked_load_v4i32(<4 x i32>* %a, <4 x i32>* %m_ptr, <4 x i32>* %res
; CHECK-LABEL: masked_load_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle32.v v25, (a0), v0.t
-; CHECK-NEXT: vse32.v v25, (a2)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <4 x i32>, <4 x i32>* %m_ptr
%mask = icmp eq <4 x i32> %m, zeroinitializer
@@ -193,10 +193,10 @@ define void @masked_load_v4i64(<4 x i64>* %a, <4 x i64>* %m_ptr, <4 x i64>* %res
; CHECK-LABEL: masked_load_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a1)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vle64.v v26, (a0), v0.t
-; CHECK-NEXT: vse64.v v26, (a2)
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle64.v v8, (a0), v0.t
+; CHECK-NEXT: vse64.v v8, (a2)
; CHECK-NEXT: ret
%m = load <4 x i64>, <4 x i64>* %m_ptr
%mask = icmp eq <4 x i64> %m, zeroinitializer
@@ -210,10 +210,10 @@ define void @masked_load_v8i8(<8 x i8>* %a, <8 x i8>* %m_ptr, <8 x i8>* %res_ptr
; CHECK-LABEL: masked_load_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle8.v v25, (a0), v0.t
-; CHECK-NEXT: vse8.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: ret
%m = load <8 x i8>, <8 x i8>* %m_ptr
%mask = icmp eq <8 x i8> %m, zeroinitializer
@@ -227,10 +227,10 @@ define void @masked_load_v8i16(<8 x i16>* %a, <8 x i16>* %m_ptr, <8 x i16>* %res
; CHECK-LABEL: masked_load_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle16.v v25, (a0), v0.t
-; CHECK-NEXT: vse16.v v25, (a2)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <8 x i16>, <8 x i16>* %m_ptr
%mask = icmp eq <8 x i16> %m, zeroinitializer
@@ -244,10 +244,10 @@ define void @masked_load_v8i32(<8 x i32>* %a, <8 x i32>* %m_ptr, <8 x i32>* %res
; CHECK-LABEL: masked_load_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vle32.v v26, (a0), v0.t
-; CHECK-NEXT: vse32.v v26, (a2)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <8 x i32>, <8 x i32>* %m_ptr
%mask = icmp eq <8 x i32> %m, zeroinitializer
@@ -261,10 +261,10 @@ define void @masked_load_v8i64(<8 x i64>* %a, <8 x i64>* %m_ptr, <8 x i64>* %res
; CHECK-LABEL: masked_load_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a1)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vle64.v v28, (a0), v0.t
-; CHECK-NEXT: vse64.v v28, (a2)
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle64.v v8, (a0), v0.t
+; CHECK-NEXT: vse64.v v8, (a2)
; CHECK-NEXT: ret
%m = load <8 x i64>, <8 x i64>* %m_ptr
%mask = icmp eq <8 x i64> %m, zeroinitializer
@@ -278,10 +278,10 @@ define void @masked_load_v16i8(<16 x i8>* %a, <16 x i8>* %m_ptr, <16 x i8>* %res
; CHECK-LABEL: masked_load_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vle8.v v25, (a0), v0.t
-; CHECK-NEXT: vse8.v v25, (a2)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: ret
%m = load <16 x i8>, <16 x i8>* %m_ptr
%mask = icmp eq <16 x i8> %m, zeroinitializer
@@ -295,10 +295,10 @@ define void @masked_load_v16i16(<16 x i16>* %a, <16 x i16>* %m_ptr, <16 x i16>*
; CHECK-LABEL: masked_load_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vle16.v v26, (a0), v0.t
-; CHECK-NEXT: vse16.v v26, (a2)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <16 x i16>, <16 x i16>* %m_ptr
%mask = icmp eq <16 x i16> %m, zeroinitializer
@@ -312,10 +312,10 @@ define void @masked_load_v16i32(<16 x i32>* %a, <16 x i32>* %m_ptr, <16 x i32>*
; CHECK-LABEL: masked_load_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vle32.v v28, (a0), v0.t
-; CHECK-NEXT: vse32.v v28, (a2)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%m = load <16 x i32>, <16 x i32>* %m_ptr
%mask = icmp eq <16 x i32> %m, zeroinitializer
@@ -347,10 +347,10 @@ define void @masked_load_v32i8(<32 x i8>* %a, <32 x i8>* %m_ptr, <32 x i8>* %res
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vle8.v v26, (a0), v0.t
-; CHECK-NEXT: vse8.v v26, (a2)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: ret
%m = load <32 x i8>, <32 x i8>* %m_ptr
%mask = icmp eq <32 x i8> %m, zeroinitializer
@@ -365,10 +365,10 @@ define void @masked_load_v32i16(<32 x i16>* %a, <32 x i16>* %m_ptr, <32 x i16>*
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vle16.v v28, (a0), v0.t
-; CHECK-NEXT: vse16.v v28, (a2)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%m = load <32 x i16>, <32 x i16>* %m_ptr
%mask = icmp eq <32 x i16> %m, zeroinitializer
@@ -399,52 +399,40 @@ declare <32 x i32> @llvm.masked.load.v32i32(<32 x i32>*, i32, <32 x i1>, <32 x i
define void @masked_load_v32i64(<32 x i64>* %a, <32 x i64>* %m_ptr, <32 x i64>* %res_ptr) nounwind {
; RV32-LABEL: masked_load_v32i64:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: sub sp, sp, a3
; RV32-NEXT: addi a3, a1, 128
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vle64.v v8, (a3)
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
-; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: vle64.v v16, (a3)
+; RV32-NEXT: vle64.v v0, (a1)
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vmseq.vv v25, v16, v8
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8re8.v v16, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vmseq.vv v0, v16, v8
+; RV32-NEXT: vmseq.vv v8, v0, v24
+; RV32-NEXT: vmseq.vv v0, v16, v24
; RV32-NEXT: addi a1, a0, 128
-; RV32-NEXT: vle64.v v8, (a1), v0.t
-; RV32-NEXT: vmv1r.v v0, v25
-; RV32-NEXT: vle64.v v16, (a0), v0.t
-; RV32-NEXT: vse64.v v16, (a2)
+; RV32-NEXT: vle64.v v16, (a1), v0.t
+; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vle64.v v8, (a0), v0.t
+; RV32-NEXT: vse64.v v8, (a2)
; RV32-NEXT: addi a0, a2, 128
-; RV32-NEXT: vse64.v v8, (a0)
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add sp, sp, a0
-; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: vse64.v v16, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: masked_load_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: addi a3, a1, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: vle64.v v16, (a3)
-; RV64-NEXT: vmseq.vi v25, v8, 0
-; RV64-NEXT: vmseq.vi v0, v16, 0
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: vle64.v v24, (a3)
+; RV64-NEXT: vmseq.vi v8, v16, 0
+; RV64-NEXT: vmseq.vi v0, v24, 0
; RV64-NEXT: addi a1, a0, 128
-; RV64-NEXT: vle64.v v8, (a1), v0.t
-; RV64-NEXT: vmv1r.v v0, v25
-; RV64-NEXT: vle64.v v16, (a0), v0.t
-; RV64-NEXT: vse64.v v16, (a2)
+; RV64-NEXT: vle64.v v16, (a1), v0.t
+; RV64-NEXT: vmv1r.v v0, v8
+; RV64-NEXT: vle64.v v8, (a0), v0.t
+; RV64-NEXT: vse64.v v8, (a2)
; RV64-NEXT: addi a0, a2, 128
-; RV64-NEXT: vse64.v v8, (a0)
+; RV64-NEXT: vse64.v v16, (a0)
; RV64-NEXT: ret
%m = load <32 x i64>, <32 x i64>* %m_ptr
%mask = icmp eq <32 x i64> %m, zeroinitializer
@@ -459,10 +447,10 @@ define void @masked_load_v64i8(<64 x i8>* %a, <64 x i8>* %m_ptr, <64 x i8>* %res
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a1)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vle8.v v28, (a0), v0.t
-; CHECK-NEXT: vse8.v v28, (a2)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: ret
%m = load <64 x i8>, <64 x i8>* %m_ptr
%mask = icmp eq <64 x i8> %m, zeroinitializer
@@ -496,17 +484,17 @@ define void @masked_load_v64i32(<64 x i32>* %a, <64 x i32>* %m_ptr, <64 x i32>*
; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: addi a4, zero, 32
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, mu
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vle32.v v16, (a3)
-; CHECK-NEXT: vmseq.vi v25, v8, 0
-; CHECK-NEXT: vmseq.vi v0, v16, 0
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vle32.v v24, (a3)
+; CHECK-NEXT: vmseq.vi v8, v16, 0
+; CHECK-NEXT: vmseq.vi v0, v24, 0
; CHECK-NEXT: addi a1, a0, 128
-; CHECK-NEXT: vle32.v v8, (a1), v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vle32.v v16, (a0), v0.t
-; CHECK-NEXT: vse32.v v16, (a2)
+; CHECK-NEXT: vle32.v v16, (a1), v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: addi a0, a2, 128
-; CHECK-NEXT: vse32.v v8, (a0)
+; CHECK-NEXT: vse32.v v16, (a0)
; CHECK-NEXT: ret
%m = load <64 x i32>, <64 x i32>* %m_ptr
%mask = icmp eq <64 x i32> %m, zeroinitializer
@@ -540,17 +528,17 @@ define void @masked_load_v256i8(<256 x i8>* %a, <256 x i8>* %m_ptr, <256 x i8>*
; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: addi a4, zero, 128
; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, mu
-; CHECK-NEXT: vle8.v v8, (a1)
-; CHECK-NEXT: vle8.v v16, (a3)
-; CHECK-NEXT: vmseq.vi v25, v8, 0
-; CHECK-NEXT: vmseq.vi v0, v16, 0
+; CHECK-NEXT: vle8.v v16, (a1)
+; CHECK-NEXT: vle8.v v24, (a3)
+; CHECK-NEXT: vmseq.vi v8, v16, 0
+; CHECK-NEXT: vmseq.vi v0, v24, 0
; CHECK-NEXT: addi a1, a0, 128
-; CHECK-NEXT: vle8.v v8, (a1), v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vle8.v v16, (a0), v0.t
-; CHECK-NEXT: vse8.v v16, (a2)
+; CHECK-NEXT: vle8.v v16, (a1), v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: vse8.v v8, (a2)
; CHECK-NEXT: addi a0, a2, 128
-; CHECK-NEXT: vse8.v v8, (a0)
+; CHECK-NEXT: vse8.v v16, (a0)
; CHECK-NEXT: ret
%m = load <256 x i8>, <256 x i8>* %m_ptr
%mask = icmp eq <256 x i8> %m, zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
index 5f4e7b8c10164..e738b95d03fff 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
@@ -44,15 +44,15 @@ define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2
; RV32-LABEL: mscatter_v2i16_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i16_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i16> %val to <2 x i8>
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
@@ -63,19 +63,19 @@ define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2
; RV32-LABEL: mscatter_v2i32_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i32_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i8>
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
@@ -86,23 +86,23 @@ define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2
; RV32-LABEL: mscatter_v2i64_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i64_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i8>
call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m)
@@ -179,17 +179,17 @@ define void @mscatter_baseidx_v8i8(<8 x i8> %val, i8* %base, <8 x i8> %idxs, <8
; RV32-LABEL: mscatter_baseidx_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
+; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
+; RV64-NEXT: vsext.vf8 v12, v9
; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs
call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> %val, <8 x i8*> %ptrs, i32 1, <8 x i1> %m)
@@ -236,15 +236,15 @@ define void @mscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, <
; RV32-LABEL: mscatter_v2i32_truncstore_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i32_truncstore_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i16>
call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
@@ -255,19 +255,19 @@ define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, <
; RV32-LABEL: mscatter_v2i64_truncstore_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i64_truncstore_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i16>
call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m)
@@ -344,19 +344,19 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i8> %i
; RV32-LABEL: mscatter_baseidx_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs
call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m)
@@ -367,19 +367,19 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
@@ -391,19 +391,19 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
@@ -415,19 +415,19 @@ define void @mscatter_baseidx_v8i16(<8 x i16> %val, i16* %base, <8 x i16> %idxs,
; RV32-LABEL: mscatter_baseidx_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs
call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m)
@@ -474,15 +474,15 @@ define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, <
; RV32-LABEL: mscatter_v2i64_truncstore_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i64_truncstore_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i32>
call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, i32 4, <2 x i1> %m)
@@ -559,18 +559,18 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i8> %i
; RV32-LABEL: mscatter_baseidx_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs
call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m)
@@ -581,18 +581,18 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -604,18 +604,18 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -627,18 +627,18 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x i16>
; RV32-LABEL: mscatter_baseidx_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs
call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m)
@@ -649,18 +649,18 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x
; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -672,18 +672,18 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x
; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -695,17 +695,17 @@ define void @mscatter_baseidx_v8i32(<8 x i32> %val, i32* %base, <8 x i32> %idxs,
; RV32-LABEL: mscatter_baseidx_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v10, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsll.vi v10, v10, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs
call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m)
@@ -818,18 +818,18 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %i
; RV32-LABEL: mscatter_baseidx_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
@@ -840,17 +840,17 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf8 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf8 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -862,17 +862,17 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf8 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf8 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -884,18 +884,18 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16>
; RV32-LABEL: mscatter_baseidx_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
@@ -906,17 +906,17 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x
; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -928,17 +928,17 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x
; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -950,17 +950,17 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32>
; RV32-LABEL: mscatter_baseidx_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v12, 3
+; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
@@ -971,17 +971,17 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x
; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -993,17 +993,17 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x
; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -1015,15 +1015,15 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs,
; RV32-LABEL: mscatter_baseidx_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v12, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v12, v12, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsll.vi v28, v12, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsll.vi v12, v12, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs
call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m)
@@ -1136,19 +1136,19 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, half* %base, <8 x i8>
; RV32-LABEL: mscatter_baseidx_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs
call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m)
@@ -1159,19 +1159,19 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, half* %base, <8 x
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
@@ -1183,19 +1183,19 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, half* %base, <8 x
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
@@ -1207,19 +1207,19 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, half* %base, <8 x i16> %idx
; RV32-LABEL: mscatter_baseidx_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs
call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m)
@@ -1332,18 +1332,18 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, float* %base, <8 x i8
; RV32-LABEL: mscatter_baseidx_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs
call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m)
@@ -1354,18 +1354,18 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, float* %base, <8
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1377,18 +1377,18 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, float* %base, <8
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1400,18 +1400,18 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, float* %base, <8 x i
; RV32-LABEL: mscatter_baseidx_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs
call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m)
@@ -1422,18 +1422,18 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, float* %base, <
; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1445,18 +1445,18 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, float* %base, <
; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vzext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1468,17 +1468,17 @@ define void @mscatter_baseidx_v8f32(<8 x float> %val, float* %base, <8 x i32> %i
; RV32-LABEL: mscatter_baseidx_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v10, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsll.vi v10, v10, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs
call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m)
@@ -1591,18 +1591,18 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, double* %base, <8 x
; RV32-LABEL: mscatter_baseidx_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
@@ -1613,17 +1613,17 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base,
; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf8 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf8 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1635,17 +1635,17 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base,
; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf8 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf8 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1657,18 +1657,18 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, double* %base, <8 x
; RV32-LABEL: mscatter_baseidx_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
@@ -1679,17 +1679,17 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base,
; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1701,17 +1701,17 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base,
; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1723,17 +1723,17 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, double* %base, <8 x
; RV32-LABEL: mscatter_baseidx_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v12, 3
+; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
@@ -1744,17 +1744,17 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base,
; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1766,17 +1766,17 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base,
; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vzext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1788,15 +1788,15 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64>
; RV32-LABEL: mscatter_baseidx_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v12, 3
-; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v12, v12, 3
+; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsll.vi v28, v12, 3
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsll.vi v12, v12, 3
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs
call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m)
@@ -1809,9 +1809,9 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, i8* %base, <16 x i8> %idxs,
; RV32-LABEL: mscatter_baseidx_v16i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v9
+; RV32-NEXT: vsext.vf4 v12, v9
; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_v16i8:
@@ -1845,14 +1845,14 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, i8* %base, <32 x i8> %idxs,
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, mu
-; RV64-NEXT: vslidedown.vi v26, v8, 16
-; RV64-NEXT: vslidedown.vi v28, v10, 16
+; RV64-NEXT: vslidedown.vi v8, v8, 16
+; RV64-NEXT: vslidedown.vi v10, v10, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vsext.vf8 v8, v28
+; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v26, (a0), v8, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs
call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> %val, <32 x i8*> %ptrs, i32 1, <32 x i1> %m)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
index 0885acb3e4d88..f9c105e6eddc0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
@@ -6,11 +6,11 @@ define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>
; CHECK-LABEL: masked_store_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x half>, <1 x half>* %m_ptr
%mask = fcmp oeq <1 x half> %m, zeroinitializer
@@ -24,11 +24,11 @@ define void @masked_store_v1f32(<1 x float>* %val_ptr, <1 x float>* %a, <1 x flo
; CHECK-LABEL: masked_store_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a2)
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vse32.v v26, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x float>, <1 x float>* %m_ptr
%mask = fcmp oeq <1 x float> %m, zeroinitializer
@@ -42,21 +42,21 @@ define void @masked_store_v1f64(<1 x double>* %val_ptr, <1 x double>* %a, <1 x d
; RV32-LABEL: masked_store_v1f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a2)
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a2)
+; RV32-NEXT: vle64.v v9, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v25, ft0
-; RV32-NEXT: vse64.v v26, (a1), v0.t
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vse64.v v9, (a1), v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: masked_store_v1f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a2)
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a2)
+; RV64-NEXT: vle64.v v9, (a0)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v25, ft0
-; RV64-NEXT: vse64.v v26, (a1), v0.t
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vse64.v v9, (a1), v0.t
; RV64-NEXT: ret
%m = load <1 x double>, <1 x double>* %m_ptr
%mask = fcmp oeq <1 x double> %m, zeroinitializer
@@ -70,11 +70,11 @@ define void @masked_store_v2f16(<2 x half>* %val_ptr, <2 x half>* %a, <2 x half>
; CHECK-LABEL: masked_store_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x half>, <2 x half>* %m_ptr
%mask = fcmp oeq <2 x half> %m, zeroinitializer
@@ -88,11 +88,11 @@ define void @masked_store_v2f32(<2 x float>* %val_ptr, <2 x float>* %a, <2 x flo
; CHECK-LABEL: masked_store_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a2)
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vse32.v v26, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x float>, <2 x float>* %m_ptr
%mask = fcmp oeq <2 x float> %m, zeroinitializer
@@ -106,21 +106,21 @@ define void @masked_store_v2f64(<2 x double>* %val_ptr, <2 x double>* %a, <2 x d
; RV32-LABEL: masked_store_v2f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a2)
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a2)
+; RV32-NEXT: vle64.v v9, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v25, ft0
-; RV32-NEXT: vse64.v v26, (a1), v0.t
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vse64.v v9, (a1), v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: masked_store_v2f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a2)
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a2)
+; RV64-NEXT: vle64.v v9, (a0)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v25, ft0
-; RV64-NEXT: vse64.v v26, (a1), v0.t
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vse64.v v9, (a1), v0.t
; RV64-NEXT: ret
%m = load <2 x double>, <2 x double>* %m_ptr
%mask = fcmp oeq <2 x double> %m, zeroinitializer
@@ -134,11 +134,11 @@ define void @masked_store_v4f16(<4 x half>* %val_ptr, <4 x half>* %a, <4 x half>
; CHECK-LABEL: masked_store_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x half>, <4 x half>* %m_ptr
%mask = fcmp oeq <4 x half> %m, zeroinitializer
@@ -152,11 +152,11 @@ define void @masked_store_v4f32(<4 x float>* %val_ptr, <4 x float>* %a, <4 x flo
; CHECK-LABEL: masked_store_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a2)
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vse32.v v26, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x float>, <4 x float>* %m_ptr
%mask = fcmp oeq <4 x float> %m, zeroinitializer
@@ -170,21 +170,21 @@ define void @masked_store_v4f64(<4 x double>* %val_ptr, <4 x double>* %a, <4 x d
; RV32-LABEL: masked_store_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a2)
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a2)
+; RV32-NEXT: vle64.v v10, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v26, ft0
-; RV32-NEXT: vse64.v v28, (a1), v0.t
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vse64.v v10, (a1), v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: masked_store_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a2)
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a2)
+; RV64-NEXT: vle64.v v10, (a0)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v26, ft0
-; RV64-NEXT: vse64.v v28, (a1), v0.t
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vse64.v v10, (a1), v0.t
; RV64-NEXT: ret
%m = load <4 x double>, <4 x double>* %m_ptr
%mask = fcmp oeq <4 x double> %m, zeroinitializer
@@ -198,11 +198,11 @@ define void @masked_store_v8f16(<8 x half>* %val_ptr, <8 x half>* %a, <8 x half>
; CHECK-LABEL: masked_store_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v25, ft0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x half>, <8 x half>* %m_ptr
%mask = fcmp oeq <8 x half> %m, zeroinitializer
@@ -216,11 +216,11 @@ define void @masked_store_v8f32(<8 x float>* %val_ptr, <8 x float>* %a, <8 x flo
; CHECK-LABEL: masked_store_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a2)
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v26, ft0
-; CHECK-NEXT: vse32.v v28, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse32.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x float>, <8 x float>* %m_ptr
%mask = fcmp oeq <8 x float> %m, zeroinitializer
@@ -234,21 +234,21 @@ define void @masked_store_v8f64(<8 x double>* %val_ptr, <8 x double>* %a, <8 x d
; RV32-LABEL: masked_store_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a2)
-; RV32-NEXT: vle64.v v8, (a0)
+; RV32-NEXT: vle64.v v8, (a2)
+; RV32-NEXT: vle64.v v12, (a0)
; RV32-NEXT: fcvt.d.w ft0, zero
-; RV32-NEXT: vmfeq.vf v0, v28, ft0
-; RV32-NEXT: vse64.v v8, (a1), v0.t
+; RV32-NEXT: vmfeq.vf v0, v8, ft0
+; RV32-NEXT: vse64.v v12, (a1), v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: masked_store_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a2)
-; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vle64.v v8, (a2)
+; RV64-NEXT: vle64.v v12, (a0)
; RV64-NEXT: fmv.d.x ft0, zero
-; RV64-NEXT: vmfeq.vf v0, v28, ft0
-; RV64-NEXT: vse64.v v8, (a1), v0.t
+; RV64-NEXT: vmfeq.vf v0, v8, ft0
+; RV64-NEXT: vse64.v v12, (a1), v0.t
; RV64-NEXT: ret
%m = load <8 x double>, <8 x double>* %m_ptr
%mask = fcmp oeq <8 x double> %m, zeroinitializer
@@ -262,11 +262,11 @@ define void @masked_store_v16f16(<16 x half>* %val_ptr, <16 x half>* %a, <16 x h
; CHECK-LABEL: masked_store_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a2)
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v26, ft0
-; CHECK-NEXT: vse16.v v28, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse16.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <16 x half>, <16 x half>* %m_ptr
%mask = fcmp oeq <16 x half> %m, zeroinitializer
@@ -280,11 +280,11 @@ define void @masked_store_v16f32(<16 x float>* %val_ptr, <16 x float>* %a, <16 x
; CHECK-LABEL: masked_store_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a2)
-; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v28, ft0
-; CHECK-NEXT: vse32.v v8, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse32.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <16 x float>, <16 x float>* %m_ptr
%mask = fcmp oeq <16 x float> %m, zeroinitializer
@@ -327,11 +327,11 @@ define void @masked_store_v32f16(<32 x half>* %val_ptr, <32 x half>* %a, <32 x h
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a2)
-; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
-; CHECK-NEXT: vmfeq.vf v0, v28, ft0
-; CHECK-NEXT: vse16.v v8, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v0, v8, ft0
+; CHECK-NEXT: vse16.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <32 x half>, <32 x half>* %m_ptr
%mask = fcmp oeq <32 x half> %m, zeroinitializer
@@ -378,20 +378,20 @@ define void @masked_store_v32f64(<32 x double>* %val_ptr, <32 x double>* %a, <32
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: fcvt.d.w ft0, zero
; RV32-NEXT: vmfeq.vf v0, v8, ft0
-; RV32-NEXT: vle64.v v8, (a0)
+; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: addi a0, a0, 128
-; RV32-NEXT: vle64.v v16, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; RV32-NEXT: vmfeq.vf v25, v16, ft0
-; RV32-NEXT: vse64.v v8, (a1), v0.t
+; RV32-NEXT: vmfeq.vf v8, v16, ft0
+; RV32-NEXT: vse64.v v24, (a1), v0.t
; RV32-NEXT: addi a0, a1, 128
-; RV32-NEXT: vmv1r.v v0, v25
+; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vse64.v v8, (a0), v0.t
@@ -418,20 +418,20 @@ define void @masked_store_v32f64(<32 x double>* %val_ptr, <32 x double>* %a, <32
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: fmv.d.x ft0, zero
; RV64-NEXT: vmfeq.vf v0, v8, ft0
-; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: addi a0, a0, 128
-; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; RV64-NEXT: vmfeq.vf v25, v16, ft0
-; RV64-NEXT: vse64.v v8, (a1), v0.t
+; RV64-NEXT: vmfeq.vf v8, v16, ft0
+; RV64-NEXT: vse64.v v24, (a1), v0.t
; RV64-NEXT: addi a0, a1, 128
-; RV64-NEXT: vmv1r.v v0, v25
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a0), v0.t
@@ -486,20 +486,20 @@ define void @masked_store_v64f32(<64 x float>* %val_ptr, <64 x float>* %a, <64 x
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: fmv.w.x ft0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0
-; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmfeq.vf v25, v16, ft0
-; CHECK-NEXT: vse32.v v8, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v8, v16, ft0
+; CHECK-NEXT: vse32.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse32.v v8, (a0), v0.t
@@ -535,20 +535,20 @@ define void @masked_store_v128f16(<128 x half>* %val_ptr, <128 x half>* %a, <128
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: vmfeq.vf v0, v8, ft0
-; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmfeq.vf v25, v16, ft0
-; CHECK-NEXT: vse16.v v8, (a1), v0.t
+; CHECK-NEXT: vmfeq.vf v8, v16, ft0
+; CHECK-NEXT: vse16.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse16.v v8, (a0), v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
index dc04ba99372f3..036510dc0f528 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
@@ -6,10 +6,10 @@ define void @masked_store_v1i8(<1 x i8>* %val_ptr, <1 x i8>* %a, <1 x i8>* %m_pt
; CHECK-LABEL: masked_store_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a2)
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse8.v v26, (a1), v0.t
+; CHECK-NEXT: vle8.v v8, (a2)
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse8.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x i8>, <1 x i8>* %m_ptr
%mask = icmp eq <1 x i8> %m, zeroinitializer
@@ -23,10 +23,10 @@ define void @masked_store_v1i16(<1 x i16>* %val_ptr, <1 x i16>* %a, <1 x i16>* %
; CHECK-LABEL: masked_store_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x i16>, <1 x i16>* %m_ptr
%mask = icmp eq <1 x i16> %m, zeroinitializer
@@ -40,10 +40,10 @@ define void @masked_store_v1i32(<1 x i32>* %val_ptr, <1 x i32>* %a, <1 x i32>* %
; CHECK-LABEL: masked_store_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a2)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse32.v v26, (a1), v0.t
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x i32>, <1 x i32>* %m_ptr
%mask = icmp eq <1 x i32> %m, zeroinitializer
@@ -57,10 +57,10 @@ define void @masked_store_v1i64(<1 x i64>* %val_ptr, <1 x i64>* %a, <1 x i64>* %
; CHECK-LABEL: masked_store_v1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a2)
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse64.v v26, (a1), v0.t
+; CHECK-NEXT: vle64.v v8, (a2)
+; CHECK-NEXT: vle64.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse64.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <1 x i64>, <1 x i64>* %m_ptr
%mask = icmp eq <1 x i64> %m, zeroinitializer
@@ -74,10 +74,10 @@ define void @masked_store_v2i8(<2 x i8>* %val_ptr, <2 x i8>* %a, <2 x i8>* %m_pt
; CHECK-LABEL: masked_store_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a2)
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse8.v v26, (a1), v0.t
+; CHECK-NEXT: vle8.v v8, (a2)
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse8.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x i8>, <2 x i8>* %m_ptr
%mask = icmp eq <2 x i8> %m, zeroinitializer
@@ -91,10 +91,10 @@ define void @masked_store_v2i16(<2 x i16>* %val_ptr, <2 x i16>* %a, <2 x i16>* %
; CHECK-LABEL: masked_store_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x i16>, <2 x i16>* %m_ptr
%mask = icmp eq <2 x i16> %m, zeroinitializer
@@ -108,10 +108,10 @@ define void @masked_store_v2i32(<2 x i32>* %val_ptr, <2 x i32>* %a, <2 x i32>* %
; CHECK-LABEL: masked_store_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a2)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse32.v v26, (a1), v0.t
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x i32>, <2 x i32>* %m_ptr
%mask = icmp eq <2 x i32> %m, zeroinitializer
@@ -125,10 +125,10 @@ define void @masked_store_v2i64(<2 x i64>* %val_ptr, <2 x i64>* %a, <2 x i64>* %
; CHECK-LABEL: masked_store_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a2)
-; CHECK-NEXT: vle64.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse64.v v26, (a1), v0.t
+; CHECK-NEXT: vle64.v v8, (a2)
+; CHECK-NEXT: vle64.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse64.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <2 x i64>, <2 x i64>* %m_ptr
%mask = icmp eq <2 x i64> %m, zeroinitializer
@@ -142,10 +142,10 @@ define void @masked_store_v4i8(<4 x i8>* %val_ptr, <4 x i8>* %a, <4 x i8>* %m_pt
; CHECK-LABEL: masked_store_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a2)
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse8.v v26, (a1), v0.t
+; CHECK-NEXT: vle8.v v8, (a2)
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse8.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x i8>, <4 x i8>* %m_ptr
%mask = icmp eq <4 x i8> %m, zeroinitializer
@@ -159,10 +159,10 @@ define void @masked_store_v4i16(<4 x i16>* %val_ptr, <4 x i16>* %a, <4 x i16>* %
; CHECK-LABEL: masked_store_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x i16>, <4 x i16>* %m_ptr
%mask = icmp eq <4 x i16> %m, zeroinitializer
@@ -176,10 +176,10 @@ define void @masked_store_v4i32(<4 x i32>* %val_ptr, <4 x i32>* %a, <4 x i32>* %
; CHECK-LABEL: masked_store_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a2)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse32.v v26, (a1), v0.t
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse32.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x i32>, <4 x i32>* %m_ptr
%mask = icmp eq <4 x i32> %m, zeroinitializer
@@ -193,10 +193,10 @@ define void @masked_store_v4i64(<4 x i64>* %val_ptr, <4 x i64>* %a, <4 x i64>* %
; CHECK-LABEL: masked_store_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a2)
-; CHECK-NEXT: vle64.v v28, (a0)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vse64.v v28, (a1), v0.t
+; CHECK-NEXT: vle64.v v8, (a2)
+; CHECK-NEXT: vle64.v v10, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse64.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <4 x i64>, <4 x i64>* %m_ptr
%mask = icmp eq <4 x i64> %m, zeroinitializer
@@ -210,10 +210,10 @@ define void @masked_store_v8i8(<8 x i8>* %val_ptr, <8 x i8>* %a, <8 x i8>* %m_pt
; CHECK-LABEL: masked_store_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a2)
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse8.v v26, (a1), v0.t
+; CHECK-NEXT: vle8.v v8, (a2)
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse8.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x i8>, <8 x i8>* %m_ptr
%mask = icmp eq <8 x i8> %m, zeroinitializer
@@ -227,10 +227,10 @@ define void @masked_store_v8i16(<8 x i16>* %val_ptr, <8 x i16>* %a, <8 x i16>* %
; CHECK-LABEL: masked_store_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a2)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse16.v v26, (a1), v0.t
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse16.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x i16>, <8 x i16>* %m_ptr
%mask = icmp eq <8 x i16> %m, zeroinitializer
@@ -244,10 +244,10 @@ define void @masked_store_v8i32(<8 x i32>* %val_ptr, <8 x i32>* %a, <8 x i32>* %
; CHECK-LABEL: masked_store_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a2)
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vse32.v v28, (a1), v0.t
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse32.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x i32>, <8 x i32>* %m_ptr
%mask = icmp eq <8 x i32> %m, zeroinitializer
@@ -261,10 +261,10 @@ define void @masked_store_v8i64(<8 x i64>* %val_ptr, <8 x i64>* %a, <8 x i64>* %
; CHECK-LABEL: masked_store_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a2)
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vse64.v v8, (a1), v0.t
+; CHECK-NEXT: vle64.v v8, (a2)
+; CHECK-NEXT: vle64.v v12, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse64.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <8 x i64>, <8 x i64>* %m_ptr
%mask = icmp eq <8 x i64> %m, zeroinitializer
@@ -278,10 +278,10 @@ define void @masked_store_v16i8(<16 x i8>* %val_ptr, <16 x i8>* %a, <16 x i8>* %
; CHECK-LABEL: masked_store_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a2)
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vmseq.vi v0, v25, 0
-; CHECK-NEXT: vse8.v v26, (a1), v0.t
+; CHECK-NEXT: vle8.v v8, (a2)
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse8.v v9, (a1), v0.t
; CHECK-NEXT: ret
%m = load <16 x i8>, <16 x i8>* %m_ptr
%mask = icmp eq <16 x i8> %m, zeroinitializer
@@ -295,10 +295,10 @@ define void @masked_store_v16i16(<16 x i16>* %val_ptr, <16 x i16>* %a, <16 x i16
; CHECK-LABEL: masked_store_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a2)
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vse16.v v28, (a1), v0.t
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse16.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <16 x i16>, <16 x i16>* %m_ptr
%mask = icmp eq <16 x i16> %m, zeroinitializer
@@ -312,10 +312,10 @@ define void @masked_store_v16i32(<16 x i32>* %val_ptr, <16 x i32>* %a, <16 x i32
; CHECK-LABEL: masked_store_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a2)
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vse32.v v8, (a1), v0.t
+; CHECK-NEXT: vle32.v v8, (a2)
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse32.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <16 x i32>, <16 x i32>* %m_ptr
%mask = icmp eq <16 x i32> %m, zeroinitializer
@@ -347,10 +347,10 @@ define void @masked_store_v32i8(<32 x i8>* %val_ptr, <32 x i8>* %a, <32 x i8>* %
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a2)
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vse8.v v28, (a1), v0.t
+; CHECK-NEXT: vle8.v v8, (a2)
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse8.v v10, (a1), v0.t
; CHECK-NEXT: ret
%m = load <32 x i8>, <32 x i8>* %m_ptr
%mask = icmp eq <32 x i8> %m, zeroinitializer
@@ -365,10 +365,10 @@ define void @masked_store_v32i16(<32 x i16>* %val_ptr, <32 x i16>* %a, <32 x i16
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a2)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vse16.v v8, (a1), v0.t
+; CHECK-NEXT: vle16.v v8, (a2)
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse16.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <32 x i16>, <32 x i16>* %m_ptr
%mask = icmp eq <32 x i16> %m, zeroinitializer
@@ -411,25 +411,25 @@ define void @masked_store_v32i64(<32 x i64>* %val_ptr, <32 x i64>* %a, <32 x i64
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
-; RV32-NEXT: vle64.v v16, (a2)
+; RV32-NEXT: vle64.v v24, (a2)
; RV32-NEXT: addi a2, zero, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vmseq.vv v1, v16, v8
+; RV32-NEXT: vmseq.vv v1, v24, v8
; RV32-NEXT: addi a2, a0, 128
-; RV32-NEXT: vle64.v v16, (a2)
-; RV32-NEXT: vle64.v v24, (a0)
+; RV32-NEXT: vle64.v v24, (a2)
+; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload
-; RV32-NEXT: vmseq.vv v0, v24, v8
+; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
+; RV32-NEXT: vmseq.vv v0, v16, v8
; RV32-NEXT: addi a0, a1, 128
-; RV32-NEXT: vse64.v v16, (a0), v0.t
+; RV32-NEXT: vse64.v v24, (a0), v0.t
; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload
@@ -456,20 +456,20 @@ define void @masked_store_v32i64(<32 x i64>* %val_ptr, <32 x i64>* %a, <32 x i64
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: addi a0, a0, 128
-; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; RV64-NEXT: vmseq.vi v25, v16, 0
-; RV64-NEXT: vse64.v v8, (a1), v0.t
+; RV64-NEXT: vmseq.vi v8, v16, 0
+; RV64-NEXT: vse64.v v24, (a1), v0.t
; RV64-NEXT: addi a0, a1, 128
-; RV64-NEXT: vmv1r.v v0, v25
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a0), v0.t
@@ -491,10 +491,10 @@ define void @masked_store_v64i8(<64 x i8>* %val_ptr, <64 x i8>* %a, <64 x i8>* %
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 64
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a2)
-; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vse8.v v8, (a1), v0.t
+; CHECK-NEXT: vle8.v v8, (a2)
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vse8.v v12, (a1), v0.t
; CHECK-NEXT: ret
%m = load <64 x i8>, <64 x i8>* %m_ptr
%mask = icmp eq <64 x i8> %m, zeroinitializer
@@ -540,20 +540,20 @@ define void @masked_store_v64i32(<64 x i32>* %val_ptr, <64 x i32>* %a, <64 x i32
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmseq.vi v25, v16, 0
-; CHECK-NEXT: vse32.v v8, (a1), v0.t
+; CHECK-NEXT: vmseq.vi v8, v16, 0
+; CHECK-NEXT: vse32.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse32.v v8, (a0), v0.t
@@ -606,20 +606,20 @@ define void @masked_store_v128i16(<128 x i16>* %val_ptr, <128 x i16>* %a, <128 x
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmseq.vi v25, v16, 0
-; CHECK-NEXT: vse16.v v8, (a1), v0.t
+; CHECK-NEXT: vmseq.vi v8, v16, 0
+; CHECK-NEXT: vse16.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse16.v v8, (a0), v0.t
@@ -654,20 +654,20 @@ define void @masked_store_v256i8(<256 x i8>* %val_ptr, <256 x i8>* %a, <256 x i8
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmseq.vi v25, v16, 0
-; CHECK-NEXT: vse8.v v8, (a1), v0.t
+; CHECK-NEXT: vmseq.vi v8, v16, 0
+; CHECK-NEXT: vse8.v v24, (a1), v0.t
; CHECK-NEXT: addi a0, a1, 128
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse8.v v8, (a0), v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
index cbd636088b765..0c7e258adad92 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -10,10 +10,10 @@ define half @vpreduce_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroex
; CHECK-LABEL: vpreduce_fadd_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl)
ret half %r
@@ -23,10 +23,10 @@ define half @vpreduce_ord_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 ze
; CHECK-LABEL: vpreduce_ord_fadd_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl)
ret half %r
@@ -38,10 +38,10 @@ define half @vpreduce_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroex
; CHECK-LABEL: vpreduce_fadd_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl)
ret half %r
@@ -51,10 +51,10 @@ define half @vpreduce_ord_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 ze
; CHECK-LABEL: vpreduce_ord_fadd_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl)
ret half %r
@@ -66,10 +66,10 @@ define float @vpreduce_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 zer
; CHECK-LABEL: vpreduce_fadd_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl)
ret float %r
@@ -79,10 +79,10 @@ define float @vpreduce_ord_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32
; CHECK-LABEL: vpreduce_ord_fadd_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl)
ret float %r
@@ -94,10 +94,10 @@ define float @vpreduce_fadd_v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 zer
; CHECK-LABEL: vpreduce_fadd_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl)
ret float %r
@@ -107,10 +107,10 @@ define float @vpreduce_ord_fadd_v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32
; CHECK-LABEL: vpreduce_ord_fadd_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl)
ret float %r
@@ -122,10 +122,10 @@ define double @vpreduce_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32
; CHECK-LABEL: vpreduce_fadd_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl)
ret double %r
@@ -135,10 +135,10 @@ define double @vpreduce_ord_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m,
; CHECK-LABEL: vpreduce_ord_fadd_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl)
ret double %r
@@ -150,10 +150,10 @@ define double @vpreduce_fadd_v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32
; CHECK-LABEL: vpreduce_fadd_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%r = call reassoc double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl)
ret double %r
@@ -163,10 +163,10 @@ define double @vpreduce_ord_fadd_v4f64(double %s, <4 x double> %v, <4 x i1> %m,
; CHECK-LABEL: vpreduce_ord_fadd_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%r = call double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl)
ret double %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index bc2139c2d81d0..ddef4af7b5584 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -8,8 +8,8 @@ define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <1 x half>, <1 x half>* %x
@@ -21,12 +21,12 @@ define half @vreduce_ord_fadd_v1f16(<1 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <1 x half>, <1 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
@@ -41,12 +41,12 @@ define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
@@ -58,12 +58,12 @@ define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
@@ -78,12 +78,12 @@ define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
@@ -95,12 +95,12 @@ define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
@@ -115,12 +115,12 @@ define half @vreduce_fadd_v8f16(<8 x half>* %x, half %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI6_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <8 x half>, <8 x half>* %x
@@ -132,12 +132,12 @@ define half @vreduce_ord_fadd_v8f16(<8 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x half>, <8 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
@@ -152,12 +152,12 @@ define half @vreduce_fadd_v16f16(<16 x half>* %x, half %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI8_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI8_0)(a1)
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x
@@ -169,12 +169,12 @@ define half @vreduce_ord_fadd_v16f16(<16 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
@@ -190,12 +190,12 @@ define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) {
; RV32-NEXT: lui a2, %hi(.LCPI10_0)
; RV32-NEXT: flh ft0, %lo(.LCPI10_0)(a2)
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV32-NEXT: vle16.v v28, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32-NEXT: vfmv.v.f v25, ft0
+; RV32-NEXT: vfmv.v.f v12, ft0
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV32-NEXT: vfredusum.vs v25, v28, v25
-; RV32-NEXT: vfmv.f.s ft0, v25
+; RV32-NEXT: vfredusum.vs v8, v8, v12
+; RV32-NEXT: vfmv.f.s ft0, v8
; RV32-NEXT: fadd.h fa0, fa0, ft0
; RV32-NEXT: ret
;
@@ -205,12 +205,12 @@ define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) {
; RV64-NEXT: flh ft0, %lo(.LCPI10_0)(a1)
; RV64-NEXT: addi a1, zero, 32
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-NEXT: vle16.v v28, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64-NEXT: vfmv.v.f v25, ft0
+; RV64-NEXT: vfmv.v.f v12, ft0
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-NEXT: vfredusum.vs v25, v28, v25
-; RV64-NEXT: vfmv.f.s ft0, v25
+; RV64-NEXT: vfredusum.vs v8, v8, v12
+; RV64-NEXT: vfmv.f.s ft0, v8
; RV64-NEXT: fadd.h fa0, fa0, ft0
; RV64-NEXT: ret
%v = load <32 x half>, <32 x half>* %x
@@ -223,12 +223,12 @@ define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v28, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x half>, <32 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
@@ -246,10 +246,10 @@ define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) {
; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32-NEXT: vfmv.v.f v25, ft0
+; RV32-NEXT: vfmv.v.f v16, ft0
; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; RV32-NEXT: vfredusum.vs v25, v8, v25
-; RV32-NEXT: vfmv.f.s ft0, v25
+; RV32-NEXT: vfredusum.vs v8, v8, v16
+; RV32-NEXT: vfmv.f.s ft0, v8
; RV32-NEXT: fadd.h fa0, fa0, ft0
; RV32-NEXT: ret
;
@@ -261,10 +261,10 @@ define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) {
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64-NEXT: vfmv.v.f v25, ft0
+; RV64-NEXT: vfmv.v.f v16, ft0
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; RV64-NEXT: vfredusum.vs v25, v8, v25
-; RV64-NEXT: vfmv.f.s ft0, v25
+; RV64-NEXT: vfredusum.vs v8, v8, v16
+; RV64-NEXT: vfmv.f.s ft0, v8
; RV64-NEXT: fadd.h fa0, fa0, ft0
; RV64-NEXT: ret
%v = load <64 x half>, <64 x half>* %x
@@ -279,10 +279,10 @@ define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) {
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <64 x half>, <64 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
@@ -303,10 +303,10 @@ define half @vreduce_fadd_v128f16(<128 x half>* %x, half %s) {
; CHECK-NEXT: flh ft0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x
@@ -323,15 +323,15 @@ define half @vreduce_ord_fadd_v128f16(<128 x half>* %x, half %s) {
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v24, fa0
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v16, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredosum.vs v16, v16, v24
+; CHECK-NEXT: vfmv.f.s ft0, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
@@ -344,8 +344,8 @@ define float @vreduce_fadd_v1f32(<1 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <1 x float>, <1 x float>* %x
@@ -357,12 +357,12 @@ define float @vreduce_ord_fadd_v1f32(<1 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <1 x float>, <1 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
@@ -377,12 +377,12 @@ define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI18_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
@@ -394,12 +394,12 @@ define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
@@ -414,12 +414,12 @@ define float @vreduce_fadd_v4f32(<4 x float>* %x, float %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI20_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
@@ -431,12 +431,12 @@ define float @vreduce_ord_fadd_v4f32(<4 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
@@ -451,12 +451,12 @@ define float @vreduce_fadd_v8f32(<8 x float>* %x, float %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI22_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <8 x float>, <8 x float>* %x
@@ -468,12 +468,12 @@ define float @vreduce_ord_fadd_v8f32(<8 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x float>, <8 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
@@ -488,12 +488,12 @@ define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI24_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v12, ft0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v28, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <16 x float>, <16 x float>* %x
@@ -505,12 +505,12 @@ define float @vreduce_ord_fadd_v16f32(<16 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v28, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x float>, <16 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
@@ -528,10 +528,10 @@ define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) {
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vfmv.v.f v25, ft0
+; RV32-NEXT: vfmv.v.f v16, ft0
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; RV32-NEXT: vfredusum.vs v25, v8, v25
-; RV32-NEXT: vfmv.f.s ft0, v25
+; RV32-NEXT: vfredusum.vs v8, v8, v16
+; RV32-NEXT: vfmv.f.s ft0, v8
; RV32-NEXT: fadd.s fa0, fa0, ft0
; RV32-NEXT: ret
;
@@ -543,10 +543,10 @@ define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) {
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vfmv.v.f v25, ft0
+; RV64-NEXT: vfmv.v.f v16, ft0
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; RV64-NEXT: vfredusum.vs v25, v8, v25
-; RV64-NEXT: vfmv.f.s ft0, v25
+; RV64-NEXT: vfredusum.vs v8, v8, v16
+; RV64-NEXT: vfmv.f.s ft0, v8
; RV64-NEXT: fadd.s fa0, fa0, ft0
; RV64-NEXT: ret
%v = load <32 x float>, <32 x float>* %x
@@ -561,10 +561,10 @@ define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) {
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x float>, <32 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
@@ -585,10 +585,10 @@ define float @vreduce_fadd_v64f32(<64 x float>* %x, float %s) {
; CHECK-NEXT: flw ft0, %lo(.LCPI28_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <64 x float>, <64 x float>* %x
@@ -605,15 +605,15 @@ define float @vreduce_ord_fadd_v64f32(<64 x float>* %x, float %s) {
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v24, fa0
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v16, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredosum.vs v16, v16, v24
+; CHECK-NEXT: vfmv.f.s ft0, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <64 x float>, <64 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
@@ -626,8 +626,8 @@ define double @vreduce_fadd_v1f64(<1 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_fadd_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <1 x double>, <1 x double>* %x
@@ -639,12 +639,12 @@ define double @vreduce_ord_fadd_v1f64(<1 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <1 x double>, <1 x double>* %x
%red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
@@ -659,12 +659,12 @@ define double @vreduce_fadd_v2f64(<2 x double>* %x, double %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI32_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI32_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <2 x double>, <2 x double>* %x
@@ -676,12 +676,12 @@ define double @vreduce_ord_fadd_v2f64(<2 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x double>, <2 x double>* %x
%red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
@@ -696,12 +696,12 @@ define double @vreduce_fadd_v4f64(<4 x double>* %x, double %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI34_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI34_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
@@ -713,12 +713,12 @@ define double @vreduce_ord_fadd_v4f64(<4 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
@@ -733,12 +733,12 @@ define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) {
; CHECK-NEXT: lui a1, %hi(.LCPI36_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI36_0)(a1)
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v12, ft0
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v28, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <8 x double>, <8 x double>* %x
@@ -750,12 +750,12 @@ define double @vreduce_ord_fadd_v8f64(<8 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vle64.v v28, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v28, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x double>, <8 x double>* %x
%red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
@@ -772,10 +772,10 @@ define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) {
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <16 x double>, <16 x double>* %x
@@ -789,10 +789,10 @@ define double @vreduce_ord_fadd_v16f64(<16 x double>* %x, double %s) {
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x double>, <16 x double>* %x
%red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
@@ -812,10 +812,10 @@ define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) {
; CHECK-NEXT: fld ft0, %lo(.LCPI40_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x
@@ -831,15 +831,15 @@ define double @vreduce_ord_fadd_v32f64(<32 x double>* %x, double %s) {
; CHECK-NEXT: vle64.v v8, (a1)
; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v24, fa0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v16, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredosum.vs v16, v16, v24
+; CHECK-NEXT: vfmv.f.s ft0, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
@@ -854,12 +854,12 @@ define half @vreduce_fmin_v2f16(<2 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI42_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI42_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
%red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v)
@@ -874,12 +874,12 @@ define half @vreduce_fmin_v4f16(<4 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI43_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI43_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
@@ -892,12 +892,12 @@ define half @vreduce_fmin_v4f16_nonans(<4 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI44_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI44_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
@@ -910,12 +910,12 @@ define half @vreduce_fmin_v4f16_nonans_noinfs(<4 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI45_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI45_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
@@ -936,10 +936,10 @@ define half @vreduce_fmin_v128f16(<128 x half>* %x) {
; CHECK-NEXT: flh ft0, %lo(.LCPI46_0)(a0)
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x
%red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v)
@@ -954,12 +954,12 @@ define float @vreduce_fmin_v2f32(<2 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI47_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
%red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v)
@@ -974,12 +974,12 @@ define float @vreduce_fmin_v4f32(<4 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI48_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI48_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
@@ -992,12 +992,12 @@ define float @vreduce_fmin_v4f32_nonans(<4 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI49_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI49_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
@@ -1010,12 +1010,12 @@ define float @vreduce_fmin_v4f32_nonans_noinfs(<4 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI50_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI50_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
@@ -1042,10 +1042,10 @@ define float @vreduce_fmin_v128f32(<128 x float>* %x) {
; CHECK-NEXT: vfmin.vv v16, v24, v0
; CHECK-NEXT: vfmin.vv v8, v16, v8
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <128 x float>, <128 x float>* %x
%red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v)
@@ -1060,12 +1060,12 @@ define double @vreduce_fmin_v2f64(<2 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI52_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI52_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x double>, <2 x double>* %x
%red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v)
@@ -1080,12 +1080,12 @@ define double @vreduce_fmin_v4f64(<4 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI53_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI53_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
@@ -1098,12 +1098,12 @@ define double @vreduce_fmin_v4f64_nonans(<4 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI54_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI54_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
@@ -1116,12 +1116,12 @@ define double @vreduce_fmin_v4f64_nonans_noinfs(<4 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI55_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI55_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
@@ -1141,10 +1141,10 @@ define double @vreduce_fmin_v32f64(<32 x double>* %x) {
; CHECK-NEXT: fld ft0, %lo(.LCPI56_0)(a0)
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x
%red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v)
@@ -1159,12 +1159,12 @@ define half @vreduce_fmax_v2f16(<2 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI57_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI57_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
%red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v)
@@ -1179,12 +1179,12 @@ define half @vreduce_fmax_v4f16(<4 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI58_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI58_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
@@ -1197,12 +1197,12 @@ define half @vreduce_fmax_v4f16_nonans(<4 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI59_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI59_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
@@ -1215,12 +1215,12 @@ define half @vreduce_fmax_v4f16_nonans_noinfs(<4 x half>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI60_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI60_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
%red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
@@ -1241,10 +1241,10 @@ define half @vreduce_fmax_v128f16(<128 x half>* %x) {
; CHECK-NEXT: flh ft0, %lo(.LCPI61_0)(a0)
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x
%red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v)
@@ -1259,12 +1259,12 @@ define float @vreduce_fmax_v2f32(<2 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI62_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI62_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
%red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v)
@@ -1279,12 +1279,12 @@ define float @vreduce_fmax_v4f32(<4 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI63_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI63_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
@@ -1297,12 +1297,12 @@ define float @vreduce_fmax_v4f32_nonans(<4 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI64_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI64_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
@@ -1315,12 +1315,12 @@ define float @vreduce_fmax_v4f32_nonans_noinfs(<4 x float>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI65_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI65_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x
%red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
@@ -1347,10 +1347,10 @@ define float @vreduce_fmax_v128f32(<128 x float>* %x) {
; CHECK-NEXT: vfmax.vv v16, v24, v0
; CHECK-NEXT: vfmax.vv v8, v16, v8
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <128 x float>, <128 x float>* %x
%red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v)
@@ -1365,12 +1365,12 @@ define double @vreduce_fmax_v2f64(<2 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI67_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI67_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vle64.v v25, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v25, v26
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x double>, <2 x double>* %x
%red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v)
@@ -1385,12 +1385,12 @@ define double @vreduce_fmax_v4f64(<4 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI68_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI68_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
@@ -1403,12 +1403,12 @@ define double @vreduce_fmax_v4f64_nonans(<4 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI69_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI69_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
@@ -1421,12 +1421,12 @@ define double @vreduce_fmax_v4f64_nonans_noinfs(<4 x double>* %x) {
; CHECK-NEXT: lui a1, %hi(.LCPI70_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI70_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vle64.v v26, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v26, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x
%red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
@@ -1446,10 +1446,10 @@ define double @vreduce_fmax_v32f64(<32 x double>* %x) {
; CHECK-NEXT: fld ft0, %lo(.LCPI71_0)(a0)
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x
%red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 48e51f5fb2fad..163e561f9ad85 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -10,10 +10,10 @@ define signext i8 @vpreduce_add_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
; CHECK-LABEL: vpreduce_add_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.add.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -26,10 +26,10 @@ define signext i8 @vpreduce_umax_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -41,10 +41,10 @@ define signext i8 @vpreduce_smax_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i
; CHECK-LABEL: vpreduce_smax_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -57,10 +57,10 @@ define signext i8 @vpreduce_umin_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -72,10 +72,10 @@ define signext i8 @vpreduce_smin_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i
; CHECK-LABEL: vpreduce_smin_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -87,10 +87,10 @@ define signext i8 @vpreduce_and_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
; CHECK-LABEL: vpreduce_and_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.and.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -102,10 +102,10 @@ define signext i8 @vpreduce_or_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32
; CHECK-LABEL: vpreduce_or_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.or.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -117,10 +117,10 @@ define signext i8 @vpreduce_xor_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
; CHECK-LABEL: vpreduce_xor_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.xor.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl)
ret i8 %r
@@ -132,10 +132,10 @@ define signext i8 @vpreduce_add_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
; CHECK-LABEL: vpreduce_add_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.add.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -148,10 +148,10 @@ define signext i8 @vpreduce_umax_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -163,10 +163,10 @@ define signext i8 @vpreduce_smax_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i
; CHECK-LABEL: vpreduce_smax_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -179,10 +179,10 @@ define signext i8 @vpreduce_umin_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -194,10 +194,10 @@ define signext i8 @vpreduce_smin_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i
; CHECK-LABEL: vpreduce_smin_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -209,10 +209,10 @@ define signext i8 @vpreduce_and_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
; CHECK-LABEL: vpreduce_and_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.and.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -224,10 +224,10 @@ define signext i8 @vpreduce_or_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32
; CHECK-LABEL: vpreduce_or_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.or.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -239,10 +239,10 @@ define signext i8 @vpreduce_xor_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
; CHECK-LABEL: vpreduce_xor_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.xor.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl)
ret i8 %r
@@ -254,10 +254,10 @@ define signext i16 @vpreduce_add_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m
; CHECK-LABEL: vpreduce_add_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.add.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -272,10 +272,10 @@ define signext i16 @vpreduce_umax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v2i16:
@@ -284,10 +284,10 @@ define signext i16 @vpreduce_umax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -299,10 +299,10 @@ define signext i16 @vpreduce_smax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %
; CHECK-LABEL: vpreduce_smax_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -317,10 +317,10 @@ define signext i16 @vpreduce_umin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v2i16:
@@ -329,10 +329,10 @@ define signext i16 @vpreduce_umin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -344,10 +344,10 @@ define signext i16 @vpreduce_smin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %
; CHECK-LABEL: vpreduce_smin_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -359,10 +359,10 @@ define signext i16 @vpreduce_and_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m
; CHECK-LABEL: vpreduce_and_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.and.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -374,10 +374,10 @@ define signext i16 @vpreduce_or_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m,
; CHECK-LABEL: vpreduce_or_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.or.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -389,10 +389,10 @@ define signext i16 @vpreduce_xor_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m
; CHECK-LABEL: vpreduce_xor_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.xor.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl)
ret i16 %r
@@ -404,10 +404,10 @@ define signext i16 @vpreduce_add_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m
; CHECK-LABEL: vpreduce_add_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.add.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -422,10 +422,10 @@ define signext i16 @vpreduce_umax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v4i16:
@@ -434,10 +434,10 @@ define signext i16 @vpreduce_umax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -449,10 +449,10 @@ define signext i16 @vpreduce_smax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %
; CHECK-LABEL: vpreduce_smax_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -467,10 +467,10 @@ define signext i16 @vpreduce_umin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v4i16:
@@ -479,10 +479,10 @@ define signext i16 @vpreduce_umin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -494,10 +494,10 @@ define signext i16 @vpreduce_smin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %
; CHECK-LABEL: vpreduce_smin_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -509,10 +509,10 @@ define signext i16 @vpreduce_and_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m
; CHECK-LABEL: vpreduce_and_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.and.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -524,10 +524,10 @@ define signext i16 @vpreduce_or_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m,
; CHECK-LABEL: vpreduce_or_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.or.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -539,10 +539,10 @@ define signext i16 @vpreduce_xor_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m
; CHECK-LABEL: vpreduce_xor_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.xor.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl)
ret i16 %r
@@ -554,10 +554,10 @@ define signext i32 @vpreduce_add_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m
; CHECK-LABEL: vpreduce_add_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.add.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -569,10 +569,10 @@ define signext i32 @vpreduce_umax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
; RV32-LABEL: vpreduce_umax_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v2i32:
@@ -580,10 +580,10 @@ define signext i32 @vpreduce_umax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -595,10 +595,10 @@ define signext i32 @vpreduce_smax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
; CHECK-LABEL: vpreduce_smax_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -610,10 +610,10 @@ define signext i32 @vpreduce_umin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
; RV32-LABEL: vpreduce_umin_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v2i32:
@@ -621,10 +621,10 @@ define signext i32 @vpreduce_umin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -636,10 +636,10 @@ define signext i32 @vpreduce_smin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
; CHECK-LABEL: vpreduce_smin_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -651,10 +651,10 @@ define signext i32 @vpreduce_and_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m
; CHECK-LABEL: vpreduce_and_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.and.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -666,10 +666,10 @@ define signext i32 @vpreduce_or_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m,
; CHECK-LABEL: vpreduce_or_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.or.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -681,10 +681,10 @@ define signext i32 @vpreduce_xor_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m
; CHECK-LABEL: vpreduce_xor_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.xor.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
@@ -696,10 +696,10 @@ define signext i32 @vpreduce_add_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m
; CHECK-LABEL: vpreduce_add_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.add.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -711,10 +711,10 @@ define signext i32 @vpreduce_umax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
; RV32-LABEL: vpreduce_umax_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v4i32:
@@ -722,10 +722,10 @@ define signext i32 @vpreduce_umax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -737,10 +737,10 @@ define signext i32 @vpreduce_smax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
; CHECK-LABEL: vpreduce_smax_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -752,10 +752,10 @@ define signext i32 @vpreduce_umin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
; RV32-LABEL: vpreduce_umin_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v4i32:
@@ -763,10 +763,10 @@ define signext i32 @vpreduce_umin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -778,10 +778,10 @@ define signext i32 @vpreduce_smin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
; CHECK-LABEL: vpreduce_smin_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -793,10 +793,10 @@ define signext i32 @vpreduce_and_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m
; CHECK-LABEL: vpreduce_and_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.and.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -808,10 +808,10 @@ define signext i32 @vpreduce_or_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m,
; CHECK-LABEL: vpreduce_or_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.or.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -823,10 +823,10 @@ define signext i32 @vpreduce_xor_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m
; CHECK-LABEL: vpreduce_xor_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.xor.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
@@ -843,24 +843,24 @@ define signext i64 @vpreduce_add_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_add_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.add.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -877,24 +877,24 @@ define signext i64 @vpreduce_umax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -911,24 +911,24 @@ define signext i64 @vpreduce_smax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smax_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -945,24 +945,24 @@ define signext i64 @vpreduce_umin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -979,24 +979,24 @@ define signext i64 @vpreduce_smin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smin_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1013,24 +1013,24 @@ define signext i64 @vpreduce_and_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_and_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.and.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1047,24 +1047,24 @@ define signext i64 @vpreduce_or_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_or_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.or.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1081,24 +1081,24 @@ define signext i64 @vpreduce_xor_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_xor_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.xor.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1115,24 +1115,24 @@ define signext i64 @vpreduce_add_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_add_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.add.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1149,24 +1149,24 @@ define signext i64 @vpreduce_umax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1183,24 +1183,24 @@ define signext i64 @vpreduce_smax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smax_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1217,24 +1217,24 @@ define signext i64 @vpreduce_umin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1251,24 +1251,24 @@ define signext i64 @vpreduce_smin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smin_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1285,24 +1285,24 @@ define signext i64 @vpreduce_and_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_and_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.and.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1319,24 +1319,24 @@ define signext i64 @vpreduce_or_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_or_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.or.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1353,24 +1353,24 @@ define signext i64 @vpreduce_xor_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_xor_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.xor.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl)
ret i64 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
index 49997585b93ed..8602731a57310 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
@@ -8,8 +8,8 @@ define i8 @vreduce_add_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_add_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %v)
@@ -22,12 +22,12 @@ define i8 @vreduce_add_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_add_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v)
@@ -40,12 +40,12 @@ define i8 @vreduce_add_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_add_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v)
@@ -58,12 +58,12 @@ define i8 @vreduce_add_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_add_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v)
@@ -76,12 +76,12 @@ define i8 @vreduce_add_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_add_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v)
@@ -95,12 +95,12 @@ define i8 @vreduce_add_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v)
@@ -114,12 +114,12 @@ define i8 @vreduce_add_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %v)
@@ -135,10 +135,10 @@ define i8 @vreduce_add_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %v)
@@ -157,10 +157,10 @@ define i8 @vreduce_add_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %v)
@@ -173,8 +173,8 @@ define i16 @vreduce_add_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_add_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %v)
@@ -187,12 +187,12 @@ define i16 @vreduce_add_v2i16(<2 x i16>* %x) {
; CHECK-LABEL: vreduce_add_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v)
@@ -205,12 +205,12 @@ define i16 @vreduce_add_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_add_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v)
@@ -223,12 +223,12 @@ define i16 @vreduce_add_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_add_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v)
@@ -241,12 +241,12 @@ define i16 @vreduce_add_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_add_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v)
@@ -260,12 +260,12 @@ define i16 @vreduce_add_v32i16(<32 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %v)
@@ -281,10 +281,10 @@ define i16 @vreduce_add_v64i16(<64 x i16>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %v)
@@ -303,10 +303,10 @@ define i16 @vreduce_add_v128i16(<128 x i16>* %x) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %v)
@@ -319,8 +319,8 @@ define i32 @vreduce_add_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_add_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %v)
@@ -333,12 +333,12 @@ define i32 @vreduce_add_v2i32(<2 x i32>* %x) {
; CHECK-LABEL: vreduce_add_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v)
@@ -351,12 +351,12 @@ define i32 @vreduce_add_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_add_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v)
@@ -369,12 +369,12 @@ define i32 @vreduce_add_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_add_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v)
@@ -387,12 +387,12 @@ define i32 @vreduce_add_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_add_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v)
@@ -408,10 +408,10 @@ define i32 @vreduce_add_v32i32(<32 x i32>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %v)
@@ -430,10 +430,10 @@ define i32 @vreduce_add_v64i32(<64 x i32>* %x) {
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %v)
@@ -446,18 +446,18 @@ define i64 @vreduce_add_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_add_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_add_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %v)
@@ -470,27 +470,27 @@ define i64 @vreduce_add_v2i64(<2 x i64>* %x) {
; RV32-LABEL: vreduce_add_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredsum.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_add_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredsum.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v)
@@ -503,27 +503,27 @@ define i64 @vreduce_add_v4i64(<4 x i64>* %x) {
; RV32-LABEL: vreduce_add_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredsum.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_add_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredsum.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)
@@ -536,27 +536,27 @@ define i64 @vreduce_add_v8i64(<8 x i64>* %x) {
; RV32-LABEL: vreduce_add_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredsum.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_add_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredsum.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %v)
@@ -571,14 +571,14 @@ define i64 @vreduce_add_v16i64(<16 x i64>* %x) {
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_add_v16i64:
@@ -586,10 +586,10 @@ define i64 @vreduce_add_v16i64(<16 x i64>* %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %v)
@@ -607,14 +607,14 @@ define i64 @vreduce_add_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_add_v32i64:
@@ -625,10 +625,10 @@ define i64 @vreduce_add_v32i64(<32 x i64>* %x) {
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %v)
@@ -652,14 +652,14 @@ define i64 @vreduce_add_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vadd.vv v8, v8, v0
; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_add_v64i64:
@@ -676,10 +676,10 @@ define i64 @vreduce_add_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: vadd.vv v8, v8, v0
; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.add.v64i64(<64 x i64> %v)
@@ -692,8 +692,8 @@ define i8 @vreduce_and_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_and_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %v)
@@ -706,12 +706,12 @@ define i8 @vreduce_and_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_and_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v)
@@ -724,12 +724,12 @@ define i8 @vreduce_and_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_and_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v)
@@ -742,12 +742,12 @@ define i8 @vreduce_and_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_and_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v)
@@ -760,12 +760,12 @@ define i8 @vreduce_and_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_and_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %v)
@@ -779,12 +779,12 @@ define i8 @vreduce_and_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v)
@@ -798,12 +798,12 @@ define i8 @vreduce_and_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %v)
@@ -819,10 +819,10 @@ define i8 @vreduce_and_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %v)
@@ -841,10 +841,10 @@ define i8 @vreduce_and_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %v)
@@ -857,8 +857,8 @@ define i16 @vreduce_and_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_and_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %v)
@@ -871,12 +871,12 @@ define i16 @vreduce_and_v2i16(<2 x i16>* %x) {
; CHECK-LABEL: vreduce_and_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v)
@@ -889,12 +889,12 @@ define i16 @vreduce_and_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_and_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)
@@ -907,12 +907,12 @@ define i16 @vreduce_and_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_and_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %v)
@@ -925,12 +925,12 @@ define i16 @vreduce_and_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_and_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)
@@ -944,12 +944,12 @@ define i16 @vreduce_and_v32i16(<32 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %v)
@@ -965,10 +965,10 @@ define i16 @vreduce_and_v64i16(<64 x i16>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %v)
@@ -987,10 +987,10 @@ define i16 @vreduce_and_v128i16(<128 x i16>* %x) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %v)
@@ -1003,8 +1003,8 @@ define i32 @vreduce_and_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_and_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %v)
@@ -1017,12 +1017,12 @@ define i32 @vreduce_and_v2i32(<2 x i32>* %x) {
; CHECK-LABEL: vreduce_and_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v)
@@ -1035,12 +1035,12 @@ define i32 @vreduce_and_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_and_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vredand.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v)
@@ -1053,12 +1053,12 @@ define i32 @vreduce_and_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_and_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)
@@ -1071,12 +1071,12 @@ define i32 @vreduce_and_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_and_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v)
@@ -1092,10 +1092,10 @@ define i32 @vreduce_and_v32i32(<32 x i32>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %v)
@@ -1114,10 +1114,10 @@ define i32 @vreduce_and_v64i32(<64 x i32>* %x) {
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %v)
@@ -1130,18 +1130,18 @@ define i64 @vreduce_and_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_and_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_and_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %v)
@@ -1154,27 +1154,27 @@ define i64 @vreduce_and_v2i64(<2 x i64>* %x) {
; RV32-LABEL: vreduce_and_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, -1
+; RV32-NEXT: vmv.v.i v9, -1
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredand.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_and_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, -1
+; RV64-NEXT: vmv.v.i v9, -1
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredand.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %v)
@@ -1187,27 +1187,27 @@ define i64 @vreduce_and_v4i64(<4 x i64>* %x) {
; RV32-LABEL: vreduce_and_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v10, -1
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredand.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_and_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v10, -1
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredand.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
@@ -1220,27 +1220,27 @@ define i64 @vreduce_and_v8i64(<8 x i64>* %x) {
; RV32-LABEL: vreduce_and_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v12, -1
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredand.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_and_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v12, -1
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredand.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %v)
@@ -1255,14 +1255,14 @@ define i64 @vreduce_and_v16i64(<16 x i64>* %x) {
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredand.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_and_v16i64:
@@ -1270,10 +1270,10 @@ define i64 @vreduce_and_v16i64(<16 x i64>* %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v16, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredand.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %v)
@@ -1291,14 +1291,14 @@ define i64 @vreduce_and_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredand.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_and_v32i64:
@@ -1309,10 +1309,10 @@ define i64 @vreduce_and_v32i64(<32 x i64>* %x) {
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v16, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredand.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %v)
@@ -1336,14 +1336,14 @@ define i64 @vreduce_and_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredand.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_and_v64i64:
@@ -1360,10 +1360,10 @@ define i64 @vreduce_and_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: vand.vv v8, v8, v0
; RV64-NEXT: vand.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v16, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredand.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.and.v64i64(<64 x i64> %v)
@@ -1376,8 +1376,8 @@ define i8 @vreduce_or_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_or_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %v)
@@ -1390,12 +1390,12 @@ define i8 @vreduce_or_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_or_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> %v)
@@ -1408,12 +1408,12 @@ define i8 @vreduce_or_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_or_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %v)
@@ -1426,12 +1426,12 @@ define i8 @vreduce_or_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_or_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %v)
@@ -1444,12 +1444,12 @@ define i8 @vreduce_or_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_or_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %v)
@@ -1463,12 +1463,12 @@ define i8 @vreduce_or_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v)
@@ -1482,12 +1482,12 @@ define i8 @vreduce_or_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %v)
@@ -1503,10 +1503,10 @@ define i8 @vreduce_or_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %v)
@@ -1525,10 +1525,10 @@ define i8 @vreduce_or_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %v)
@@ -1541,8 +1541,8 @@ define i16 @vreduce_or_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_or_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v1i16(<1 x i16> %v)
@@ -1555,12 +1555,12 @@ define i16 @vreduce_or_v2i16(<2 x i16>* %x) {
; CHECK-LABEL: vreduce_or_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %v)
@@ -1573,12 +1573,12 @@ define i16 @vreduce_or_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_or_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v)
@@ -1591,12 +1591,12 @@ define i16 @vreduce_or_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_or_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %v)
@@ -1609,12 +1609,12 @@ define i16 @vreduce_or_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_or_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v)
@@ -1628,12 +1628,12 @@ define i16 @vreduce_or_v32i16(<32 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %v)
@@ -1649,10 +1649,10 @@ define i16 @vreduce_or_v64i16(<64 x i16>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %v)
@@ -1671,10 +1671,10 @@ define i16 @vreduce_or_v128i16(<128 x i16>* %x) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %v)
@@ -1687,8 +1687,8 @@ define i32 @vreduce_or_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_or_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.or.v1i32(<1 x i32> %v)
@@ -1701,12 +1701,12 @@ define i32 @vreduce_or_v2i32(<2 x i32>* %x) {
; CHECK-LABEL: vreduce_or_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %v)
@@ -1719,12 +1719,12 @@ define i32 @vreduce_or_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_or_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vredor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %v)
@@ -1737,12 +1737,12 @@ define i32 @vreduce_or_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_or_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v)
@@ -1755,12 +1755,12 @@ define i32 @vreduce_or_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_or_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %v)
@@ -1776,10 +1776,10 @@ define i32 @vreduce_or_v32i32(<32 x i32>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %v)
@@ -1798,10 +1798,10 @@ define i32 @vreduce_or_v64i32(<64 x i32>* %x) {
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %v)
@@ -1814,18 +1814,18 @@ define i64 @vreduce_or_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_or_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_or_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %v)
@@ -1838,27 +1838,27 @@ define i64 @vreduce_or_v2i64(<2 x i64>* %x) {
; RV32-LABEL: vreduce_or_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredor.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_or_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredor.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %v)
@@ -1871,27 +1871,27 @@ define i64 @vreduce_or_v4i64(<4 x i64>* %x) {
; RV32-LABEL: vreduce_or_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredor.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_or_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredor.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
@@ -1904,27 +1904,27 @@ define i64 @vreduce_or_v8i64(<8 x i64>* %x) {
; RV32-LABEL: vreduce_or_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredor.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_or_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredor.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %v)
@@ -1939,14 +1939,14 @@ define i64 @vreduce_or_v16i64(<16 x i64>* %x) {
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredor.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_or_v16i64:
@@ -1954,10 +1954,10 @@ define i64 @vreduce_or_v16i64(<16 x i64>* %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredor.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %v)
@@ -1975,14 +1975,14 @@ define i64 @vreduce_or_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredor.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_or_v32i64:
@@ -1993,10 +1993,10 @@ define i64 @vreduce_or_v32i64(<32 x i64>* %x) {
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredor.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %v)
@@ -2020,14 +2020,14 @@ define i64 @vreduce_or_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vor.vv v8, v8, v0
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredor.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_or_v64i64:
@@ -2044,10 +2044,10 @@ define i64 @vreduce_or_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: vor.vv v8, v8, v0
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredor.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.or.v64i64(<64 x i64> %v)
@@ -2060,8 +2060,8 @@ define i8 @vreduce_xor_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_xor_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> %v)
@@ -2074,12 +2074,12 @@ define i8 @vreduce_xor_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_xor_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> %v)
@@ -2092,12 +2092,12 @@ define i8 @vreduce_xor_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_xor_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %v)
@@ -2110,12 +2110,12 @@ define i8 @vreduce_xor_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_xor_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %v)
@@ -2128,12 +2128,12 @@ define i8 @vreduce_xor_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_xor_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %v)
@@ -2147,12 +2147,12 @@ define i8 @vreduce_xor_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %v)
@@ -2166,12 +2166,12 @@ define i8 @vreduce_xor_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %v)
@@ -2187,10 +2187,10 @@ define i8 @vreduce_xor_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %v)
@@ -2209,10 +2209,10 @@ define i8 @vreduce_xor_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vxor.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %v)
@@ -2225,8 +2225,8 @@ define i16 @vreduce_xor_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_xor_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v1i16(<1 x i16> %v)
@@ -2239,12 +2239,12 @@ define i16 @vreduce_xor_v2i16(<2 x i16>* %x) {
; CHECK-LABEL: vreduce_xor_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %v)
@@ -2257,12 +2257,12 @@ define i16 @vreduce_xor_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_xor_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v)
@@ -2275,12 +2275,12 @@ define i16 @vreduce_xor_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_xor_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %v)
@@ -2293,12 +2293,12 @@ define i16 @vreduce_xor_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_xor_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %v)
@@ -2312,12 +2312,12 @@ define i16 @vreduce_xor_v32i16(<32 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %v)
@@ -2333,10 +2333,10 @@ define i16 @vreduce_xor_v64i16(<64 x i16>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %v)
@@ -2355,10 +2355,10 @@ define i16 @vreduce_xor_v128i16(<128 x i16>* %x) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vxor.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %v)
@@ -2371,8 +2371,8 @@ define i32 @vreduce_xor_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_xor_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> %v)
@@ -2385,12 +2385,12 @@ define i32 @vreduce_xor_v2i32(<2 x i32>* %x) {
; CHECK-LABEL: vreduce_xor_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %v)
@@ -2403,12 +2403,12 @@ define i32 @vreduce_xor_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_xor_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %v)
@@ -2421,12 +2421,12 @@ define i32 @vreduce_xor_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_xor_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %v)
@@ -2439,12 +2439,12 @@ define i32 @vreduce_xor_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_xor_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %v)
@@ -2460,10 +2460,10 @@ define i32 @vreduce_xor_v32i32(<32 x i32>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %v)
@@ -2482,10 +2482,10 @@ define i32 @vreduce_xor_v64i32(<64 x i32>* %x) {
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vxor.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %v)
@@ -2498,18 +2498,18 @@ define i64 @vreduce_xor_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_xor_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_xor_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %v)
@@ -2522,27 +2522,27 @@ define i64 @vreduce_xor_v2i64(<2 x i64>* %x) {
; RV32-LABEL: vreduce_xor_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredxor.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_xor_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredxor.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %v)
@@ -2555,27 +2555,27 @@ define i64 @vreduce_xor_v4i64(<4 x i64>* %x) {
; RV32-LABEL: vreduce_xor_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredxor.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_xor_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredxor.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)
@@ -2588,27 +2588,27 @@ define i64 @vreduce_xor_v8i64(<8 x i64>* %x) {
; RV32-LABEL: vreduce_xor_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredxor.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_xor_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredxor.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %v)
@@ -2623,14 +2623,14 @@ define i64 @vreduce_xor_v16i64(<16 x i64>* %x) {
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_xor_v16i64:
@@ -2638,10 +2638,10 @@ define i64 @vreduce_xor_v16i64(<16 x i64>* %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %v)
@@ -2659,14 +2659,14 @@ define i64 @vreduce_xor_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: vxor.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_xor_v32i64:
@@ -2677,10 +2677,10 @@ define i64 @vreduce_xor_v32i64(<32 x i64>* %x) {
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vxor.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %v)
@@ -2704,14 +2704,14 @@ define i64 @vreduce_xor_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vxor.vv v8, v8, v0
; RV32-NEXT: vxor.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_xor_v64i64:
@@ -2728,10 +2728,10 @@ define i64 @vreduce_xor_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: vxor.vv v8, v8, v0
; RV64-NEXT: vxor.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.xor.v64i64(<64 x i64> %v)
@@ -2744,8 +2744,8 @@ define i8 @vreduce_smin_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_smin_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v1i8(<1 x i8> %v)
@@ -2758,13 +2758,13 @@ define i8 @vreduce_smin_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_smin_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v)
@@ -2777,13 +2777,13 @@ define i8 @vreduce_smin_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_smin_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v)
@@ -2796,13 +2796,13 @@ define i8 @vreduce_smin_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_smin_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)
@@ -2815,13 +2815,13 @@ define i8 @vreduce_smin_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_smin_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v)
@@ -2835,13 +2835,13 @@ define i8 @vreduce_smin_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v)
@@ -2855,13 +2855,13 @@ define i8 @vreduce_smin_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> %v)
@@ -2878,10 +2878,10 @@ define i8 @vreduce_smin_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %v)
@@ -2901,10 +2901,10 @@ define i8 @vreduce_smin_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vmin.vv v8, v8, v16
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %v)
@@ -2917,8 +2917,8 @@ define i16 @vreduce_smin_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_smin_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v1i16(<1 x i16> %v)
@@ -2931,27 +2931,27 @@ define i16 @vreduce_smin_v2i16(<2 x i16>* %x) {
; RV32-LABEL: vreduce_smin_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vredmin.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vle16.v v25, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vredmin.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v)
@@ -2964,27 +2964,27 @@ define i16 @vreduce_smin_v4i16(<4 x i16>* %x) {
; RV32-LABEL: vreduce_smin_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vredmin.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v4i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV64-NEXT: vle16.v v25, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV64-NEXT: vredmin.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)
@@ -2997,27 +2997,27 @@ define i16 @vreduce_smin_v8i16(<8 x i16>* %x) {
; RV32-LABEL: vreduce_smin_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vle16.v v25, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vredmin.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64-NEXT: vle16.v v25, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64-NEXT: vredmin.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v)
@@ -3030,27 +3030,27 @@ define i16 @vreduce_smin_v16i16(<16 x i16>* %x) {
; RV32-LABEL: vreduce_smin_v16i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; RV32-NEXT: vle16.v v26, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; RV32-NEXT: vredmin.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v16i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; RV64-NEXT: vle16.v v26, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; RV64-NEXT: vredmin.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v)
@@ -3064,28 +3064,28 @@ define i16 @vreduce_smin_v32i16(<32 x i16>* %x) {
; RV32: # %bb.0:
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV32-NEXT: vle16.v v28, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV32-NEXT: vredmin.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v32i16:
; RV64: # %bb.0:
; RV64-NEXT: addi a1, zero, 32
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-NEXT: vle16.v v28, (a0)
+; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-NEXT: vredmin.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> %v)
@@ -3103,10 +3103,10 @@ define i16 @vreduce_smin_v64i16(<64 x i16>* %x) {
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v64i16:
@@ -3117,10 +3117,10 @@ define i16 @vreduce_smin_v64i16(<64 x i16>* %x) {
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> %v)
@@ -3141,10 +3141,10 @@ define i16 @vreduce_smin_v128i16(<128 x i16>* %x) {
; RV32-NEXT: lui a0, 8
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v128i16:
@@ -3158,10 +3158,10 @@ define i16 @vreduce_smin_v128i16(<128 x i16>* %x) {
; RV64-NEXT: lui a0, 8
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %v)
@@ -3174,8 +3174,8 @@ define i32 @vreduce_smin_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_smin_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> %v)
@@ -3188,27 +3188,27 @@ define i32 @vreduce_smin_v2i32(<2 x i32>* %x) {
; RV32-LABEL: vreduce_smin_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vredmin.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: lui a0, 524288
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vredmin.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v)
@@ -3221,27 +3221,27 @@ define i32 @vreduce_smin_v4i32(<4 x i32>* %x) {
; RV32-LABEL: vreduce_smin_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v26, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vredmin.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: lui a0, 524288
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vredmin.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v)
@@ -3254,27 +3254,27 @@ define i32 @vreduce_smin_v8i32(<8 x i32>* %x) {
; RV32-LABEL: vreduce_smin_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vle32.v v26, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vredmin.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV64-NEXT: vle32.v v26, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: lui a0, 524288
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV64-NEXT: vredmin.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v)
@@ -3287,27 +3287,27 @@ define i32 @vreduce_smin_v16i32(<16 x i32>* %x) {
; RV32-LABEL: vreduce_smin_v16i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vle32.v v28, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vredmin.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v16i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV64-NEXT: vle32.v v28, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: lui a0, 524288
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV64-NEXT: vredmin.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %v)
@@ -3325,10 +3325,10 @@ define i32 @vreduce_smin_v32i32(<32 x i32>* %x) {
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v32i32:
@@ -3339,10 +3339,10 @@ define i32 @vreduce_smin_v32i32(<32 x i32>* %x) {
; RV64-NEXT: lui a0, 524288
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> %v)
@@ -3363,10 +3363,10 @@ define i32 @vreduce_smin_v64i32(<64 x i32>* %x) {
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v64i32:
@@ -3380,10 +3380,10 @@ define i32 @vreduce_smin_v64i32(<64 x i32>* %x) {
; RV64-NEXT: lui a0, 524288
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %v)
@@ -3396,18 +3396,18 @@ define i64 @vreduce_smin_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_smin_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> %v)
@@ -3422,7 +3422,7 @@ define i64 @vreduce_smin_v2i64(<2 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, -1
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288
@@ -3430,28 +3430,28 @@ define i64 @vreduce_smin_v2i64(<2 x i64>* %x) {
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredmin.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredmin.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %v)
@@ -3466,7 +3466,7 @@ define i64 @vreduce_smin_v4i64(<4 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, -1
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288
@@ -3474,28 +3474,28 @@ define i64 @vreduce_smin_v4i64(<4 x i64>* %x) {
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredmin.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredmin.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
@@ -3510,7 +3510,7 @@ define i64 @vreduce_smin_v8i64(<8 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, -1
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288
@@ -3518,28 +3518,28 @@ define i64 @vreduce_smin_v8i64(<8 x i64>* %x) {
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredmin.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smin_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredmin.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %v)
@@ -3562,14 +3562,14 @@ define i64 @vreduce_smin_v16i64(<16 x i64>* %x) {
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -3580,10 +3580,10 @@ define i64 @vreduce_smin_v16i64(<16 x i64>* %x) {
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> %v)
@@ -3609,14 +3609,14 @@ define i64 @vreduce_smin_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vmin.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -3630,10 +3630,10 @@ define i64 @vreduce_smin_v32i64(<32 x i64>* %x) {
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %v)
@@ -3664,14 +3664,14 @@ define i64 @vreduce_smin_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vmin.vv v8, v8, v24
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -3691,10 +3691,10 @@ define i64 @vreduce_smin_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.smin.v64i64(<64 x i64> %v)
@@ -3707,8 +3707,8 @@ define i8 @vreduce_smax_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_smax_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v1i8(<1 x i8> %v)
@@ -3721,13 +3721,13 @@ define i8 @vreduce_smax_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_smax_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v)
@@ -3740,13 +3740,13 @@ define i8 @vreduce_smax_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_smax_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v)
@@ -3759,13 +3759,13 @@ define i8 @vreduce_smax_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_smax_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)
@@ -3778,13 +3778,13 @@ define i8 @vreduce_smax_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_smax_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v)
@@ -3798,13 +3798,13 @@ define i8 @vreduce_smax_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v)
@@ -3818,13 +3818,13 @@ define i8 @vreduce_smax_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> %v)
@@ -3841,10 +3841,10 @@ define i8 @vreduce_smax_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %v)
@@ -3864,10 +3864,10 @@ define i8 @vreduce_smax_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %v)
@@ -3880,8 +3880,8 @@ define i16 @vreduce_smax_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_smax_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v1i16(<1 x i16> %v)
@@ -3894,13 +3894,13 @@ define i16 @vreduce_smax_v2i16(<2 x i16>* %x) {
; CHECK-LABEL: vreduce_smax_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v)
@@ -3913,13 +3913,13 @@ define i16 @vreduce_smax_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_smax_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)
@@ -3932,13 +3932,13 @@ define i16 @vreduce_smax_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_smax_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v)
@@ -3951,13 +3951,13 @@ define i16 @vreduce_smax_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_smax_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v)
@@ -3971,13 +3971,13 @@ define i16 @vreduce_smax_v32i16(<32 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> %v)
@@ -3994,10 +3994,10 @@ define i16 @vreduce_smax_v64i16(<64 x i16>* %x) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> %v)
@@ -4017,10 +4017,10 @@ define i16 @vreduce_smax_v128i16(<128 x i16>* %x) {
; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %v)
@@ -4033,8 +4033,8 @@ define i32 @vreduce_smax_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_smax_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> %v)
@@ -4047,13 +4047,13 @@ define i32 @vreduce_smax_v2i32(<2 x i32>* %x) {
; CHECK-LABEL: vreduce_smax_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v)
@@ -4066,13 +4066,13 @@ define i32 @vreduce_smax_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_smax_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v)
@@ -4085,13 +4085,13 @@ define i32 @vreduce_smax_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_smax_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v)
@@ -4104,13 +4104,13 @@ define i32 @vreduce_smax_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_smax_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %v)
@@ -4127,10 +4127,10 @@ define i32 @vreduce_smax_v32i32(<32 x i32>* %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> %v)
@@ -4150,10 +4150,10 @@ define i32 @vreduce_smax_v64i32(<64 x i32>* %x) {
; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %v)
@@ -4166,18 +4166,18 @@ define i64 @vreduce_smax_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_smax_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smax_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> %v)
@@ -4192,34 +4192,34 @@ define i64 @vreduce_smax_v2i64(<2 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredmax.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smax_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: slli a0, a0, 63
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v26, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredmax.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %v)
@@ -4234,34 +4234,34 @@ define i64 @vreduce_smax_v4i64(<4 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredmax.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smax_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: slli a0, a0, 63
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredmax.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
@@ -4276,34 +4276,34 @@ define i64 @vreduce_smax_v8i64(<8 x i64>* %x) {
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredmax.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_smax_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: slli a0, a0, 63
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredmax.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %v)
@@ -4324,14 +4324,14 @@ define i64 @vreduce_smax_v16i64(<16 x i64>* %x) {
; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -4342,10 +4342,10 @@ define i64 @vreduce_smax_v16i64(<16 x i64>* %x) {
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: slli a0, a0, 63
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %v)
@@ -4369,14 +4369,14 @@ define i64 @vreduce_smax_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vmax.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -4390,10 +4390,10 @@ define i64 @vreduce_smax_v32i64(<32 x i64>* %x) {
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: slli a0, a0, 63
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %v)
@@ -4422,14 +4422,14 @@ define i64 @vreduce_smax_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vmax.vv v8, v8, v24
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -4449,10 +4449,10 @@ define i64 @vreduce_smax_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: addi a0, zero, -1
; RV64-NEXT: slli a0, a0, 63
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.smax.v64i64(<64 x i64> %v)
@@ -4465,8 +4465,8 @@ define i8 @vreduce_umin_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_umin_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v1i8(<1 x i8> %v)
@@ -4479,12 +4479,12 @@ define i8 @vreduce_umin_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_umin_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %v)
@@ -4497,12 +4497,12 @@ define i8 @vreduce_umin_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_umin_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %v)
@@ -4515,12 +4515,12 @@ define i8 @vreduce_umin_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_umin_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)
@@ -4533,12 +4533,12 @@ define i8 @vreduce_umin_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_umin_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v)
@@ -4552,12 +4552,12 @@ define i8 @vreduce_umin_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v)
@@ -4571,12 +4571,12 @@ define i8 @vreduce_umin_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> %v)
@@ -4592,10 +4592,10 @@ define i8 @vreduce_umin_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %v)
@@ -4614,10 +4614,10 @@ define i8 @vreduce_umin_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vminu.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %v)
@@ -4630,8 +4630,8 @@ define i16 @vreduce_umin_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_umin_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v1i16(<1 x i16> %v)
@@ -4644,12 +4644,12 @@ define i16 @vreduce_umin_v2i16(<2 x i16>* %x) {
; CHECK-LABEL: vreduce_umin_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %v)
@@ -4662,12 +4662,12 @@ define i16 @vreduce_umin_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_umin_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v)
@@ -4680,12 +4680,12 @@ define i16 @vreduce_umin_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_umin_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %v)
@@ -4698,12 +4698,12 @@ define i16 @vreduce_umin_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_umin_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v)
@@ -4717,12 +4717,12 @@ define i16 @vreduce_umin_v32i16(<32 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> %v)
@@ -4738,10 +4738,10 @@ define i16 @vreduce_umin_v64i16(<64 x i16>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> %v)
@@ -4760,10 +4760,10 @@ define i16 @vreduce_umin_v128i16(<128 x i16>* %x) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vminu.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %v)
@@ -4776,8 +4776,8 @@ define i32 @vreduce_umin_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_umin_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> %v)
@@ -4790,12 +4790,12 @@ define i32 @vreduce_umin_v2i32(<2 x i32>* %x) {
; CHECK-LABEL: vreduce_umin_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %v)
@@ -4808,12 +4808,12 @@ define i32 @vreduce_umin_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_umin_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v)
@@ -4826,12 +4826,12 @@ define i32 @vreduce_umin_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_umin_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v)
@@ -4844,12 +4844,12 @@ define i32 @vreduce_umin_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_umin_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %v)
@@ -4865,10 +4865,10 @@ define i32 @vreduce_umin_v32i32(<32 x i32>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> %v)
@@ -4887,10 +4887,10 @@ define i32 @vreduce_umin_v64i32(<64 x i32>* %x) {
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vminu.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %v)
@@ -4903,18 +4903,18 @@ define i64 @vreduce_umin_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_umin_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umin_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> %v)
@@ -4927,27 +4927,27 @@ define i64 @vreduce_umin_v2i64(<2 x i64>* %x) {
; RV32-LABEL: vreduce_umin_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, -1
+; RV32-NEXT: vmv.v.i v9, -1
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredminu.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umin_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, -1
+; RV64-NEXT: vmv.v.i v9, -1
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredminu.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %v)
@@ -4960,27 +4960,27 @@ define i64 @vreduce_umin_v4i64(<4 x i64>* %x) {
; RV32-LABEL: vreduce_umin_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v10, -1
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredminu.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umin_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v10, -1
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredminu.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
@@ -4993,27 +4993,27 @@ define i64 @vreduce_umin_v8i64(<8 x i64>* %x) {
; RV32-LABEL: vreduce_umin_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v12, -1
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredminu.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umin_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v12, -1
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredminu.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %v)
@@ -5028,14 +5028,14 @@ define i64 @vreduce_umin_v16i64(<16 x i64>* %x) {
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umin_v16i64:
@@ -5043,10 +5043,10 @@ define i64 @vreduce_umin_v16i64(<16 x i64>* %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v16, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> %v)
@@ -5064,14 +5064,14 @@ define i64 @vreduce_umin_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: vminu.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umin_v32i64:
@@ -5082,10 +5082,10 @@ define i64 @vreduce_umin_v32i64(<32 x i64>* %x) {
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vminu.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v16, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %v)
@@ -5109,14 +5109,14 @@ define i64 @vreduce_umin_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vminu.vv v8, v8, v0
; RV32-NEXT: vminu.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, -1
+; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umin_v64i64:
@@ -5133,10 +5133,10 @@ define i64 @vreduce_umin_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: vminu.vv v8, v8, v0
; RV64-NEXT: vminu.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, -1
+; RV64-NEXT: vmv.v.i v16, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.umin.v64i64(<64 x i64> %v)
@@ -5149,8 +5149,8 @@ define i8 @vreduce_umax_v1i8(<1 x i8>* %x) {
; CHECK-LABEL: vreduce_umax_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i8>, <1 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %v)
@@ -5163,12 +5163,12 @@ define i8 @vreduce_umax_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: vreduce_umax_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, <2 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %v)
@@ -5181,12 +5181,12 @@ define i8 @vreduce_umax_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_umax_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %v)
@@ -5199,12 +5199,12 @@ define i8 @vreduce_umax_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_umax_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v)
@@ -5217,12 +5217,12 @@ define i8 @vreduce_umax_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_umax_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %v)
@@ -5236,12 +5236,12 @@ define i8 @vreduce_umax_v32i8(<32 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %v)
@@ -5255,12 +5255,12 @@ define i8 @vreduce_umax_v64i8(<64 x i8>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> %v)
@@ -5276,10 +5276,10 @@ define i8 @vreduce_umax_v128i8(<128 x i8>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %v)
@@ -5298,10 +5298,10 @@ define i8 @vreduce_umax_v256i8(<256 x i8>* %x) {
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vmaxu.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %v)
@@ -5314,8 +5314,8 @@ define i16 @vreduce_umax_v1i16(<1 x i16>* %x) {
; CHECK-LABEL: vreduce_umax_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i16>, <1 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %v)
@@ -5328,12 +5328,12 @@ define i16 @vreduce_umax_v2i16(<2 x i16>* %x) {
; CHECK-LABEL: vreduce_umax_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, <2 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %v)
@@ -5346,12 +5346,12 @@ define i16 @vreduce_umax_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_umax_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v)
@@ -5364,12 +5364,12 @@ define i16 @vreduce_umax_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_umax_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %v)
@@ -5382,12 +5382,12 @@ define i16 @vreduce_umax_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_umax_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %v)
@@ -5401,12 +5401,12 @@ define i16 @vreduce_umax_v32i16(<32 x i16>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> %v)
@@ -5422,10 +5422,10 @@ define i16 @vreduce_umax_v64i16(<64 x i16>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> %v)
@@ -5444,10 +5444,10 @@ define i16 @vreduce_umax_v128i16(<128 x i16>* %x) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vmaxu.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %v)
@@ -5460,8 +5460,8 @@ define i32 @vreduce_umax_v1i32(<1 x i32>* %x) {
; CHECK-LABEL: vreduce_umax_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <1 x i32>, <1 x i32>* %x
%red = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %v)
@@ -5474,12 +5474,12 @@ define i32 @vreduce_umax_v2i32(<2 x i32>* %x) {
; CHECK-LABEL: vreduce_umax_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i32>, <2 x i32>* %x
%red = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %v)
@@ -5492,12 +5492,12 @@ define i32 @vreduce_umax_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_umax_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v25, v26
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v)
@@ -5510,12 +5510,12 @@ define i32 @vreduce_umax_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_umax_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v26, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v)
@@ -5528,12 +5528,12 @@ define i32 @vreduce_umax_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_umax_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v28, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %v)
@@ -5549,10 +5549,10 @@ define i32 @vreduce_umax_v32i32(<32 x i32>* %x) {
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> %v)
@@ -5571,10 +5571,10 @@ define i32 @vreduce_umax_v64i32(<64 x i32>* %x) {
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vmaxu.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v16
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %v)
@@ -5587,18 +5587,18 @@ define i64 @vreduce_umax_v1i64(<1 x i64>* %x) {
; RV32-LABEL: vreduce_umax_v1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, zero, 32
-; RV32-NEXT: vsrl.vx v26, v25, a0
-; RV32-NEXT: vmv.x.s a1, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vsrl.vx v9, v8, a0
+; RV32-NEXT: vmv.x.s a1, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umax_v1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <1 x i64>, <1 x i64>* %x
%red = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %v)
@@ -5611,27 +5611,27 @@ define i64 @vreduce_umax_v2i64(<2 x i64>* %x) {
; RV32-LABEL: vreduce_umax_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vle64.v v25, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vredmaxu.vs v25, v25, v26
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v8, v8, v9
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umax_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vle64.v v25, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vredmaxu.vs v25, v25, v26
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v8, v8, v9
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i64>, <2 x i64>* %x
%red = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %v)
@@ -5644,27 +5644,27 @@ define i64 @vreduce_umax_v4i64(<4 x i64>* %x) {
; RV32-LABEL: vreduce_umax_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vle64.v v26, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vredmaxu.vs v25, v26, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v8, v8, v10
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umax_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vle64.v v26, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vredmaxu.vs v25, v26, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v8, v8, v10
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)
@@ -5677,27 +5677,27 @@ define i64 @vreduce_umax_v8i64(<8 x i64>* %x) {
; RV32-LABEL: vreduce_umax_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle64.v v28, (a0)
+; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vredmaxu.vs v25, v28, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umax_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vle64.v v28, (a0)
+; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vredmaxu.vs v25, v28, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %v)
@@ -5712,14 +5712,14 @@ define i64 @vreduce_umax_v16i64(<16 x i64>* %x) {
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umax_v16i64:
@@ -5727,10 +5727,10 @@ define i64 @vreduce_umax_v16i64(<16 x i64>* %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %v)
@@ -5748,14 +5748,14 @@ define i64 @vreduce_umax_v32i64(<32 x i64>* %x) {
; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: vmaxu.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umax_v32i64:
@@ -5766,10 +5766,10 @@ define i64 @vreduce_umax_v32i64(<32 x i64>* %x) {
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vmaxu.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %v)
@@ -5793,14 +5793,14 @@ define i64 @vreduce_umax_v64i64(<64 x i64>* %x) nounwind {
; RV32-NEXT: vmaxu.vv v8, v8, v0
; RV32-NEXT: vmaxu.vv v8, v8, v16
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v8, v8, v16
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v8, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
;
; RV64-LABEL: vreduce_umax_v64i64:
@@ -5817,10 +5817,10 @@ define i64 @vreduce_umax_v64i64(<64 x i64>* %x) nounwind {
; RV64-NEXT: vmaxu.vv v8, v8, v0
; RV64-NEXT: vmaxu.vv v8, v8, v16
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v8, v8, v16
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.umax.v64i64(<64 x i64> %v)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
index 72fc3a1ab26ed..3bfc7e0112eff 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
@@ -10,9 +10,9 @@ define signext i1 @vpreduce_and_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i3
; CHECK-LABEL: vpreduce_and_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -26,10 +26,10 @@ declare i1 @llvm.vp.reduce.or.v1i1(i1, <1 x i1>, <1 x i1>, i32)
define signext i1 @vpreduce_or_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_v1i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -44,10 +44,10 @@ declare i1 @llvm.vp.reduce.xor.v1i1(i1, <1 x i1>, <1 x i1>, i32)
define signext i1 @vpreduce_xor_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_v1i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -62,9 +62,9 @@ define signext i1 @vpreduce_and_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i3
; CHECK-LABEL: vpreduce_and_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -78,10 +78,10 @@ declare i1 @llvm.vp.reduce.or.v2i1(i1, <2 x i1>, <2 x i1>, i32)
define signext i1 @vpreduce_or_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_v2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -96,10 +96,10 @@ declare i1 @llvm.vp.reduce.xor.v2i1(i1, <2 x i1>, <2 x i1>, i32)
define signext i1 @vpreduce_xor_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_v2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -114,9 +114,9 @@ define signext i1 @vpreduce_and_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i3
; CHECK-LABEL: vpreduce_and_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -130,10 +130,10 @@ declare i1 @llvm.vp.reduce.or.v4i1(i1, <4 x i1>, <4 x i1>, i32)
define signext i1 @vpreduce_or_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_v4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -148,10 +148,10 @@ declare i1 @llvm.vp.reduce.xor.v4i1(i1, <4 x i1>, <4 x i1>, i32)
define signext i1 @vpreduce_xor_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_v4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -166,9 +166,9 @@ define signext i1 @vpreduce_and_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i3
; CHECK-LABEL: vpreduce_and_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -182,10 +182,10 @@ declare i1 @llvm.vp.reduce.or.v8i1(i1, <8 x i1>, <8 x i1>, i32)
define signext i1 @vpreduce_or_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_v8i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -200,10 +200,10 @@ declare i1 @llvm.vp.reduce.xor.v8i1(i1, <8 x i1>, <8 x i1>, i32)
define signext i1 @vpreduce_xor_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_v8i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -218,9 +218,9 @@ define signext i1 @vpreduce_and_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m,
; CHECK-LABEL: vpreduce_and_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -234,10 +234,10 @@ declare i1 @llvm.vp.reduce.or.v16i1(i1, <16 x i1>, <16 x i1>, i32)
define signext i1 @vpreduce_or_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_v16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -252,10 +252,10 @@ declare i1 @llvm.vp.reduce.xor.v16i1(i1, <16 x i1>, <16 x i1>, i32)
define signext i1 @vpreduce_xor_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_v16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
index 7a3bdb4081313..2429473799a20 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
@@ -8,8 +8,8 @@ define <2 x half> @select_v2f16(i1 zeroext %c, <2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: select_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -22,8 +22,8 @@ define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -36,8 +36,8 @@ define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: select_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -50,8 +50,8 @@ define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -64,8 +64,8 @@ define <8 x half> @select_v8f16(i1 zeroext %c, <8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: select_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -78,8 +78,8 @@ define <8 x half> @selectcc_v8f16(half %a, half %b, <8 x half> %c, <8 x half> %d
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -92,8 +92,8 @@ define <16 x half> @select_v16f16(i1 zeroext %c, <16 x half> %a, <16 x half> %b)
; CHECK-LABEL: select_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -106,8 +106,8 @@ define <16 x half> @selectcc_v16f16(half %a, half %b, <16 x half> %c, <16 x half
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -120,8 +120,8 @@ define <2 x float> @select_v2f32(i1 zeroext %c, <2 x float> %a, <2 x float> %b)
; CHECK-LABEL: select_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -134,8 +134,8 @@ define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x floa
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -148,8 +148,8 @@ define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %a, <4 x float> %b)
; CHECK-LABEL: select_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -162,8 +162,8 @@ define <4 x float> @selectcc_v4f32(float %a, float %b, <4 x float> %c, <4 x floa
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -176,8 +176,8 @@ define <8 x float> @select_v8f32(i1 zeroext %c, <8 x float> %a, <8 x float> %b)
; CHECK-LABEL: select_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -190,8 +190,8 @@ define <8 x float> @selectcc_v8f32(float %a, float %b, <8 x float> %c, <8 x floa
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -204,8 +204,8 @@ define <16 x float> @select_v16f32(i1 zeroext %c, <16 x float> %a, <16 x float>
; CHECK-LABEL: select_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -218,8 +218,8 @@ define <16 x float> @selectcc_v16f32(float %a, float %b, <16 x float> %c, <16 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -232,8 +232,8 @@ define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %a, <2 x double> %
; CHECK-LABEL: select_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -246,8 +246,8 @@ define <2 x double> @selectcc_v2f64(double %a, double %b, <2 x double> %c, <2 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -260,8 +260,8 @@ define <4 x double> @select_v4f64(i1 zeroext %c, <4 x double> %a, <4 x double> %
; CHECK-LABEL: select_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -274,8 +274,8 @@ define <4 x double> @selectcc_v4f64(double %a, double %b, <4 x double> %c, <4 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -288,8 +288,8 @@ define <8 x double> @select_v8f64(i1 zeroext %c, <8 x double> %a, <8 x double> %
; CHECK-LABEL: select_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -302,8 +302,8 @@ define <8 x double> @selectcc_v8f64(double %a, double %b, <8 x double> %c, <8 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -316,8 +316,8 @@ define <16 x double> @select_v16f64(i1 zeroext %c, <16 x double> %a, <16 x doubl
; CHECK-LABEL: select_v16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -330,8 +330,8 @@ define <16 x double> @selectcc_v16f64(double %a, double %b, <16 x double> %c, <1
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
index 536091d1c1f63..e3f8eb3b8ef99 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
@@ -8,11 +8,11 @@ define <1 x i1> @select_v1i1(i1 zeroext %c, <1 x i1> %a, <1 x i1> %b) {
; CHECK-LABEL: select_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <1 x i1> %a, <1 x i1> %b
ret <1 x i1> %v
@@ -24,11 +24,11 @@ define <1 x i1> @selectcc_v1i1(i1 signext %a, i1 signext %b, <1 x i1> %c, <1 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <1 x i1> %c, <1 x i1> %d
@@ -39,11 +39,11 @@ define <2 x i1> @select_v2i1(i1 zeroext %c, <2 x i1> %a, <2 x i1> %b) {
; CHECK-LABEL: select_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <2 x i1> %a, <2 x i1> %b
ret <2 x i1> %v
@@ -55,11 +55,11 @@ define <2 x i1> @selectcc_v2i1(i1 signext %a, i1 signext %b, <2 x i1> %c, <2 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <2 x i1> %c, <2 x i1> %d
@@ -70,11 +70,11 @@ define <4 x i1> @select_v4i1(i1 zeroext %c, <4 x i1> %a, <4 x i1> %b) {
; CHECK-LABEL: select_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <4 x i1> %a, <4 x i1> %b
ret <4 x i1> %v
@@ -86,11 +86,11 @@ define <4 x i1> @selectcc_v4i1(i1 signext %a, i1 signext %b, <4 x i1> %c, <4 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <4 x i1> %c, <4 x i1> %d
@@ -101,11 +101,11 @@ define <8 x i1> @select_v8i1(i1 zeroext %c, <8 x i1> %a, <8 x i1> %b) {
; CHECK-LABEL: select_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <8 x i1> %a, <8 x i1> %b
ret <8 x i1> %v
@@ -117,11 +117,11 @@ define <8 x i1> @selectcc_v8i1(i1 signext %a, i1 signext %b, <8 x i1> %c, <8 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <8 x i1> %c, <8 x i1> %d
@@ -132,11 +132,11 @@ define <16 x i1> @select_v16i1(i1 zeroext %c, <16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: select_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <16 x i1> %a, <16 x i1> %b
ret <16 x i1> %v
@@ -148,11 +148,11 @@ define <16 x i1> @selectcc_v16i1(i1 signext %a, i1 signext %b, <16 x i1> %c, <16
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <16 x i1> %c, <16 x i1> %d
@@ -163,8 +163,8 @@ define <2 x i8> @select_v2i8(i1 zeroext %c, <2 x i8> %a, <2 x i8> %b) {
; CHECK-LABEL: select_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x i8> %a, <2 x i8> %b
@@ -177,8 +177,8 @@ define <2 x i8> @selectcc_v2i8(i8 signext %a, i8 signext %b, <2 x i8> %c, <2 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -190,8 +190,8 @@ define <4 x i8> @select_v4i8(i1 zeroext %c, <4 x i8> %a, <4 x i8> %b) {
; CHECK-LABEL: select_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x i8> %a, <4 x i8> %b
@@ -204,8 +204,8 @@ define <4 x i8> @selectcc_v4i8(i8 signext %a, i8 signext %b, <4 x i8> %c, <4 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -217,8 +217,8 @@ define <8 x i8> @select_v8i8(i1 zeroext %c, <8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: select_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x i8> %a, <8 x i8> %b
@@ -231,8 +231,8 @@ define <8 x i8> @selectcc_v8i8(i8 signext %a, i8 signext %b, <8 x i8> %c, <8 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -244,8 +244,8 @@ define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: select_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x i8> %a, <16 x i8> %b
@@ -258,8 +258,8 @@ define <16 x i8> @selectcc_v16i8(i8 signext %a, i8 signext %b, <16 x i8> %c, <16
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -271,8 +271,8 @@ define <2 x i16> @select_v2i16(i1 zeroext %c, <2 x i16> %a, <2 x i16> %b) {
; CHECK-LABEL: select_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -286,8 +286,8 @@ define <2 x i16> @selectcc_v2i16(i16 signext %a, i16 signext %b, <2 x i16> %c, <
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -300,8 +300,8 @@ define <4 x i16> @select_v4i16(i1 zeroext %c, <4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: select_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -315,8 +315,8 @@ define <4 x i16> @selectcc_v4i16(i16 signext %a, i16 signext %b, <4 x i16> %c, <
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -329,8 +329,8 @@ define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: select_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -344,8 +344,8 @@ define <8 x i16> @selectcc_v8i16(i16 signext %a, i16 signext %b, <8 x i16> %c, <
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -358,8 +358,8 @@ define <16 x i16> @select_v16i16(i1 zeroext %c, <16 x i16> %a, <16 x i16> %b) {
; CHECK-LABEL: select_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -373,8 +373,8 @@ define <16 x i16> @selectcc_v16i16(i16 signext %a, i16 signext %b, <16 x i16> %c
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -387,8 +387,8 @@ define <2 x i32> @select_v2i32(i1 zeroext %c, <2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: select_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -402,8 +402,8 @@ define <2 x i32> @selectcc_v2i32(i32 signext %a, i32 signext %b, <2 x i32> %c, <
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -416,8 +416,8 @@ define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: select_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -431,8 +431,8 @@ define <4 x i32> @selectcc_v4i32(i32 signext %a, i32 signext %b, <4 x i32> %c, <
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -445,8 +445,8 @@ define <8 x i32> @select_v8i32(i1 zeroext %c, <8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: select_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -460,8 +460,8 @@ define <8 x i32> @selectcc_v8i32(i32 signext %a, i32 signext %b, <8 x i32> %c, <
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -474,8 +474,8 @@ define <16 x i32> @select_v16i32(i1 zeroext %c, <16 x i32> %a, <16 x i32> %b) {
; CHECK-LABEL: select_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -489,8 +489,8 @@ define <16 x i32> @selectcc_v16i32(i32 signext %a, i32 signext %b, <16 x i32> %c
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -503,8 +503,8 @@ define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: select_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -520,8 +520,8 @@ define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, <
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: ret
@@ -531,8 +531,8 @@ define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, <
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v10, a0
+; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: ret
@@ -545,8 +545,8 @@ define <4 x i64> @select_v4i64(i1 zeroext %c, <4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: select_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -562,8 +562,8 @@ define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, <
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v12, a0
+; RV32-NEXT: vmsne.vi v0, v12, 0
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32-NEXT: vmerge.vvm v8, v10, v8, v0
; RV32-NEXT: ret
@@ -573,8 +573,8 @@ define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, <
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v12, a0
+; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
; RV64-NEXT: ret
@@ -587,8 +587,8 @@ define <8 x i64> @select_v8i64(i1 zeroext %c, <8 x i64> %a, <8 x i64> %b) {
; CHECK-LABEL: select_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -604,8 +604,8 @@ define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, <
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vmsne.vi v0, v16, 0
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vmerge.vvm v8, v12, v8, v0
; RV32-NEXT: ret
@@ -615,8 +615,8 @@ define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, <
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsne.vi v0, v16, 0
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64-NEXT: vmerge.vvm v8, v12, v8, v0
; RV64-NEXT: ret
@@ -629,8 +629,8 @@ define <16 x i64> @select_v16i64(i1 zeroext %c, <16 x i64> %a, <16 x i64> %b) {
; CHECK-LABEL: select_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -646,8 +646,8 @@ define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v24, a0
+; RV32-NEXT: vmsne.vi v0, v24, 0
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
; RV32-NEXT: ret
@@ -657,8 +657,8 @@ define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v24, a0
+; RV64-NEXT: vmsne.vi v0, v24, 0
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
index 741bd68bf855f..3ccc141033276 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
@@ -76,16 +76,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v25, v25, 1, v0
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 0
+; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmsne.vi v25, v26, 0
+; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vsm.v v25, (a0)
+; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: beqz a1, .LBB4_2
@@ -103,16 +103,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV32-NEXT: beqz a0, .LBB4_4
; RV32-NEXT: # %bb.3: # %cond.load1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v8, 1
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: lb a1, 1(a0)
; RV32-NEXT: lbu a0, 0(a0)
; RV32-NEXT: slli a1, a1, 8
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vmv.s.x v25, a0
+; RV32-NEXT: vmv.s.x v8, a0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, tu, mu
-; RV32-NEXT: vslideup.vi v9, v25, 1
+; RV32-NEXT: vslideup.vi v9, v8, 1
; RV32-NEXT: .LBB4_4: # %else2
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: addi sp, sp, 16
@@ -123,16 +123,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v25, v25, 1, v0
+; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v25, 0
+; RV64-NEXT: vslideup.vi v11, v10, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmsne.vi v25, v26, 0
+; RV64-NEXT: vmsne.vi v10, v11, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vsm.v v25, (a0)
+; RV64-NEXT: vsm.v v10, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: beqz a1, .LBB4_2
@@ -150,16 +150,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV64-NEXT: beqz a0, .LBB4_4
; RV64-NEXT: # %bb.3: # %cond.load1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v8, 1
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: lb a1, 1(a0)
; RV64-NEXT: lbu a0, 0(a0)
; RV64-NEXT: slli a1, a1, 8
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vmv.s.x v25, a0
+; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, tu, mu
-; RV64-NEXT: vslideup.vi v9, v25, 1
+; RV64-NEXT: vslideup.vi v9, v8, 1
; RV64-NEXT: .LBB4_4: # %else2
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: addi sp, sp, 16
@@ -176,43 +176,43 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64>
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v25, v25, 1, v0
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 0
+; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmsne.vi v25, v26, 0
+; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vsm.v v25, (a0)
+; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: beqz a1, .LBB5_2
; RV32-NEXT: # %bb.1: # %cond.load
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: vslide1up.vx v26, v25, a2
-; RV32-NEXT: vslide1up.vx v27, v26, a1
+; RV32-NEXT: vslide1up.vx v11, v10, a2
+; RV32-NEXT: vslide1up.vx v12, v11, a1
; RV32-NEXT: vsetivli zero, 1, e64, m1, tu, mu
-; RV32-NEXT: vslideup.vi v9, v27, 0
+; RV32-NEXT: vslideup.vi v9, v12, 0
; RV32-NEXT: .LBB5_2: # %else
; RV32-NEXT: andi a0, a0, 2
; RV32-NEXT: beqz a0, .LBB5_4
; RV32-NEXT: # %bb.3: # %cond.load1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; RV32-NEXT: vslidedown.vi v26, v8, 1
-; RV32-NEXT: vmv.x.s a0, v26
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: lw a1, 4(a0)
; RV32-NEXT: lw a0, 0(a0)
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; RV32-NEXT: vslide1up.vx v26, v25, a1
-; RV32-NEXT: vslide1up.vx v25, v26, a0
+; RV32-NEXT: vslide1up.vx v8, v10, a1
+; RV32-NEXT: vslide1up.vx v10, v8, a0
; RV32-NEXT: vsetivli zero, 2, e64, m1, tu, mu
-; RV32-NEXT: vslideup.vi v9, v25, 1
+; RV32-NEXT: vslideup.vi v9, v10, 1
; RV32-NEXT: .LBB5_4: # %else2
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: addi sp, sp, 16
@@ -223,16 +223,16 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64>
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v25, v25, 1, v0
+; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v25, 0
+; RV64-NEXT: vslideup.vi v11, v10, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmsne.vi v25, v26, 0
+; RV64-NEXT: vmsne.vi v10, v11, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vsm.v v25, (a0)
+; RV64-NEXT: vsm.v v10, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: beqz a1, .LBB5_2
@@ -250,16 +250,16 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64>
; RV64-NEXT: beqz a0, .LBB5_4
; RV64-NEXT: # %bb.3: # %cond.load1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v8, 1
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: lwu a1, 4(a0)
; RV64-NEXT: lwu a0, 0(a0)
; RV64-NEXT: slli a1, a1, 32
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vmv.s.x v25, a0
+; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; RV64-NEXT: vslideup.vi v9, v25, 1
+; RV64-NEXT: vslideup.vi v9, v8, 1
; RV64-NEXT: .LBB5_4: # %else2
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: addi sp, sp, 16
@@ -276,16 +276,16 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v25, v25, 1, v0
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 0
+; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmsne.vi v25, v26, 0
+; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vsm.v v25, (a0)
+; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: bnez a1, .LBB6_5
@@ -313,11 +313,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV32-NEXT: beqz a1, .LBB6_2
; RV32-NEXT: .LBB6_6: # %cond.store1
; RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v8, 1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vslidedown.vi v10, v8, 1
+; RV32-NEXT: vmv.x.s a1, v10
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v9, 1
-; RV32-NEXT: vmv.x.s a2, v25
+; RV32-NEXT: vslidedown.vi v10, v9, 1
+; RV32-NEXT: vmv.x.s a2, v10
; RV32-NEXT: sb a1, 0(a2)
; RV32-NEXT: srli a1, a1, 8
; RV32-NEXT: sb a1, 1(a2)
@@ -325,11 +325,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV32-NEXT: beqz a1, .LBB6_3
; RV32-NEXT: .LBB6_7: # %cond.store3
; RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v8, 2
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vslidedown.vi v10, v8, 2
+; RV32-NEXT: vmv.x.s a1, v10
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v9, 2
-; RV32-NEXT: vmv.x.s a2, v25
+; RV32-NEXT: vslidedown.vi v10, v9, 2
+; RV32-NEXT: vmv.x.s a2, v10
; RV32-NEXT: sb a1, 0(a2)
; RV32-NEXT: srli a1, a1, 8
; RV32-NEXT: sb a1, 1(a2)
@@ -337,11 +337,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV32-NEXT: beqz a0, .LBB6_4
; RV32-NEXT: .LBB6_8: # %cond.store5
; RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v8, 3
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vslidedown.vi v8, v8, 3
+; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v9, 3
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vslidedown.vi v8, v9, 3
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: sb a0, 0(a1)
; RV32-NEXT: srli a0, a0, 8
; RV32-NEXT: sb a0, 1(a1)
@@ -353,16 +353,16 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v25, v25, 1, v0
+; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v25, 0
+; RV64-NEXT: vslideup.vi v12, v9, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmsne.vi v25, v26, 0
+; RV64-NEXT: vmsne.vi v9, v12, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vsm.v v25, (a0)
+; RV64-NEXT: vsm.v v9, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: bnez a1, .LBB6_5
@@ -390,11 +390,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV64-NEXT: beqz a1, .LBB6_2
; RV64-NEXT: .LBB6_6: # %cond.store1
; RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v8, 1
-; RV64-NEXT: vmv.x.s a1, v25
+; RV64-NEXT: vslidedown.vi v9, v8, 1
+; RV64-NEXT: vmv.x.s a1, v9
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV64-NEXT: vslidedown.vi v26, v10, 1
-; RV64-NEXT: vmv.x.s a2, v26
+; RV64-NEXT: vslidedown.vi v12, v10, 1
+; RV64-NEXT: vmv.x.s a2, v12
; RV64-NEXT: sb a1, 0(a2)
; RV64-NEXT: srli a1, a1, 8
; RV64-NEXT: sb a1, 1(a2)
@@ -402,11 +402,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV64-NEXT: beqz a1, .LBB6_3
; RV64-NEXT: .LBB6_7: # %cond.store3
; RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v8, 2
-; RV64-NEXT: vmv.x.s a1, v25
+; RV64-NEXT: vslidedown.vi v9, v8, 2
+; RV64-NEXT: vmv.x.s a1, v9
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV64-NEXT: vslidedown.vi v26, v10, 2
-; RV64-NEXT: vmv.x.s a2, v26
+; RV64-NEXT: vslidedown.vi v12, v10, 2
+; RV64-NEXT: vmv.x.s a2, v12
; RV64-NEXT: sb a1, 0(a2)
; RV64-NEXT: srli a1, a1, 8
; RV64-NEXT: sb a1, 1(a2)
@@ -414,11 +414,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV64-NEXT: beqz a0, .LBB6_4
; RV64-NEXT: .LBB6_8: # %cond.store5
; RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v8, 3
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vslidedown.vi v8, v8, 3
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV64-NEXT: vslidedown.vi v26, v10, 3
-; RV64-NEXT: vmv.x.s a1, v26
+; RV64-NEXT: vslidedown.vi v8, v10, 3
+; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: sb a0, 0(a1)
; RV64-NEXT: srli a0, a0, 8
; RV64-NEXT: sb a0, 1(a1)
@@ -436,16 +436,16 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v25, v25, 1, v0
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 0
+; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmsne.vi v25, v26, 0
+; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vsm.v v25, (a0)
+; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: bnez a1, .LBB7_3
@@ -466,10 +466,10 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m
; RV32-NEXT: beqz a0, .LBB7_2
; RV32-NEXT: .LBB7_4: # %cond.store1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v8, 1
-; RV32-NEXT: vmv.x.s a0, v25
-; RV32-NEXT: vslidedown.vi v25, v9, 1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: vslidedown.vi v8, v9, 1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: sh a0, 0(a1)
; RV32-NEXT: srli a0, a0, 16
; RV32-NEXT: sh a0, 2(a1)
@@ -481,16 +481,16 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v25, v25, 1, v0
+; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v25, 0
+; RV64-NEXT: vslideup.vi v11, v10, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmsne.vi v25, v26, 0
+; RV64-NEXT: vmsne.vi v10, v11, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vsm.v v25, (a0)
+; RV64-NEXT: vsm.v v10, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: bnez a1, .LBB7_3
@@ -512,11 +512,11 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m
; RV64-NEXT: beqz a0, .LBB7_2
; RV64-NEXT: .LBB7_4: # %cond.store1
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v8, 1
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v9, 1
-; RV64-NEXT: vmv.x.s a1, v25
+; RV64-NEXT: vslidedown.vi v8, v9, 1
+; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: sh a0, 0(a1)
; RV64-NEXT: srli a0, a0, 16
; RV64-NEXT: sh a0, 2(a1)
@@ -535,16 +535,16 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmseq.vi v0, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v25, v25, 1, v0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 0
+; RV32-NEXT: vslideup.vi v9, v8, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmsne.vi v25, v26, 0
+; RV32-NEXT: vmsne.vi v8, v9, 0
; RV32-NEXT: addi a2, sp, 15
-; RV32-NEXT: vsm.v v25, (a2)
+; RV32-NEXT: vsm.v v8, (a2)
; RV32-NEXT: lbu a2, 15(sp)
; RV32-NEXT: andi a3, a2, 1
; RV32-NEXT: beqz a3, .LBB8_2
@@ -560,13 +560,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV32-NEXT: slli a3, a3, 16
; RV32-NEXT: or a3, a3, a4
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vmv.v.x v25, a3
+; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: andi a2, a2, 2
; RV32-NEXT: bnez a2, .LBB8_3
; RV32-NEXT: j .LBB8_4
; RV32-NEXT: .LBB8_2:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
+; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: andi a2, a2, 2
; RV32-NEXT: beqz a2, .LBB8_4
; RV32-NEXT: .LBB8_3: # %cond.load1
@@ -580,12 +580,12 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV32-NEXT: or a0, a3, a0
; RV32-NEXT: slli a0, a0, 16
; RV32-NEXT: or a0, a0, a2
-; RV32-NEXT: vmv.s.x v26, a0
+; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v25, v26, 1
+; RV32-NEXT: vslideup.vi v8, v9, 1
; RV32-NEXT: .LBB8_4: # %else2
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV32-NEXT: vse32.v v25, (a1)
+; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -595,16 +595,16 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmseq.vi v0, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v25, v25, 1, v0
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v25, 0
+; RV64-NEXT: vslideup.vi v9, v8, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmsne.vi v25, v26, 0
+; RV64-NEXT: vmsne.vi v8, v9, 0
; RV64-NEXT: addi a2, sp, 15
-; RV64-NEXT: vsm.v v25, (a2)
+; RV64-NEXT: vsm.v v8, (a2)
; RV64-NEXT: lbu a2, 15(sp)
; RV64-NEXT: andi a3, a2, 1
; RV64-NEXT: beqz a3, .LBB8_2
@@ -620,13 +620,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV64-NEXT: slli a3, a3, 16
; RV64-NEXT: or a3, a3, a4
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vmv.v.x v25, a3
+; RV64-NEXT: vmv.v.x v8, a3
; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: bnez a2, .LBB8_3
; RV64-NEXT: j .LBB8_4
; RV64-NEXT: .LBB8_2:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
+; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: beqz a2, .LBB8_4
; RV64-NEXT: .LBB8_3: # %cond.load1
@@ -640,12 +640,12 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV64-NEXT: or a0, a3, a0
; RV64-NEXT: slli a0, a0, 16
; RV64-NEXT: or a0, a0, a2
-; RV64-NEXT: vmv.s.x v26, a0
+; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v25, v26, 1
+; RV64-NEXT: vslideup.vi v8, v9, 1
; RV64-NEXT: .LBB8_4: # %else2
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vse32.v v25, (a1)
+; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
%mask = icmp eq <2 x i32> %m, zeroinitializer
@@ -663,16 +663,16 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32>
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmseq.vi v0, v9, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v25, v25, 1, v0
+; RV32-NEXT: vmv.v.i v9, 0
+; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.i v26, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV32-NEXT: vslideup.vi v26, v25, 0
+; RV32-NEXT: vslideup.vi v10, v9, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV32-NEXT: vmsne.vi v25, v26, 0
+; RV32-NEXT: vmsne.vi v9, v10, 0
; RV32-NEXT: addi a1, sp, 15
-; RV32-NEXT: vsm.v v25, (a1)
+; RV32-NEXT: vsm.v v9, (a1)
; RV32-NEXT: lbu a1, 15(sp)
; RV32-NEXT: andi a2, a1, 1
; RV32-NEXT: bnez a2, .LBB9_3
@@ -692,8 +692,8 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32>
; RV32-NEXT: beqz a1, .LBB9_2
; RV32-NEXT: .LBB9_4: # %cond.store1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; RV32-NEXT: vslidedown.vi v25, v8, 1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: sh a1, 4(a0)
; RV32-NEXT: srli a1, a1, 16
; RV32-NEXT: sh a1, 6(a0)
@@ -706,16 +706,16 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32>
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmseq.vi v0, v9, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v25, v25, 1, v0
+; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.i v26, 0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
-; RV64-NEXT: vslideup.vi v26, v25, 0
+; RV64-NEXT: vslideup.vi v10, v9, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; RV64-NEXT: vmsne.vi v25, v26, 0
+; RV64-NEXT: vmsne.vi v9, v10, 0
; RV64-NEXT: addi a1, sp, 15
-; RV64-NEXT: vsm.v v25, (a1)
+; RV64-NEXT: vsm.v v9, (a1)
; RV64-NEXT: lbu a1, 15(sp)
; RV64-NEXT: andi a2, a1, 1
; RV64-NEXT: bnez a2, .LBB9_3
@@ -735,8 +735,8 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32>
; RV64-NEXT: beqz a1, .LBB9_2
; RV64-NEXT: .LBB9_4: # %cond.store1
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v8, 1
-; RV64-NEXT: vmv.x.s a1, v25
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: sh a1, 4(a0)
; RV64-NEXT: srli a1, a1, 16
; RV64-NEXT: sh a1, 6(a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
index b7fb68b14ffcc..03349765c7b94 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
@@ -403,23 +403,23 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-NEXT: vlm.v v26, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: addi a3, a1, -128
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: bltu a1, a3, .LBB31_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a3
; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB31_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: addi a1, zero, 128
; CHECK-NEXT: .LBB31_4:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <256 x i8> undef, i8 -1, i32 0
@@ -462,10 +462,10 @@ define <256 x i8> @vadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <256 x i8> undef, i8 -1, i32 0
@@ -1130,9 +1130,9 @@ define <2 x i64> @vadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v25, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1156,9 +1156,9 @@ define <2 x i64> @vadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v25
+; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1234,9 +1234,9 @@ define <4 x i64> @vadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v26, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1260,9 +1260,9 @@ define <4 x i64> @vadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v26
+; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1338,9 +1338,9 @@ define <8 x i64> @vadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v28, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1364,9 +1364,9 @@ define <8 x i64> @vadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v28
+; RV32-NEXT: vadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1546,7 +1546,7 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
;
; RV64-LABEL: vadd_vx_v32i64:
; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v25, v0
+; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: mv a1, zero
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64-NEXT: addi a2, a0, -16
@@ -1563,7 +1563,7 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: addi a0, zero, 16
; RV64-NEXT: .LBB107_4:
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; RV64-NEXT: vmv1r.v v0, v25
+; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t
; RV64-NEXT: ret
%elt.head = insertelement <32 x i64> undef, i64 -1, i32 0
@@ -1662,11 +1662,11 @@ define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; RV64-LABEL: vadd_vx_v32i64_evl27:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
-; RV64-NEXT: vslidedown.vi v25, v0, 2
+; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t
; RV64-NEXT: vsetivli zero, 11, e64, m8, ta, mu
-; RV64-NEXT: vmv1r.v v0, v25
+; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
; RV64-NEXT: ret
%elt.head = insertelement <32 x i64> undef, i64 -1, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
index dbb2df83e1ec4..3180f0445d4c1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
@@ -961,9 +961,9 @@ define <2 x i64> @vand_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v25, v0.t
+; RV32-NEXT: vand.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -987,9 +987,9 @@ define <2 x i64> @vand_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v25
+; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1065,9 +1065,9 @@ define <4 x i64> @vand_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v26, v0.t
+; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1091,9 +1091,9 @@ define <4 x i64> @vand_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v26
+; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1169,9 +1169,9 @@ define <8 x i64> @vand_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v28, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1195,9 +1195,9 @@ define <8 x i64> @vand_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v28
+; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1267,19 +1267,19 @@ define <11 x i64> @vand_vv_v11i64_unmasked(<11 x i64> %va, <11 x i64> %b, i32 ze
define <11 x i64> @vand_vx_v11i64(<11 x i64> %va, i64 %b, <11 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v11i64:
; RV32: # %bb.0:
-; RV32-NEXT: vmv1r.v v25, v0
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: addi a3, zero, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, mu
-; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 341
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, mu
-; RV32-NEXT: vmerge.vxm v16, v16, a0, v0
+; RV32-NEXT: vmerge.vxm v24, v24, a0, v0
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; RV32-NEXT: vmv1r.v v0, v25
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vand_vx_v11i64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
index 45293124e5dd3..b7dac4e289044 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
@@ -10,12 +10,12 @@ define <8 x i7> @vdiv_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK-LABEL: vdiv_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v25, v9, v9
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vadd.vv v26, v8, v8
-; CHECK-NEXT: vsra.vi v26, v26, 1
+; CHECK-NEXT: vadd.vv v9, v9, v9
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vdiv.vv v8, v26, v25, v0.t
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -666,9 +666,9 @@ define <2 x i64> @vdiv_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v25, v0.t
+; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -692,9 +692,9 @@ define <2 x i64> @vdiv_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v25
+; RV32-NEXT: vdiv.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -744,9 +744,9 @@ define <4 x i64> @vdiv_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v26, v0.t
+; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -770,9 +770,9 @@ define <4 x i64> @vdiv_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v26
+; RV32-NEXT: vdiv.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -822,9 +822,9 @@ define <8 x i64> @vdiv_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v28, v0.t
+; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -848,9 +848,9 @@ define <8 x i64> @vdiv_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v28
+; RV32-NEXT: vdiv.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
index 1f83ba3e5043d..537583143cedf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
@@ -11,10 +11,10 @@ define <8 x i7> @vdivu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vx v25, v9, a1
-; CHECK-NEXT: vand.vx v26, v8, a1
+; CHECK-NEXT: vand.vx v9, v9, a1
+; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vdivu.vv v8, v26, v25, v0.t
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.udiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -665,9 +665,9 @@ define <2 x i64> @vdivu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v25, v0.t
+; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -691,9 +691,9 @@ define <2 x i64> @vdivu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v25
+; RV32-NEXT: vdivu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -743,9 +743,9 @@ define <4 x i64> @vdivu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v26, v0.t
+; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -769,9 +769,9 @@ define <4 x i64> @vdivu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v26
+; RV32-NEXT: vdivu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -821,9 +821,9 @@ define <8 x i64> @vdivu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v28, v0.t
+; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -847,9 +847,9 @@ define <8 x i64> @vdivu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v28
+; RV32-NEXT: vdivu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
index 9302940d29ba5..95e7d0702cf98 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
@@ -32,9 +32,9 @@ define <2 x half> @vfadd_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero
; CHECK-LABEL: vfadd_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -96,9 +96,9 @@ define <4 x half> @vfadd_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero
; CHECK-LABEL: vfadd_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -148,9 +148,9 @@ define <8 x half> @vfadd_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero
; CHECK-LABEL: vfadd_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -200,9 +200,9 @@ define <16 x half> @vfadd_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32
; CHECK-LABEL: vfadd_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -252,9 +252,9 @@ define <2 x float> @vfadd_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z
; CHECK-LABEL: vfadd_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -304,9 +304,9 @@ define <4 x float> @vfadd_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z
; CHECK-LABEL: vfadd_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <8 x float> @vfadd_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z
; CHECK-LABEL: vfadd_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -408,9 +408,9 @@ define <16 x float> @vfadd_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i
; CHECK-LABEL: vfadd_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -460,9 +460,9 @@ define <2 x double> @vfadd_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3
; CHECK-LABEL: vfadd_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -512,9 +512,9 @@ define <4 x double> @vfadd_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3
; CHECK-LABEL: vfadd_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -564,9 +564,9 @@ define <8 x double> @vfadd_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3
; CHECK-LABEL: vfadd_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
index aa4ab8dba3a27..355c4e99bf08d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
@@ -32,9 +32,9 @@ define <2 x half> @vfdiv_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero
; CHECK-LABEL: vfdiv_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -96,9 +96,9 @@ define <4 x half> @vfdiv_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero
; CHECK-LABEL: vfdiv_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -148,9 +148,9 @@ define <8 x half> @vfdiv_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero
; CHECK-LABEL: vfdiv_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -200,9 +200,9 @@ define <16 x half> @vfdiv_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32
; CHECK-LABEL: vfdiv_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -252,9 +252,9 @@ define <2 x float> @vfdiv_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z
; CHECK-LABEL: vfdiv_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -304,9 +304,9 @@ define <4 x float> @vfdiv_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z
; CHECK-LABEL: vfdiv_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <8 x float> @vfdiv_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z
; CHECK-LABEL: vfdiv_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -408,9 +408,9 @@ define <16 x float> @vfdiv_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i
; CHECK-LABEL: vfdiv_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -460,9 +460,9 @@ define <2 x double> @vfdiv_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3
; CHECK-LABEL: vfdiv_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -512,9 +512,9 @@ define <4 x double> @vfdiv_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3
; CHECK-LABEL: vfdiv_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -564,9 +564,9 @@ define <8 x double> @vfdiv_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3
; CHECK-LABEL: vfdiv_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
index 885a16510dbb5..e8ff802066591 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
@@ -32,9 +32,9 @@ define <2 x half> @vfmul_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero
; CHECK-LABEL: vfmul_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -96,9 +96,9 @@ define <4 x half> @vfmul_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero
; CHECK-LABEL: vfmul_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -148,9 +148,9 @@ define <8 x half> @vfmul_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero
; CHECK-LABEL: vfmul_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -200,9 +200,9 @@ define <16 x half> @vfmul_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32
; CHECK-LABEL: vfmul_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -252,9 +252,9 @@ define <2 x float> @vfmul_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z
; CHECK-LABEL: vfmul_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -304,9 +304,9 @@ define <4 x float> @vfmul_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z
; CHECK-LABEL: vfmul_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <8 x float> @vfmul_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z
; CHECK-LABEL: vfmul_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -408,9 +408,9 @@ define <16 x float> @vfmul_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i
; CHECK-LABEL: vfmul_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -460,9 +460,9 @@ define <2 x double> @vfmul_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3
; CHECK-LABEL: vfmul_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -512,9 +512,9 @@ define <4 x double> @vfmul_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3
; CHECK-LABEL: vfmul_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -564,9 +564,9 @@ define <8 x double> @vfmul_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3
; CHECK-LABEL: vfmul_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
index 5745e03fc23e1..19e9eca8d7823 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
@@ -10,9 +10,9 @@ define <2 x half> @vfrdiv_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zer
; CHECK-LABEL: vfrdiv_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -40,9 +40,9 @@ define <4 x half> @vfrdiv_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zer
; CHECK-LABEL: vfrdiv_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -70,9 +70,9 @@ define <8 x half> @vfrdiv_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
; CHECK-LABEL: vfrdiv_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -100,9 +100,9 @@ define <16 x half> @vfrdiv_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32
; CHECK-LABEL: vfrdiv_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -130,9 +130,9 @@ define <2 x float> @vfrdiv_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32
; CHECK-LABEL: vfrdiv_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -160,9 +160,9 @@ define <4 x float> @vfrdiv_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32
; CHECK-LABEL: vfrdiv_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -190,9 +190,9 @@ define <8 x float> @vfrdiv_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32
; CHECK-LABEL: vfrdiv_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -220,9 +220,9 @@ define <16 x float> @vfrdiv_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m,
; CHECK-LABEL: vfrdiv_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -250,9 +250,9 @@ define <2 x double> @vfrdiv_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i
; CHECK-LABEL: vfrdiv_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -280,9 +280,9 @@ define <4 x double> @vfrdiv_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i
; CHECK-LABEL: vfrdiv_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -310,9 +310,9 @@ define <8 x double> @vfrdiv_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i
; CHECK-LABEL: vfrdiv_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
index 8762766192a71..b379b5a622e70 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
@@ -10,9 +10,9 @@ define <2 x half> @vfrsub_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zer
; CHECK-LABEL: vfrsub_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -40,9 +40,9 @@ define <4 x half> @vfrsub_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zer
; CHECK-LABEL: vfrsub_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -70,9 +70,9 @@ define <8 x half> @vfrsub_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
; CHECK-LABEL: vfrsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -100,9 +100,9 @@ define <16 x half> @vfrsub_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32
; CHECK-LABEL: vfrsub_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -130,9 +130,9 @@ define <2 x float> @vfrsub_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32
; CHECK-LABEL: vfrsub_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -160,9 +160,9 @@ define <4 x float> @vfrsub_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32
; CHECK-LABEL: vfrsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -190,9 +190,9 @@ define <8 x float> @vfrsub_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32
; CHECK-LABEL: vfrsub_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -220,9 +220,9 @@ define <16 x float> @vfrsub_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m,
; CHECK-LABEL: vfrsub_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -250,9 +250,9 @@ define <2 x double> @vfrsub_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i
; CHECK-LABEL: vfrsub_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -280,9 +280,9 @@ define <4 x double> @vfrsub_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i
; CHECK-LABEL: vfrsub_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -310,9 +310,9 @@ define <8 x double> @vfrsub_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i
; CHECK-LABEL: vfrsub_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
index e4158640a459c..b557e29fe1127 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
@@ -32,9 +32,9 @@ define <2 x half> @vfsub_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero
; CHECK-LABEL: vfsub_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x half> undef, half %b, i32 0
%vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer
@@ -96,9 +96,9 @@ define <4 x half> @vfsub_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero
; CHECK-LABEL: vfsub_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x half> undef, half %b, i32 0
%vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer
@@ -148,9 +148,9 @@ define <8 x half> @vfsub_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero
; CHECK-LABEL: vfsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> undef, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer
@@ -200,9 +200,9 @@ define <16 x half> @vfsub_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32
; CHECK-LABEL: vfsub_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x half> undef, half %b, i32 0
%vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer
@@ -252,9 +252,9 @@ define <2 x float> @vfsub_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z
; CHECK-LABEL: vfsub_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> undef, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer
@@ -304,9 +304,9 @@ define <4 x float> @vfsub_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z
; CHECK-LABEL: vfsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x float> undef, float %b, i32 0
%vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <8 x float> @vfsub_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z
; CHECK-LABEL: vfsub_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x float> undef, float %b, i32 0
%vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer
@@ -408,9 +408,9 @@ define <16 x float> @vfsub_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i
; CHECK-LABEL: vfsub_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <16 x float> undef, float %b, i32 0
%vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer
@@ -460,9 +460,9 @@ define <2 x double> @vfsub_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3
; CHECK-LABEL: vfsub_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x double> undef, double %b, i32 0
%vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer
@@ -512,9 +512,9 @@ define <4 x double> @vfsub_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3
; CHECK-LABEL: vfsub_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x double> undef, double %b, i32 0
%vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer
@@ -564,9 +564,9 @@ define <8 x double> @vfsub_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3
; CHECK-LABEL: vfsub_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> undef, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
index 41f03d22a7be3..6907f6ae61688 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
@@ -699,9 +699,9 @@ define <2 x i64> @vmul_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v25, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -725,9 +725,9 @@ define <2 x i64> @vmul_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v25
+; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -777,9 +777,9 @@ define <4 x i64> @vmul_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v26, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -803,9 +803,9 @@ define <4 x i64> @vmul_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v26
+; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -855,9 +855,9 @@ define <8 x i64> @vmul_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v28, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -881,9 +881,9 @@ define <8 x i64> @vmul_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v28
+; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
index e3877ce088ada..f623f11a56e20 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
@@ -1037,9 +1037,9 @@ define <2 x i64> @vor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v25, v0.t
+; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1063,9 +1063,9 @@ define <2 x i64> @vor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v25
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1141,9 +1141,9 @@ define <4 x i64> @vor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v26, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1167,9 +1167,9 @@ define <4 x i64> @vor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v26
+; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1245,9 +1245,9 @@ define <8 x i64> @vor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v28, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1271,9 +1271,9 @@ define <8 x i64> @vor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v28
+; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
index d19f2aa1e3d8d..f9a12282f4230 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
@@ -10,15 +10,15 @@ define <2 x i8> @vpgather_v2i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v
@@ -28,17 +28,17 @@ define <2 x i16> @vpgather_v2i8_sextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, i32
; RV32-LABEL: vpgather_v2i8_sextload_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vsext.vf2 v8, v25
+; RV32-NEXT: vsext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8_sextload_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vsext.vf2 v8, v25
+; RV64-NEXT: vsext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = sext <2 x i8> %v to <2 x i16>
@@ -49,17 +49,17 @@ define <2 x i16> @vpgather_v2i8_zextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, i32
; RV32-LABEL: vpgather_v2i8_zextload_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vzext.vf2 v8, v25
+; RV32-NEXT: vzext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8_zextload_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vzext.vf2 v8, v25
+; RV64-NEXT: vzext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = zext <2 x i8> %v to <2 x i16>
@@ -70,17 +70,17 @@ define <2 x i32> @vpgather_v2i8_sextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, i32
; RV32-LABEL: vpgather_v2i8_sextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vsext.vf4 v8, v25
+; RV32-NEXT: vsext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8_sextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vsext.vf4 v8, v25
+; RV64-NEXT: vsext.vf4 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = sext <2 x i8> %v to <2 x i32>
@@ -91,17 +91,17 @@ define <2 x i32> @vpgather_v2i8_zextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, i32
; RV32-LABEL: vpgather_v2i8_zextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vzext.vf4 v8, v25
+; RV32-NEXT: vzext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8_zextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vzext.vf4 v8, v25
+; RV64-NEXT: vzext.vf4 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = zext <2 x i8> %v to <2 x i32>
@@ -112,17 +112,17 @@ define <2 x i64> @vpgather_v2i8_sextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, i32
; RV32-LABEL: vpgather_v2i8_sextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vsext.vf8 v8, v25
+; RV32-NEXT: vsext.vf8 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8_sextload_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vsext.vf8 v8, v25
+; RV64-NEXT: vsext.vf8 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = sext <2 x i8> %v to <2 x i64>
@@ -133,17 +133,17 @@ define <2 x i64> @vpgather_v2i8_zextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, i32
; RV32-LABEL: vpgather_v2i8_zextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vzext.vf8 v8, v25
+; RV32-NEXT: vzext.vf8 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i8_zextload_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vzext.vf8 v8, v25
+; RV64-NEXT: vzext.vf8 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = zext <2 x i8> %v to <2 x i64>
@@ -156,15 +156,15 @@ define <4 x i8> @vpgather_v4i8(<4 x i8*> %ptrs, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_v4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <4 x i8> @llvm.vp.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v
@@ -174,15 +174,15 @@ define <4 x i8> @vpgather_truemask_v4i8(<4 x i8*> %ptrs, i32 zeroext %evl) {
; RV32-LABEL: vpgather_truemask_v4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -196,15 +196,15 @@ define <8 x i8> @vpgather_v8i8(<8 x i8*> %ptrs, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v8i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%v = call <8 x i8> @llvm.vp.gather.v8i8.v8p0i8(<8 x i8*> %ptrs, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v
@@ -214,17 +214,17 @@ define <8 x i8> @vpgather_baseidx_v8i8(i8* %base, <8 x i8> %idxs, <8 x i1> %m, i
; RV32-LABEL: vpgather_baseidx_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
+; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
+; RV64-NEXT: vsext.vf8 v12, v8
; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs
%v = call <8 x i8> @llvm.vp.gather.v8i8.v8p0i8(<8 x i8*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -237,15 +237,15 @@ define <2 x i16> @vpgather_v2i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v
@@ -255,17 +255,17 @@ define <2 x i32> @vpgather_v2i16_sextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, i
; RV32-LABEL: vpgather_v2i16_sextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vsext.vf2 v8, v25
+; RV32-NEXT: vsext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i16_sextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vsext.vf2 v8, v25
+; RV64-NEXT: vsext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = sext <2 x i16> %v to <2 x i32>
@@ -276,17 +276,17 @@ define <2 x i32> @vpgather_v2i16_zextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, i
; RV32-LABEL: vpgather_v2i16_zextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vzext.vf2 v8, v25
+; RV32-NEXT: vzext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i16_zextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vzext.vf2 v8, v25
+; RV64-NEXT: vzext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = zext <2 x i16> %v to <2 x i32>
@@ -297,17 +297,17 @@ define <2 x i64> @vpgather_v2i16_sextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, i
; RV32-LABEL: vpgather_v2i16_sextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vsext.vf4 v8, v25
+; RV32-NEXT: vsext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i16_sextload_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vsext.vf4 v8, v25
+; RV64-NEXT: vsext.vf4 v8, v9
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = sext <2 x i16> %v to <2 x i64>
@@ -318,17 +318,17 @@ define <2 x i64> @vpgather_v2i16_zextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, i
; RV32-LABEL: vpgather_v2i16_zextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vzext.vf4 v8, v25
+; RV32-NEXT: vzext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i16_zextload_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vzext.vf4 v8, v25
+; RV64-NEXT: vzext.vf4 v8, v9
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = zext <2 x i16> %v to <2 x i64>
@@ -341,15 +341,15 @@ define <4 x i16> @vpgather_v4i16(<4 x i16*> %ptrs, <4 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <4 x i16> @llvm.vp.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v
@@ -359,15 +359,15 @@ define <4 x i16> @vpgather_truemask_v4i16(<4 x i16*> %ptrs, i32 zeroext %evl) {
; RV32-LABEL: vpgather_truemask_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -381,15 +381,15 @@ define <8 x i16> @vpgather_v8i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v
@@ -399,19 +399,19 @@ define <8 x i16> @vpgather_baseidx_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 x i
; RV32-LABEL: vpgather_baseidx_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs
%v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -422,19 +422,19 @@ define <8 x i16> @vpgather_baseidx_sext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <
; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
@@ -446,19 +446,19 @@ define <8 x i16> @vpgather_baseidx_zext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <
; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
@@ -470,19 +470,19 @@ define <8 x i16> @vpgather_baseidx_v8i16(i16* %base, <8 x i16> %idxs, <8 x i1> %
; RV32-LABEL: vpgather_baseidx_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs
%v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -501,8 +501,8 @@ define <2 x i32> @vpgather_v2i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vpgather_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v
@@ -512,17 +512,17 @@ define <2 x i64> @vpgather_v2i32_sextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, i
; RV32-LABEL: vpgather_v2i32_sextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vsext.vf2 v8, v25
+; RV32-NEXT: vsext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i32_sextload_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vsext.vf2 v8, v25
+; RV64-NEXT: vsext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = sext <2 x i32> %v to <2 x i64>
@@ -533,17 +533,17 @@ define <2 x i64> @vpgather_v2i32_zextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, i
; RV32-LABEL: vpgather_v2i32_zextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vzext.vf2 v8, v25
+; RV32-NEXT: vzext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i32_zextload_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV64-NEXT: vzext.vf2 v8, v25
+; RV64-NEXT: vzext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 %evl)
%ev = zext <2 x i32> %v to <2 x i64>
@@ -562,8 +562,8 @@ define <4 x i32> @vpgather_v4i32(<4 x i32*> %ptrs, <4 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vpgather_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v
@@ -579,8 +579,8 @@ define <4 x i32> @vpgather_truemask_v4i32(<4 x i32*> %ptrs, i32 zeroext %evl) {
; RV64-LABEL: vpgather_truemask_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -600,8 +600,8 @@ define <8 x i32> @vpgather_v8i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vpgather_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v
@@ -611,19 +611,19 @@ define <8 x i32> @vpgather_baseidx_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8 x i
; RV32-LABEL: vpgather_baseidx_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs
%v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -634,19 +634,19 @@ define <8 x i32> @vpgather_baseidx_sext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <
; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -658,19 +658,19 @@ define <8 x i32> @vpgather_baseidx_zext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <
; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -682,19 +682,19 @@ define <8 x i32> @vpgather_baseidx_v8i16_v8i32(i32* %base, <8 x i16> %idxs, <8 x
; RV32-LABEL: vpgather_baseidx_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs
%v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -705,19 +705,19 @@ define <8 x i32> @vpgather_baseidx_sext_v8i16_v8i32(i32* %base, <8 x i16> %idxs,
; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -729,19 +729,19 @@ define <8 x i32> @vpgather_baseidx_zext_v8i16_v8i32(i32* %base, <8 x i16> %idxs,
; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -753,18 +753,18 @@ define <8 x i32> @vpgather_baseidx_v8i32(i32* %base, <8 x i32> %idxs, <8 x i1> %
; RV32-LABEL: vpgather_baseidx_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 2
+; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs
%v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -777,8 +777,8 @@ define <2 x i64> @vpgather_v2i64(<2 x i64*> %ptrs, <2 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2i64:
@@ -796,8 +796,8 @@ define <4 x i64> @vpgather_v4i64(<4 x i64*> %ptrs, <4 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4i64:
@@ -813,8 +813,8 @@ define <4 x i64> @vpgather_truemask_v4i64(<4 x i64*> %ptrs, i32 zeroext %evl) {
; RV32-LABEL: vpgather_truemask_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4i64:
@@ -834,8 +834,8 @@ define <8 x i64> @vpgather_v8i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vpgather_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8, v0.t
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v8i64:
@@ -851,19 +851,19 @@ define <8 x i64> @vpgather_baseidx_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i
; RV32-LABEL: vpgather_baseidx_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v12, v10, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs
%v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -874,10 +874,10 @@ define <8 x i64> @vpgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <
; CHECK-LABEL: vpgather_baseidx_sext_v8i8_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf8 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -889,10 +889,10 @@ define <8 x i64> @vpgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <
; CHECK-LABEL: vpgather_baseidx_zext_v8i8_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf8 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -904,19 +904,19 @@ define <8 x i64> @vpgather_baseidx_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x
; RV32-LABEL: vpgather_baseidx_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v12, v10, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs
%v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -927,10 +927,10 @@ define <8 x i64> @vpgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs,
; CHECK-LABEL: vpgather_baseidx_sext_v8i16_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -942,10 +942,10 @@ define <8 x i64> @vpgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs,
; CHECK-LABEL: vpgather_baseidx_zext_v8i16_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -957,18 +957,18 @@ define <8 x i64> @vpgather_baseidx_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x
; RV32-LABEL: vpgather_baseidx_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 3
+; RV32-NEXT: vsll.vi v12, v8, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs
%v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -979,10 +979,10 @@ define <8 x i64> @vpgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs,
; CHECK-LABEL: vpgather_baseidx_sext_v8i32_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -994,10 +994,10 @@ define <8 x i64> @vpgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs,
; CHECK-LABEL: vpgather_baseidx_zext_v8i32_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -1009,9 +1009,9 @@ define <8 x i64> @vpgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %
; CHECK-LABEL: vpgather_baseidx_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsll.vi v28, v8, 3
+; CHECK-NEXT: vsll.vi v8, v8, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs
%v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1024,15 +1024,15 @@ define <2 x half> @vpgather_v2f16(<2 x half*> %ptrs, <2 x i1> %m, i32 zeroext %e
; RV32-LABEL: vpgather_v2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <2 x half> @llvm.vp.gather.v2f16.v2p0f16(<2 x half*> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x half> %v
@@ -1044,15 +1044,15 @@ define <4 x half> @vpgather_v4f16(<4 x half*> %ptrs, <4 x i1> %m, i32 zeroext %e
; RV32-LABEL: vpgather_v4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <4 x half> @llvm.vp.gather.v4f16.v4p0f16(<4 x half*> %ptrs, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -1062,15 +1062,15 @@ define <4 x half> @vpgather_truemask_v4f16(<4 x half*> %ptrs, i32 zeroext %evl)
; RV32-LABEL: vpgather_truemask_v4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -1084,15 +1084,15 @@ define <8 x half> @vpgather_v8f16(<8 x half*> %ptrs, <8 x i1> %m, i32 zeroext %e
; RV32-LABEL: vpgather_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%v = call <8 x half> @llvm.vp.gather.v8f16.v8p0f16(<8 x half*> %ptrs, <8 x i1> %m, i32 %evl)
ret <8 x half> %v
@@ -1102,19 +1102,19 @@ define <8 x half> @vpgather_baseidx_v8i8_v8f16(half* %base, <8 x i8> %idxs, <8 x
; RV32-LABEL: vpgather_baseidx_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs
%v = call <8 x half> @llvm.vp.gather.v8f16.v8p0f16(<8 x half*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1125,19 +1125,19 @@ define <8 x half> @vpgather_baseidx_sext_v8i8_v8f16(half* %base, <8 x i8> %idxs,
; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
@@ -1149,19 +1149,19 @@ define <8 x half> @vpgather_baseidx_zext_v8i8_v8f16(half* %base, <8 x i8> %idxs,
; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
@@ -1173,19 +1173,19 @@ define <8 x half> @vpgather_baseidx_v8f16(half* %base, <8 x i16> %idxs, <8 x i1>
; RV32-LABEL: vpgather_baseidx_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs
%v = call <8 x half> @llvm.vp.gather.v8f16.v8p0f16(<8 x half*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1204,8 +1204,8 @@ define <2 x float> @vpgather_v2f32(<2 x float*> %ptrs, <2 x i1> %m, i32 zeroext
; RV64-LABEL: vpgather_v2f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <2 x float> @llvm.vp.gather.v2f32.v2p0f32(<2 x float*> %ptrs, <2 x i1> %m, i32 %evl)
ret <2 x float> %v
@@ -1223,8 +1223,8 @@ define <4 x float> @vpgather_v4f32(<4 x float*> %ptrs, <4 x i1> %m, i32 zeroext
; RV64-LABEL: vpgather_v4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <4 x float> @llvm.vp.gather.v4f32.v4p0f32(<4 x float*> %ptrs, <4 x i1> %m, i32 %evl)
ret <4 x float> %v
@@ -1240,8 +1240,8 @@ define <4 x float> @vpgather_truemask_v4f32(<4 x float*> %ptrs, i32 zeroext %evl
; RV64-LABEL: vpgather_truemask_v4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%mhead = insertelement <4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -1261,8 +1261,8 @@ define <8 x float> @vpgather_v8f32(<8 x float*> %ptrs, <8 x i1> %m, i32 zeroext
; RV64-LABEL: vpgather_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl)
ret <8 x float> %v
@@ -1272,19 +1272,19 @@ define <8 x float> @vpgather_baseidx_v8i8_v8f32(float* %base, <8 x i8> %idxs, <8
; RV32-LABEL: vpgather_baseidx_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs
%v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1295,19 +1295,19 @@ define <8 x float> @vpgather_baseidx_sext_v8i8_v8f32(float* %base, <8 x i8> %idx
; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1319,19 +1319,19 @@ define <8 x float> @vpgather_baseidx_zext_v8i8_v8f32(float* %base, <8 x i8> %idx
; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1343,19 +1343,19 @@ define <8 x float> @vpgather_baseidx_v8i16_v8f32(float* %base, <8 x i16> %idxs,
; RV32-LABEL: vpgather_baseidx_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs
%v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1366,19 +1366,19 @@ define <8 x float> @vpgather_baseidx_sext_v8i16_v8f32(float* %base, <8 x i16> %i
; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1390,19 +1390,19 @@ define <8 x float> @vpgather_baseidx_zext_v8i16_v8f32(float* %base, <8 x i16> %i
; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v8, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1414,18 +1414,18 @@ define <8 x float> @vpgather_baseidx_v8f32(float* %base, <8 x i32> %idxs, <8 x i
; RV32-LABEL: vpgather_baseidx_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 2
+; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs
%v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1438,8 +1438,8 @@ define <2 x double> @vpgather_v2f64(<2 x double*> %ptrs, <2 x i1> %m, i32 zeroex
; RV32-LABEL: vpgather_v2f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v2f64:
@@ -1457,8 +1457,8 @@ define <4 x double> @vpgather_v4f64(<4 x double*> %ptrs, <4 x i1> %m, i32 zeroex
; RV32-LABEL: vpgather_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v4f64:
@@ -1474,8 +1474,8 @@ define <4 x double> @vpgather_truemask_v4f64(<4 x double*> %ptrs, i32 zeroext %e
; RV32-LABEL: vpgather_truemask_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_v4f64:
@@ -1495,8 +1495,8 @@ define <8 x double> @vpgather_v8f64(<8 x double*> %ptrs, <8 x i1> %m, i32 zeroex
; RV32-LABEL: vpgather_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8, v0.t
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_v8f64:
@@ -1512,19 +1512,19 @@ define <8 x double> @vpgather_baseidx_v8i8_v8f64(double* %base, <8 x i8> %idxs,
; RV32-LABEL: vpgather_baseidx_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v10, v8
+; RV32-NEXT: vsll.vi v12, v10, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf8 v12, v8
+; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs
%v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1535,10 +1535,10 @@ define <8 x double> @vpgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %i
; CHECK-LABEL: vpgather_baseidx_sext_v8i8_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf8 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1550,10 +1550,10 @@ define <8 x double> @vpgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %i
; CHECK-LABEL: vpgather_baseidx_zext_v8i8_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf8 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1565,19 +1565,19 @@ define <8 x double> @vpgather_baseidx_v8i16_v8f64(double* %base, <8 x i16> %idxs
; RV32-LABEL: vpgather_baseidx_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v8
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vsll.vi v12, v10, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf4 v12, v8
+; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs
%v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1588,10 +1588,10 @@ define <8 x double> @vpgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16>
; CHECK-LABEL: vpgather_baseidx_sext_v8i16_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1603,10 +1603,10 @@ define <8 x double> @vpgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16>
; CHECK-LABEL: vpgather_baseidx_zext_v8i16_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1618,18 +1618,18 @@ define <8 x double> @vpgather_baseidx_v8i32_v8f64(double* %base, <8 x i32> %idxs
; RV32-LABEL: vpgather_baseidx_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v8, 3
+; RV32-NEXT: vsll.vi v12, v8, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v8
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf2 v12, v8
+; RV64-NEXT: vsll.vi v8, v12, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs
%v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1640,10 +1640,10 @@ define <8 x double> @vpgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32>
; CHECK-LABEL: vpgather_baseidx_sext_v8i32_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1655,10 +1655,10 @@ define <8 x double> @vpgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32>
; CHECK-LABEL: vpgather_baseidx_zext_v8i32_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1670,9 +1670,9 @@ define <8 x double> @vpgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x
; CHECK-LABEL: vpgather_baseidx_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsll.vi v28, v8, 3
+; CHECK-NEXT: vsll.vi v8, v8, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t
; CHECK-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs
%v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
index 1a4ffa0fb62ef..52887d7a88d57 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
@@ -26,17 +26,17 @@ define void @vpscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2
; RV32-LABEL: vpscatter_v2i16_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_v2i16_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i16> %val to <2 x i8>
call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
@@ -47,21 +47,21 @@ define void @vpscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2
; RV32-LABEL: vpscatter_v2i32_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_v2i32_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i8>
call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
@@ -72,25 +72,25 @@ define void @vpscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2
; RV32-LABEL: vpscatter_v2i64_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_v2i64_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i8>
call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl)
@@ -155,17 +155,17 @@ define void @vpscatter_baseidx_v8i8(<8 x i8> %val, i8* %base, <8 x i8> %idxs, <8
; RV32-LABEL: vpscatter_baseidx_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
+; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
+; RV64-NEXT: vsext.vf8 v12, v9
; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs
call void @llvm.vp.scatter.v8i8.v8p0i8(<8 x i8> %val, <8 x i8*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -194,17 +194,17 @@ define void @vpscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs,
; RV32-LABEL: vpscatter_v2i32_truncstore_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_v2i32_truncstore_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i16>
call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
@@ -215,21 +215,21 @@ define void @vpscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs,
; RV32-LABEL: vpscatter_v2i64_truncstore_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_v2i64_truncstore_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i16>
call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl)
@@ -294,19 +294,19 @@ define void @vpscatter_baseidx_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i8> %
; RV32-LABEL: vpscatter_baseidx_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs
call void @llvm.vp.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -317,19 +317,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
@@ -341,19 +341,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
@@ -365,19 +365,19 @@ define void @vpscatter_baseidx_v8i16(<8 x i16> %val, i16* %base, <8 x i16> %idxs
; RV32-LABEL: vpscatter_baseidx_v8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs
call void @llvm.vp.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -406,17 +406,17 @@ define void @vpscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs,
; RV32-LABEL: vpscatter_v2i64_truncstore_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_v2i64_truncstore_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i32>
call void @llvm.vp.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, <2 x i1> %m, i32 %evl)
@@ -481,19 +481,19 @@ define void @vpscatter_baseidx_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i8> %
; RV32-LABEL: vpscatter_baseidx_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs
call void @llvm.vp.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -504,19 +504,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -528,19 +528,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -552,19 +552,19 @@ define void @vpscatter_baseidx_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x i16>
; RV32-LABEL: vpscatter_baseidx_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs
call void @llvm.vp.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -575,19 +575,19 @@ define void @vpscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -599,19 +599,19 @@ define void @vpscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs
@@ -623,18 +623,18 @@ define void @vpscatter_baseidx_v8i32(<8 x i32> %val, i32* %base, <8 x i32> %idxs
; RV32-LABEL: vpscatter_baseidx_v8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v10, 2
+; RV32-NEXT: vsll.vi v10, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs
call void @llvm.vp.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -717,19 +717,19 @@ define void @vpscatter_baseidx_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %
; RV32-LABEL: vpscatter_baseidx_v8i8_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i8_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs
call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -740,10 +740,10 @@ define void @vpscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x
; CHECK-LABEL: vpscatter_baseidx_sext_v8i8_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf8 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -755,10 +755,10 @@ define void @vpscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x
; CHECK-LABEL: vpscatter_baseidx_zext_v8i8_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf8 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -770,19 +770,19 @@ define void @vpscatter_baseidx_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16>
; RV32-LABEL: vpscatter_baseidx_v8i16_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i16_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs
call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -793,10 +793,10 @@ define void @vpscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x
; CHECK-LABEL: vpscatter_baseidx_sext_v8i16_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf4 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -808,10 +808,10 @@ define void @vpscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x
; CHECK-LABEL: vpscatter_baseidx_zext_v8i16_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf4 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -823,18 +823,18 @@ define void @vpscatter_baseidx_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32>
; RV32-LABEL: vpscatter_baseidx_v8i32_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v12, 3
+; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i32_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs
call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -845,10 +845,10 @@ define void @vpscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x
; CHECK-LABEL: vpscatter_baseidx_sext_v8i32_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf2 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -860,10 +860,10 @@ define void @vpscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x
; CHECK-LABEL: vpscatter_baseidx_zext_v8i32_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf2 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs
@@ -875,9 +875,9 @@ define void @vpscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs
; CHECK-LABEL: vpscatter_baseidx_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsll.vi v28, v12, 3
+; CHECK-NEXT: vsll.vi v12, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs
call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -960,19 +960,19 @@ define void @vpscatter_baseidx_v8i8_v8f16(<8 x half> %val, half* %base, <8 x i8>
; RV32-LABEL: vpscatter_baseidx_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs
call void @llvm.vp.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -983,19 +983,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, half* %base, <8
; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
@@ -1007,19 +1007,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, half* %base, <8
; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vzext.vf4 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vzext.vf8 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
@@ -1031,19 +1031,19 @@ define void @vpscatter_baseidx_v8f16(<8 x half> %val, half* %base, <8 x i16> %id
; RV32-LABEL: vpscatter_baseidx_v8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v9
-; RV32-NEXT: vadd.vv v26, v26, v26
+; RV32-NEXT: vsext.vf2 v10, v9
+; RV32-NEXT: vadd.vv v10, v10, v10
; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v9
-; RV64-NEXT: vadd.vv v28, v28, v28
+; RV64-NEXT: vsext.vf4 v12, v9
+; RV64-NEXT: vadd.vv v12, v12, v12
; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs
call void @llvm.vp.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1126,19 +1126,19 @@ define void @vpscatter_baseidx_v8i8_v8f32(<8 x float> %val, float* %base, <8 x i
; RV32-LABEL: vpscatter_baseidx_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs
call void @llvm.vp.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1149,19 +1149,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, float* %base, <
; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1173,19 +1173,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, float* %base, <
; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf8 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf8 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1197,19 +1197,19 @@ define void @vpscatter_baseidx_v8i16_v8f32(<8 x float> %val, float* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs
call void @llvm.vp.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1220,19 +1220,19 @@ define void @vpscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, float* %base,
; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1244,19 +1244,19 @@ define void @vpscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, float* %base,
; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v10
-; RV32-NEXT: vsll.vi v26, v26, 2
+; RV32-NEXT: vzext.vf2 v12, v10
+; RV32-NEXT: vsll.vi v10, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vzext.vf4 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vzext.vf4 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs
@@ -1268,18 +1268,18 @@ define void @vpscatter_baseidx_v8f32(<8 x float> %val, float* %base, <8 x i32> %
; RV32-LABEL: vpscatter_baseidx_v8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v10, 2
+; RV32-NEXT: vsll.vi v10, v10, 2
; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v10
-; RV64-NEXT: vsll.vi v28, v28, 2
+; RV64-NEXT: vsext.vf2 v12, v10
+; RV64-NEXT: vsll.vi v12, v12, 2
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs
call void @llvm.vp.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1362,19 +1362,19 @@ define void @vpscatter_baseidx_v8i8_v8f64(<8 x double> %val, double* %base, <8 x
; RV32-LABEL: vpscatter_baseidx_v8i8_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf4 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i8_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf8 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf8 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs
call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1385,10 +1385,10 @@ define void @vpscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base,
; CHECK-LABEL: vpscatter_baseidx_sext_v8i8_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf8 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1400,10 +1400,10 @@ define void @vpscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base,
; CHECK-LABEL: vpscatter_baseidx_zext_v8i8_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf8 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1415,19 +1415,19 @@ define void @vpscatter_baseidx_v8i16_v8f64(<8 x double> %val, double* %base, <8
; RV32-LABEL: vpscatter_baseidx_v8i16_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v12
-; RV32-NEXT: vsll.vi v26, v26, 3
+; RV32-NEXT: vsext.vf2 v14, v12
+; RV32-NEXT: vsll.vi v12, v14, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i16_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf4 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf4 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs
call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1438,10 +1438,10 @@ define void @vpscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base
; CHECK-LABEL: vpscatter_baseidx_sext_v8i16_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf4 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1453,10 +1453,10 @@ define void @vpscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base
; CHECK-LABEL: vpscatter_baseidx_zext_v8i16_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf4 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1468,18 +1468,18 @@ define void @vpscatter_baseidx_v8i32_v8f64(<8 x double> %val, double* %base, <8
; RV32-LABEL: vpscatter_baseidx_v8i32_v8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32-NEXT: vsll.vi v26, v12, 3
+; RV32-NEXT: vsll.vi v12, v12, 3
; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_v8i32_v8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vsext.vf2 v28, v12
-; RV64-NEXT: vsll.vi v28, v28, 3
+; RV64-NEXT: vsext.vf2 v16, v12
+; RV64-NEXT: vsll.vi v12, v16, 3
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs
call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
@@ -1490,10 +1490,10 @@ define void @vpscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base
; CHECK-LABEL: vpscatter_baseidx_sext_v8i32_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vsext.vf2 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1505,10 +1505,10 @@ define void @vpscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base
; CHECK-LABEL: vpscatter_baseidx_zext_v8i32_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v12
-; CHECK-NEXT: vsll.vi v28, v28, 3
+; CHECK-NEXT: vzext.vf2 v16, v12
+; CHECK-NEXT: vsll.vi v12, v16, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs
@@ -1520,9 +1520,9 @@ define void @vpscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64>
; CHECK-LABEL: vpscatter_baseidx_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vsll.vi v28, v12, 3
+; CHECK-NEXT: vsll.vi v12, v12, 3
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
%ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs
call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
index 531f257fc84ed..37f63f474e415 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
@@ -10,9 +10,9 @@ define signext i1 @vreduce_or_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_or_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -26,9 +26,9 @@ define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_xor_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -42,9 +42,9 @@ define signext i1 @vreduce_and_v1i1(<1 x i1> %v) {
; CHECK-LABEL: vreduce_and_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -86,8 +86,8 @@ define signext i1 @vreduce_and_v2i1(<2 x i1> %v) {
; CHECK-LABEL: vreduce_and_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -129,8 +129,8 @@ define signext i1 @vreduce_and_v4i1(<4 x i1> %v) {
; CHECK-LABEL: vreduce_and_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -172,8 +172,8 @@ define signext i1 @vreduce_and_v8i1(<8 x i1> %v) {
; CHECK-LABEL: vreduce_and_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -215,8 +215,8 @@ define signext i1 @vreduce_and_v16i1(<16 x i1> %v) {
; CHECK-LABEL: vreduce_and_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -230,8 +230,8 @@ define signext i1 @vreduce_or_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_or_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmor.mm v25, v0, v8
-; LMULMAX1-NEXT: vpopc.m a0, v25
+; LMULMAX1-NEXT: vmor.mm v8, v0, v8
+; LMULMAX1-NEXT: vpopc.m a0, v8
; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret
@@ -254,8 +254,8 @@ define signext i1 @vreduce_xor_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_xor_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmxor.mm v25, v0, v8
-; LMULMAX1-NEXT: vpopc.m a0, v25
+; LMULMAX1-NEXT: vmxor.mm v8, v0, v8
+; LMULMAX1-NEXT: vpopc.m a0, v8
; LMULMAX1-NEXT: andi a0, a0, 1
; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret
@@ -278,8 +278,8 @@ define signext i1 @vreduce_and_v32i1(<32 x i1> %v) {
; LMULMAX1-LABEL: vreduce_and_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmnand.mm v25, v0, v8
-; LMULMAX1-NEXT: vpopc.m a0, v25
+; LMULMAX1-NEXT: vmnand.mm v8, v0, v8
+; LMULMAX1-NEXT: vpopc.m a0, v8
; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret
@@ -288,8 +288,8 @@ define signext i1 @vreduce_and_v32i1(<32 x i1> %v) {
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a0, zero, 32
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; LMULMAX8-NEXT: vmnand.mm v25, v0, v0
-; LMULMAX8-NEXT: vpopc.m a0, v25
+; LMULMAX8-NEXT: vmnand.mm v8, v0, v0
+; LMULMAX8-NEXT: vpopc.m a0, v8
; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: neg a0, a0
; LMULMAX8-NEXT: ret
@@ -303,10 +303,10 @@ define signext i1 @vreduce_or_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_or_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmor.mm v25, v8, v10
-; LMULMAX1-NEXT: vmor.mm v26, v0, v9
-; LMULMAX1-NEXT: vmor.mm v25, v26, v25
-; LMULMAX1-NEXT: vpopc.m a0, v25
+; LMULMAX1-NEXT: vmor.mm v8, v8, v10
+; LMULMAX1-NEXT: vmor.mm v9, v0, v9
+; LMULMAX1-NEXT: vmor.mm v8, v9, v8
+; LMULMAX1-NEXT: vpopc.m a0, v8
; LMULMAX1-NEXT: snez a0, a0
; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret
@@ -329,10 +329,10 @@ define signext i1 @vreduce_xor_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_xor_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmxor.mm v25, v8, v10
-; LMULMAX1-NEXT: vmxor.mm v26, v0, v9
-; LMULMAX1-NEXT: vmxor.mm v25, v26, v25
-; LMULMAX1-NEXT: vpopc.m a0, v25
+; LMULMAX1-NEXT: vmxor.mm v8, v8, v10
+; LMULMAX1-NEXT: vmxor.mm v9, v0, v9
+; LMULMAX1-NEXT: vmxor.mm v8, v9, v8
+; LMULMAX1-NEXT: vpopc.m a0, v8
; LMULMAX1-NEXT: andi a0, a0, 1
; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret
@@ -355,10 +355,10 @@ define signext i1 @vreduce_and_v64i1(<64 x i1> %v) {
; LMULMAX1-LABEL: vreduce_and_v64i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vmand.mm v25, v8, v10
-; LMULMAX1-NEXT: vmand.mm v26, v0, v9
-; LMULMAX1-NEXT: vmnand.mm v25, v26, v25
-; LMULMAX1-NEXT: vpopc.m a0, v25
+; LMULMAX1-NEXT: vmand.mm v8, v8, v10
+; LMULMAX1-NEXT: vmand.mm v9, v0, v9
+; LMULMAX1-NEXT: vmnand.mm v8, v9, v8
+; LMULMAX1-NEXT: vpopc.m a0, v8
; LMULMAX1-NEXT: seqz a0, a0
; LMULMAX1-NEXT: neg a0, a0
; LMULMAX1-NEXT: ret
@@ -367,8 +367,8 @@ define signext i1 @vreduce_and_v64i1(<64 x i1> %v) {
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a0, zero, 64
; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; LMULMAX8-NEXT: vmnand.mm v25, v0, v0
-; LMULMAX8-NEXT: vpopc.m a0, v25
+; LMULMAX8-NEXT: vmnand.mm v8, v0, v0
+; LMULMAX8-NEXT: vpopc.m a0, v8
; LMULMAX8-NEXT: seqz a0, a0
; LMULMAX8-NEXT: neg a0, a0
; LMULMAX8-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
index d791ca37bb460..9d58cb6bc49a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
@@ -10,12 +10,12 @@ define <8 x i7> @vrem_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK-LABEL: vrem_vv_v8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v25, v9, v9
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vadd.vv v26, v8, v8
-; CHECK-NEXT: vsra.vi v26, v26, 1
+; CHECK-NEXT: vadd.vv v9, v9, v9
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrem.vv v8, v26, v25, v0.t
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.srem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -666,9 +666,9 @@ define <2 x i64> @vrem_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v25, v0.t
+; RV32-NEXT: vrem.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -692,9 +692,9 @@ define <2 x i64> @vrem_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v25
+; RV32-NEXT: vrem.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -744,9 +744,9 @@ define <4 x i64> @vrem_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v26, v0.t
+; RV32-NEXT: vrem.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -770,9 +770,9 @@ define <4 x i64> @vrem_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v26
+; RV32-NEXT: vrem.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -822,9 +822,9 @@ define <8 x i64> @vrem_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v28, v0.t
+; RV32-NEXT: vrem.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -848,9 +848,9 @@ define <8 x i64> @vrem_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v28
+; RV32-NEXT: vrem.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
index 09e11d9868e91..64dadf0769fbc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
@@ -11,10 +11,10 @@ define <8 x i7> @vremu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vx v25, v9, a1
-; CHECK-NEXT: vand.vx v26, v8, a1
+; CHECK-NEXT: vand.vx v9, v9, a1
+; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vremu.vv v8, v26, v25, v0.t
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.urem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
@@ -665,9 +665,9 @@ define <2 x i64> @vremu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v25, v0.t
+; RV32-NEXT: vremu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -691,9 +691,9 @@ define <2 x i64> @vremu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v25
+; RV32-NEXT: vremu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -743,9 +743,9 @@ define <4 x i64> @vremu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v26, v0.t
+; RV32-NEXT: vremu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -769,9 +769,9 @@ define <4 x i64> @vremu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v26
+; RV32-NEXT: vremu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -821,9 +821,9 @@ define <8 x i64> @vremu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v28, v0.t
+; RV32-NEXT: vremu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -847,9 +847,9 @@ define <8 x i64> @vremu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v28
+; RV32-NEXT: vremu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
index 2affa084c7954..3bb9b61b949e3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
@@ -663,9 +663,9 @@ define <2 x i64> @vrsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v25, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -689,9 +689,9 @@ define <2 x i64> @vrsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v25, v8
+; RV32-NEXT: vsub.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -745,9 +745,9 @@ define <4 x i64> @vrsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v26, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v10, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -771,9 +771,9 @@ define <4 x i64> @vrsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v26, v8
+; RV32-NEXT: vsub.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -827,9 +827,9 @@ define <8 x i64> @vrsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v28, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v12, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -853,9 +853,9 @@ define <8 x i64> @vrsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v28, v8
+; RV32-NEXT: vsub.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
index 0d96d40dd34d9..293a94ff1e422 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
@@ -457,8 +457,8 @@ define <2 x i64> @sadd_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -506,8 +506,8 @@ define <4 x i64> @sadd_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -555,8 +555,8 @@ define <8 x i64> @sadd_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
index 9a698279e779f..057687fc41a52 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
@@ -457,8 +457,8 @@ define <2 x i64> @uadd_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -506,8 +506,8 @@ define <4 x i64> @uadd_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -555,8 +555,8 @@ define <8 x i64> @uadd_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
index e6ae1cee619c9..9845a485caa9d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
@@ -6,11 +6,11 @@ define void @vselect_vv_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x
; CHECK-LABEL: vselect_vv_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
-; CHECK-NEXT: vse32.v v26, (a3)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
+; CHECK-NEXT: vse32.v v8, (a3)
; CHECK-NEXT: ret
%va = load <8 x i32>, <8 x i32>* %a
%vb = load <8 x i32>, <8 x i32>* %b
@@ -25,9 +25,9 @@ define void @vselect_vx_v8i32(i32 %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0
-; CHECK-NEXT: vse32.v v26, (a3)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: vse32.v v8, (a3)
; CHECK-NEXT: ret
%vb = load <8 x i32>, <8 x i32>* %b
%ahead = insertelement <8 x i32> undef, i32 %a, i32 0
@@ -43,9 +43,9 @@ define void @vselect_vi_v8i32(<8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmerge.vim v26, v26, -1, v0
-; CHECK-NEXT: vse32.v v26, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%vb = load <8 x i32>, <8 x i32>* %b
%a = insertelement <8 x i32> undef, i32 -1, i32 0
@@ -60,11 +60,11 @@ define void @vselect_vv_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i1>* %cc, <
; CHECK-LABEL: vselect_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
-; CHECK-NEXT: vse32.v v26, (a3)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
+; CHECK-NEXT: vse32.v v8, (a3)
; CHECK-NEXT: ret
%va = load <8 x float>, <8 x float>* %a
%vb = load <8 x float>, <8 x float>* %b
@@ -79,9 +79,9 @@ define void @vselect_vx_v8f32(float %a, <8 x float>* %b, <8 x i1>* %cc, <8 x flo
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vfmerge.vfm v26, v26, fa0, v0
-; CHECK-NEXT: vse32.v v26, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%vb = load <8 x float>, <8 x float>* %b
%ahead = insertelement <8 x float> undef, float %a, i32 0
@@ -97,9 +97,9 @@ define void @vselect_vfpzero_v8f32(<8 x float>* %b, <8 x i1>* %cc, <8 x float>*
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vmerge.vim v26, v26, 0, v0
-; CHECK-NEXT: vse32.v v26, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
%vb = load <8 x float>, <8 x float>* %b
%a = insertelement <8 x float> undef, float 0.0, i32 0
@@ -114,11 +114,11 @@ define void @vselect_vv_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i1>* %cc, <
; CHECK-LABEL: vselect_vv_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
-; CHECK-NEXT: vse16.v v26, (a3)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
+; CHECK-NEXT: vse16.v v8, (a3)
; CHECK-NEXT: ret
%va = load <16 x i16>, <16 x i16>* %a
%vb = load <16 x i16>, <16 x i16>* %b
@@ -133,9 +133,9 @@ define void @vselect_vx_v16i16(i16 signext %a, <16 x i16>* %b, <16 x i1>* %cc, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0
-; CHECK-NEXT: vse16.v v26, (a3)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: vse16.v v8, (a3)
; CHECK-NEXT: ret
%vb = load <16 x i16>, <16 x i16>* %b
%ahead = insertelement <16 x i16> undef, i16 %a, i32 0
@@ -151,9 +151,9 @@ define void @vselect_vi_v16i16(<16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vmerge.vim v26, v26, 4, v0
-; CHECK-NEXT: vse16.v v26, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmerge.vim v8, v8, 4, v0
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%vb = load <16 x i16>, <16 x i16>* %b
%a = insertelement <16 x i16> undef, i16 4, i32 0
@@ -169,11 +169,11 @@ define void @vselect_vv_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x i1>* %cc,
; CHECK: # %bb.0:
; CHECK-NEXT: addi a4, zero, 32
; CHECK-NEXT: vsetvli zero, a4, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: vmerge.vvm v28, v8, v28, v0
-; CHECK-NEXT: vse16.v v28, (a3)
+; CHECK-NEXT: vle16.v v12, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
+; CHECK-NEXT: vse16.v v8, (a3)
; CHECK-NEXT: ret
%va = load <32 x half>, <32 x half>* %a
%vb = load <32 x half>, <32 x half>* %b
@@ -189,9 +189,9 @@ define void @vselect_vx_v32f16(half %a, <32 x half>* %b, <32 x i1>* %cc, <32 x h
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vfmerge.vfm v28, v28, fa0, v0
-; CHECK-NEXT: vse16.v v28, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%vb = load <32 x half>, <32 x half>* %b
%ahead = insertelement <32 x half> undef, half %a, i32 0
@@ -208,9 +208,9 @@ define void @vselect_vfpzero_v32f16(<32 x half>* %b, <32 x i1>* %cc, <32 x half>
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vmerge.vim v28, v28, 0, v0
-; CHECK-NEXT: vse16.v v28, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
%vb = load <32 x half>, <32 x half>* %b
%a = insertelement <32 x half> undef, half 0.0, i32 0
@@ -225,9 +225,9 @@ define <2 x i1> @vselect_v2i1(<2 x i1> %a, <2 x i1> %b, <2 x i1> %cc) {
; CHECK-LABEL: vselect_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <2 x i1> %cc, <2 x i1> %a, <2 x i1> %b
ret <2 x i1> %v
@@ -237,9 +237,9 @@ define <4 x i1> @vselect_v4i1(<4 x i1> %a, <4 x i1> %b, <4 x i1> %cc) {
; CHECK-LABEL: vselect_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <4 x i1> %cc, <4 x i1> %a, <4 x i1> %b
ret <4 x i1> %v
@@ -249,9 +249,9 @@ define <8 x i1> @vselect_v8i1(<8 x i1> %a, <8 x i1> %b, <8 x i1> %cc) {
; CHECK-LABEL: vselect_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <8 x i1> %cc, <8 x i1> %a, <8 x i1> %b
ret <8 x i1> %v
@@ -261,9 +261,9 @@ define <16 x i1> @vselect_v16i1(<16 x i1> %a, <16 x i1> %b, <16 x i1> %cc) {
; CHECK-LABEL: vselect_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <16 x i1> %cc, <16 x i1> %a, <16 x i1> %b
ret <16 x i1> %v
@@ -274,9 +274,9 @@ define <32 x i1> @vselect_v32i1(<32 x i1> %a, <32 x i1> %b, <32 x i1> %cc) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <32 x i1> %cc, <32 x i1> %a, <32 x i1> %b
ret <32 x i1> %v
@@ -287,9 +287,9 @@ define <64 x i1> @vselect_v64i1(<64 x i1> %a, <64 x i1> %b, <64 x i1> %cc) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <64 x i1> %cc, <64 x i1> %a, <64 x i1> %b
ret <64 x i1> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
index 44589759e8a5d..3c191b122e712 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
@@ -11,9 +11,9 @@ define <8 x i7> @vsll_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vx v25, v9, a1
+; CHECK-NEXT: vand.vx v9, v9, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vsll.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.shl.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
index 410c325e4a687..71f0580f87f6c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
@@ -11,11 +11,11 @@ define <8 x i7> @vsra_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vx v25, v9, a1
-; CHECK-NEXT: vadd.vv v26, v8, v8
-; CHECK-NEXT: vsra.vi v26, v26, 1
+; CHECK-NEXT: vand.vx v9, v9, a1
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vsra.vv v8, v26, v25, v0.t
+; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.ashr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
index fd86ee63c03f7..fd5e71e4654ae 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
@@ -11,10 +11,10 @@ define <8 x i7> @vsrl_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 127
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vx v25, v9, a1
-; CHECK-NEXT: vand.vx v26, v8, a1
+; CHECK-NEXT: vand.vx v9, v9, a1
+; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vsrl.vv v8, v26, v25, v0.t
+; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i7> @llvm.vp.lshr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
ret <8 x i7> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
index ebd30ef88c6f5..b38a944f5302b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
@@ -469,8 +469,8 @@ define <2 x i64> @ssub_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -519,8 +519,8 @@ define <4 x i64> @ssub_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -569,8 +569,8 @@ define <8 x i64> @ssub_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
index 361d0773c0647..9e345c93d3a67 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
@@ -469,8 +469,8 @@ define <2 x i64> @usub_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -519,8 +519,8 @@ define <4 x i64> @usub_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -569,8 +569,8 @@ define <8 x i64> @usub_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
index d7f0b5ff2523b..e4d100c44407f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
@@ -699,9 +699,9 @@ define <2 x i64> @vsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v25, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -725,9 +725,9 @@ define <2 x i64> @vsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v25
+; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -777,9 +777,9 @@ define <4 x i64> @vsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v26, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -803,9 +803,9 @@ define <4 x i64> @vsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v26
+; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -855,9 +855,9 @@ define <8 x i64> @vsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v28, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -881,9 +881,9 @@ define <8 x i64> @vsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v28
+; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
index bd1b3e5e2c527..a7ff2aa52af63 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
@@ -6,9 +6,9 @@ define <2 x i16> @vwmacc_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmacc_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = load <2 x i8>, <2 x i8>* %y
@@ -23,9 +23,9 @@ define <4 x i16> @vwmacc_v4i16(<4 x i8>* %x, <4 x i8>* %y, <4 x i16> %z) {
; CHECK-LABEL: vwmacc_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = load <4 x i8>, <4 x i8>* %y
@@ -40,9 +40,9 @@ define <2 x i32> @vwmacc_v2i32(<2 x i16>* %x, <2 x i16>* %y, <2 x i32> %z) {
; CHECK-LABEL: vwmacc_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = load <2 x i16>, <2 x i16>* %y
@@ -57,9 +57,9 @@ define <8 x i16> @vwmacc_v8i16(<8 x i8>* %x, <8 x i8>* %y, <8 x i16> %z) {
; CHECK-LABEL: vwmacc_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -74,9 +74,9 @@ define <4 x i32> @vwmacc_v4i32(<4 x i16>* %x, <4 x i16>* %y, <4 x i32> %z) {
; CHECK-LABEL: vwmacc_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load <4 x i16>, <4 x i16>* %y
@@ -91,9 +91,9 @@ define <2 x i64> @vwmacc_v2i64(<2 x i32>* %x, <2 x i32>* %y, <2 x i64> %z) {
; CHECK-LABEL: vwmacc_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load <2 x i32>, <2 x i32>* %y
@@ -108,9 +108,9 @@ define <16 x i16> @vwmacc_v16i16(<16 x i8>* %x, <16 x i8>* %y, <16 x i16> %z) {
; CHECK-LABEL: vwmacc_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vle8.v v11, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -125,9 +125,9 @@ define <8 x i32> @vwmacc_v8i32(<8 x i16>* %x, <8 x i16>* %y, <8 x i32> %z) {
; CHECK-LABEL: vwmacc_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vle16.v v11, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -142,9 +142,9 @@ define <4 x i64> @vwmacc_v4i64(<4 x i32>* %x, <4 x i32>* %y, <4 x i64> %z) {
; CHECK-LABEL: vwmacc_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vle32.v v11, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -160,9 +160,9 @@ define <32 x i16> @vwmacc_v32i16(<32 x i8>* %x, <32 x i8>* %y, <32 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vle8.v v28, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v26, v28
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vle8.v v14, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -177,9 +177,9 @@ define <16 x i32> @vwmacc_v16i32(<16 x i16>* %x, <16 x i16>* %y, <16 x i32> %z)
; CHECK-LABEL: vwmacc_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v26, v28
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vle16.v v14, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -194,9 +194,9 @@ define <8 x i64> @vwmacc_v8i64(<8 x i32>* %x, <8 x i32>* %y, <8 x i64> %z) {
; CHECK-LABEL: vwmacc_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v26, v28
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vle32.v v14, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -212,9 +212,9 @@ define <64 x i16> @vwmacc_v64i16(<64 x i8>* %x, <64 x i8>* %y, <64 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vle8.v v16, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v28, v16
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vle8.v v20, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -230,9 +230,9 @@ define <32 x i32> @vwmacc_v32i32(<32 x i16>* %x, <32 x i16>* %y, <32 x i32> %z)
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v28, v16
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vle16.v v20, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = load <32 x i16>, <32 x i16>* %y
@@ -247,9 +247,9 @@ define <16 x i64> @vwmacc_v16i64(<16 x i32>* %x, <16 x i32>* %y, <16 x i64> %z)
; CHECK-LABEL: vwmacc_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vwmacc.vv v8, v28, v16
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v20, (a1)
+; CHECK-NEXT: vwmacc.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = load <16 x i32>, <16 x i32>* %y
@@ -264,8 +264,8 @@ define <2 x i16> @vwmacc_vx_v2i16(<2 x i8>* %x, i8 %y, <2 x i16> %z) {
; CHECK-LABEL: vwmacc_vx_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = insertelement <2 x i8> undef, i8 %y, i32 0
@@ -281,8 +281,8 @@ define <4 x i16> @vwmacc_vx_v4i16(<4 x i8>* %x, i8 %y, <4 x i16> %z) {
; CHECK-LABEL: vwmacc_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = insertelement <4 x i8> undef, i8 %y, i32 0
@@ -298,8 +298,8 @@ define <2 x i32> @vwmacc_vx_v2i32(<2 x i16>* %x, i16 %y, <2 x i32> %z) {
; CHECK-LABEL: vwmacc_vx_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = insertelement <2 x i16> undef, i16 %y, i32 0
@@ -315,8 +315,8 @@ define <8 x i16> @vwmacc_vx_v8i16(<8 x i8>* %x, i8 %y, <8 x i16> %z) {
; CHECK-LABEL: vwmacc_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -332,8 +332,8 @@ define <4 x i32> @vwmacc_vx_v4i32(<4 x i16>* %x, i16 %y, <4 x i32> %z) {
; CHECK-LABEL: vwmacc_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = insertelement <4 x i16> undef, i16 %y, i32 0
@@ -349,8 +349,8 @@ define <2 x i64> @vwmacc_vx_v2i64(<2 x i32>* %x, i32 %y, <2 x i64> %z) {
; CHECK-LABEL: vwmacc_vx_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = insertelement <2 x i32> undef, i32 %y, i64 0
@@ -366,8 +366,8 @@ define <16 x i16> @vwmacc_vx_v16i16(<16 x i8>* %x, i8 %y, <16 x i16> %z) {
; CHECK-LABEL: vwmacc_vx_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -383,8 +383,8 @@ define <8 x i32> @vwmacc_vx_v8i32(<8 x i16>* %x, i16 %y, <8 x i32> %z) {
; CHECK-LABEL: vwmacc_vx_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -400,8 +400,8 @@ define <4 x i64> @vwmacc_vx_v4i64(<4 x i32>* %x, i32 %y, <4 x i64> %z) {
; CHECK-LABEL: vwmacc_vx_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v25
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i64 0
@@ -418,8 +418,8 @@ define <32 x i16> @vwmacc_vx_v32i16(<32 x i8>* %x, i8 %y, <32 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v26
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -435,8 +435,8 @@ define <16 x i32> @vwmacc_vx_v16i32(<16 x i16>* %x, i16 %y, <16 x i32> %z) {
; CHECK-LABEL: vwmacc_vx_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v26
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = insertelement <16 x i16> undef, i16 %y, i32 0
@@ -452,8 +452,8 @@ define <8 x i64> @vwmacc_vx_v8i64(<8 x i32>* %x, i32 %y, <8 x i64> %z) {
; CHECK-LABEL: vwmacc_vx_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v26
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = insertelement <8 x i32> undef, i32 %y, i64 0
@@ -470,8 +470,8 @@ define <64 x i16> @vwmacc_vx_v64i16(<64 x i8>* %x, i8 %y, <64 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v28
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -488,8 +488,8 @@ define <32 x i32> @vwmacc_vx_v32i32(<32 x i16>* %x, i16 %y, <32 x i32> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v28
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = insertelement <32 x i16> undef, i16 %y, i32 0
@@ -505,8 +505,8 @@ define <16 x i64> @vwmacc_vx_v16i64(<16 x i32>* %x, i32 %y, <16 x i64> %z) {
; CHECK-LABEL: vwmacc_vx_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vwmacc.vx v8, a1, v28
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vwmacc.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = insertelement <16 x i32> undef, i32 %y, i64 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
index 9cae8d23ef6f6..040bee273e9f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
@@ -6,9 +6,9 @@ define <2 x i16> @vwmaccu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccu_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = load <2 x i8>, <2 x i8>* %y
@@ -23,9 +23,9 @@ define <4 x i16> @vwmaccu_v4i16(<4 x i8>* %x, <4 x i8>* %y, <4 x i16> %z) {
; CHECK-LABEL: vwmaccu_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = load <4 x i8>, <4 x i8>* %y
@@ -40,9 +40,9 @@ define <2 x i32> @vwmaccu_v2i32(<2 x i16>* %x, <2 x i16>* %y, <2 x i32> %z) {
; CHECK-LABEL: vwmaccu_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = load <2 x i16>, <2 x i16>* %y
@@ -57,9 +57,9 @@ define <8 x i16> @vwmaccu_v8i16(<8 x i8>* %x, <8 x i8>* %y, <8 x i16> %z) {
; CHECK-LABEL: vwmaccu_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -74,9 +74,9 @@ define <4 x i32> @vwmaccu_v4i32(<4 x i16>* %x, <4 x i16>* %y, <4 x i32> %z) {
; CHECK-LABEL: vwmaccu_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load <4 x i16>, <4 x i16>* %y
@@ -91,9 +91,9 @@ define <2 x i64> @vwmaccu_v2i64(<2 x i32>* %x, <2 x i32>* %y, <2 x i64> %z) {
; CHECK-LABEL: vwmaccu_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load <2 x i32>, <2 x i32>* %y
@@ -108,9 +108,9 @@ define <16 x i16> @vwmaccu_v16i16(<16 x i8>* %x, <16 x i8>* %y, <16 x i16> %z) {
; CHECK-LABEL: vwmaccu_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vle8.v v11, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -125,9 +125,9 @@ define <8 x i32> @vwmaccu_v8i32(<8 x i16>* %x, <8 x i16>* %y, <8 x i32> %z) {
; CHECK-LABEL: vwmaccu_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vle16.v v11, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -142,9 +142,9 @@ define <4 x i64> @vwmaccu_v4i64(<4 x i32>* %x, <4 x i32>* %y, <4 x i64> %z) {
; CHECK-LABEL: vwmaccu_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vle32.v v11, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -160,9 +160,9 @@ define <32 x i16> @vwmaccu_v32i16(<32 x i8>* %x, <32 x i8>* %y, <32 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vle8.v v28, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v26, v28
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vle8.v v14, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -177,9 +177,9 @@ define <16 x i32> @vwmaccu_v16i32(<16 x i16>* %x, <16 x i16>* %y, <16 x i32> %z)
; CHECK-LABEL: vwmaccu_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v26, v28
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vle16.v v14, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -194,9 +194,9 @@ define <8 x i64> @vwmaccu_v8i64(<8 x i32>* %x, <8 x i32>* %y, <8 x i64> %z) {
; CHECK-LABEL: vwmaccu_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v26, v28
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vle32.v v14, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -212,9 +212,9 @@ define <64 x i16> @vwmaccu_v64i16(<64 x i8>* %x, <64 x i8>* %y, <64 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vle8.v v16, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v28, v16
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vle8.v v20, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -230,9 +230,9 @@ define <32 x i32> @vwmaccu_v32i32(<32 x i16>* %x, <32 x i16>* %y, <32 x i32> %z)
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v28, v16
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vle16.v v20, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = load <32 x i16>, <32 x i16>* %y
@@ -247,9 +247,9 @@ define <16 x i64> @vwmaccu_v16i64(<16 x i32>* %x, <16 x i32>* %y, <16 x i64> %z)
; CHECK-LABEL: vwmaccu_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vwmaccu.vv v8, v28, v16
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v20, (a1)
+; CHECK-NEXT: vwmaccu.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = load <16 x i32>, <16 x i32>* %y
@@ -264,8 +264,8 @@ define <2 x i16> @vwmaccu_vx_v2i16(<2 x i8>* %x, i8 %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccu_vx_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = insertelement <2 x i8> undef, i8 %y, i32 0
@@ -281,8 +281,8 @@ define <4 x i16> @vwmaccu_vx_v4i16(<4 x i8>* %x, i8 %y, <4 x i16> %z) {
; CHECK-LABEL: vwmaccu_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = insertelement <4 x i8> undef, i8 %y, i32 0
@@ -298,8 +298,8 @@ define <2 x i32> @vwmaccu_vx_v2i32(<2 x i16>* %x, i16 %y, <2 x i32> %z) {
; CHECK-LABEL: vwmaccu_vx_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = insertelement <2 x i16> undef, i16 %y, i32 0
@@ -315,8 +315,8 @@ define <8 x i16> @vwmaccu_vx_v8i16(<8 x i8>* %x, i8 %y, <8 x i16> %z) {
; CHECK-LABEL: vwmaccu_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -332,8 +332,8 @@ define <4 x i32> @vwmaccu_vx_v4i32(<4 x i16>* %x, i16 %y, <4 x i32> %z) {
; CHECK-LABEL: vwmaccu_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = insertelement <4 x i16> undef, i16 %y, i32 0
@@ -349,8 +349,8 @@ define <2 x i64> @vwmaccu_vx_v2i64(<2 x i32>* %x, i32 %y, <2 x i64> %z) {
; CHECK-LABEL: vwmaccu_vx_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = insertelement <2 x i32> undef, i32 %y, i64 0
@@ -366,8 +366,8 @@ define <16 x i16> @vwmaccu_vx_v16i16(<16 x i8>* %x, i8 %y, <16 x i16> %z) {
; CHECK-LABEL: vwmaccu_vx_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -383,8 +383,8 @@ define <8 x i32> @vwmaccu_vx_v8i32(<8 x i16>* %x, i16 %y, <8 x i32> %z) {
; CHECK-LABEL: vwmaccu_vx_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -400,8 +400,8 @@ define <4 x i64> @vwmaccu_vx_v4i64(<4 x i32>* %x, i32 %y, <4 x i64> %z) {
; CHECK-LABEL: vwmaccu_vx_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v25
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i64 0
@@ -418,8 +418,8 @@ define <32 x i16> @vwmaccu_vx_v32i16(<32 x i8>* %x, i8 %y, <32 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v26
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -435,8 +435,8 @@ define <16 x i32> @vwmaccu_vx_v16i32(<16 x i16>* %x, i16 %y, <16 x i32> %z) {
; CHECK-LABEL: vwmaccu_vx_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v26
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = insertelement <16 x i16> undef, i16 %y, i32 0
@@ -452,8 +452,8 @@ define <8 x i64> @vwmaccu_vx_v8i64(<8 x i32>* %x, i32 %y, <8 x i64> %z) {
; CHECK-LABEL: vwmaccu_vx_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v26
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = insertelement <8 x i32> undef, i32 %y, i64 0
@@ -470,8 +470,8 @@ define <64 x i16> @vwmaccu_vx_v64i16(<64 x i8>* %x, i8 %y, <64 x i16> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v28
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -488,8 +488,8 @@ define <32 x i32> @vwmaccu_vx_v32i32(<32 x i16>* %x, i16 %y, <32 x i32> %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v28
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = insertelement <32 x i16> undef, i16 %y, i32 0
@@ -505,8 +505,8 @@ define <16 x i64> @vwmaccu_vx_v16i64(<16 x i32>* %x, i32 %y, <16 x i64> %z) {
; CHECK-LABEL: vwmaccu_vx_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vwmaccu.vx v8, a1, v28
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vwmaccu.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = insertelement <16 x i32> undef, i32 %y, i64 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
index 025e3197f0f84..8439b357b30f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
@@ -6,9 +6,9 @@ define <2 x i16> @vwmul_v2i16(<2 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: vwmul_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmul.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = load <2 x i8>, <2 x i8>* %y
@@ -22,9 +22,9 @@ define <4 x i16> @vwmul_v4i16(<4 x i8>* %x, <4 x i8>* %y) {
; CHECK-LABEL: vwmul_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmul.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = load <4 x i8>, <4 x i8>* %y
@@ -38,9 +38,9 @@ define <2 x i32> @vwmul_v2i32(<2 x i16>* %x, <2 x i16>* %y) {
; CHECK-LABEL: vwmul_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmul.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = load <2 x i16>, <2 x i16>* %y
@@ -54,9 +54,9 @@ define <8 x i16> @vwmul_v8i16(<8 x i8>* %x, <8 x i8>* %y) {
; CHECK-LABEL: vwmul_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmul.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -70,9 +70,9 @@ define <4 x i32> @vwmul_v4i32(<4 x i16>* %x, <4 x i16>* %y) {
; CHECK-LABEL: vwmul_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmul.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load <4 x i16>, <4 x i16>* %y
@@ -86,9 +86,9 @@ define <2 x i64> @vwmul_v2i64(<2 x i32>* %x, <2 x i32>* %y) {
; CHECK-LABEL: vwmul_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vwmul.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load <2 x i32>, <2 x i32>* %y
@@ -102,9 +102,9 @@ define <16 x i16> @vwmul_v16i16(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: vwmul_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vle8.v v11, (a1)
+; CHECK-NEXT: vwmul.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -118,9 +118,9 @@ define <8 x i32> @vwmul_v8i32(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: vwmul_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vle16.v v11, (a1)
+; CHECK-NEXT: vwmul.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -134,9 +134,9 @@ define <4 x i64> @vwmul_v4i64(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: vwmul_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmul.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vle32.v v11, (a1)
+; CHECK-NEXT: vwmul.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -151,9 +151,9 @@ define <32 x i16> @vwmul_v32i16(<32 x i8>* %x, <32 x i8>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vle8.v v28, (a1)
-; CHECK-NEXT: vwmul.vv v8, v26, v28
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vle8.v v14, (a1)
+; CHECK-NEXT: vwmul.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -167,9 +167,9 @@ define <16 x i32> @vwmul_v16i32(<16 x i16>* %x, <16 x i16>* %y) {
; CHECK-LABEL: vwmul_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vwmul.vv v8, v26, v28
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vle16.v v14, (a1)
+; CHECK-NEXT: vwmul.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -183,9 +183,9 @@ define <8 x i64> @vwmul_v8i64(<8 x i32>* %x, <8 x i32>* %y) {
; CHECK-LABEL: vwmul_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vwmul.vv v8, v26, v28
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vle32.v v14, (a1)
+; CHECK-NEXT: vwmul.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -200,9 +200,9 @@ define <64 x i16> @vwmul_v64i16(<64 x i8>* %x, <64 x i8>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vle8.v v16, (a1)
-; CHECK-NEXT: vwmul.vv v8, v28, v16
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vle8.v v20, (a1)
+; CHECK-NEXT: vwmul.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -217,9 +217,9 @@ define <32 x i32> @vwmul_v32i32(<32 x i16>* %x, <32 x i16>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vwmul.vv v8, v28, v16
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vle16.v v20, (a1)
+; CHECK-NEXT: vwmul.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = load <32 x i16>, <32 x i16>* %y
@@ -233,9 +233,9 @@ define <16 x i64> @vwmul_v16i64(<16 x i32>* %x, <16 x i32>* %y) {
; CHECK-LABEL: vwmul_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vwmul.vv v8, v28, v16
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v20, (a1)
+; CHECK-NEXT: vwmul.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = load <16 x i32>, <16 x i32>* %y
@@ -356,12 +356,12 @@ define <2 x i32> @vwmul_v2i32_v2i8(<2 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: vwmul_v2i32_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vsext.vf2 v27, v25
-; CHECK-NEXT: vsext.vf2 v25, v26
-; CHECK-NEXT: vwmul.vv v8, v25, v27
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vsext.vf2 v11, v9
+; CHECK-NEXT: vwmul.vv v8, v11, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = load <2 x i8>, <2 x i8>* %y
@@ -375,11 +375,11 @@ define <4 x i32> @vwmul_v4i32_v4i8_v4i16(<4 x i8>* %x, <4 x i16>* %y) {
; CHECK-LABEL: vwmul_v4i32_v4i8_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v27, v25
-; CHECK-NEXT: vwmul.vv v8, v27, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vwmul.vv v8, v10, v9
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = load <4 x i16>, <4 x i16>* %y
@@ -393,10 +393,10 @@ define <4 x i64> @vwmul_v4i64_v4i32_v4i8(<4 x i32>* %x, <4 x i8>* %y) {
; CHECK-LABEL: vwmul_v4i64_v4i32_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vsext.vf4 v27, v25
-; CHECK-NEXT: vwmul.vv v8, v26, v27
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vsext.vf4 v11, v8
+; CHECK-NEXT: vwmul.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i8>, <4 x i8>* %y
@@ -410,8 +410,8 @@ define <2 x i16> @vwmul_vx_v2i16(<2 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmul_vx_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmul.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = insertelement <2 x i8> undef, i8 %y, i32 0
@@ -426,8 +426,8 @@ define <4 x i16> @vwmul_vx_v4i16(<4 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmul_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmul.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = insertelement <4 x i8> undef, i8 %y, i32 0
@@ -442,8 +442,8 @@ define <2 x i32> @vwmul_vx_v2i32(<2 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmul_vx_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmul.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = insertelement <2 x i16> undef, i16 %y, i32 0
@@ -458,8 +458,8 @@ define <8 x i16> @vwmul_vx_v8i16(<8 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmul_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmul.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -474,8 +474,8 @@ define <4 x i32> @vwmul_vx_v4i32(<4 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmul_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmul.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = insertelement <4 x i16> undef, i16 %y, i32 0
@@ -490,8 +490,8 @@ define <2 x i64> @vwmul_vx_v2i64(<2 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmul_vx_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vwmul.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = insertelement <2 x i32> undef, i32 %y, i64 0
@@ -506,8 +506,8 @@ define <16 x i16> @vwmul_vx_v16i16(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmul_vx_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vwmul.vx v8, v10, a1
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -522,8 +522,8 @@ define <8 x i32> @vwmul_vx_v8i32(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmul_vx_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vwmul.vx v8, v10, a1
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -538,8 +538,8 @@ define <4 x i64> @vwmul_vx_v4i64(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmul_vx_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmul.vx v8, v25, a1
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vwmul.vx v8, v10, a1
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i64 0
@@ -555,8 +555,8 @@ define <32 x i16> @vwmul_vx_v32i16(<32 x i8>* %x, i8 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vwmul.vx v8, v26, a1
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vwmul.vx v8, v12, a1
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -571,8 +571,8 @@ define <16 x i32> @vwmul_vx_v16i32(<16 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmul_vx_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vwmul.vx v8, v26, a1
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vwmul.vx v8, v12, a1
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = insertelement <16 x i16> undef, i16 %y, i32 0
@@ -587,8 +587,8 @@ define <8 x i64> @vwmul_vx_v8i64(<8 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmul_vx_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vwmul.vx v8, v26, a1
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vwmul.vx v8, v12, a1
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = insertelement <8 x i32> undef, i32 %y, i64 0
@@ -604,8 +604,8 @@ define <64 x i16> @vwmul_vx_v64i16(<64 x i8>* %x, i8 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vwmul.vx v8, v28, a1
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vwmul.vx v8, v16, a1
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -621,8 +621,8 @@ define <32 x i32> @vwmul_vx_v32i32(<32 x i16>* %x, i16 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vwmul.vx v8, v28, a1
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vwmul.vx v8, v16, a1
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = insertelement <32 x i16> undef, i16 %y, i32 0
@@ -637,8 +637,8 @@ define <16 x i64> @vwmul_vx_v16i64(<16 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmul_vx_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vwmul.vx v8, v28, a1
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vwmul.vx v8, v16, a1
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = insertelement <16 x i32> undef, i32 %y, i64 0
@@ -653,9 +653,9 @@ define <8 x i16> @vwmul_vx_v8i16_i8(<8 x i8>* %x, i8* %y) {
; CHECK-LABEL: vwmul_vx_v8i16_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: lb a0, 0(a1)
-; CHECK-NEXT: vwmul.vx v8, v25, a0
+; CHECK-NEXT: vwmul.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i8, i8* %y
@@ -671,11 +671,11 @@ define <8 x i16> @vwmul_vx_v8i16_i16(<8 x i8>* %x, i16* %y) {
; CHECK-LABEL: vwmul_vx_v8i16_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: lh a0, 0(a1)
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v25
-; CHECK-NEXT: vmul.vx v8, v26, a0
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmul.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i16, i16* %y
@@ -690,9 +690,9 @@ define <4 x i32> @vwmul_vx_v4i32_i8(<4 x i16>* %x, i8* %y) {
; CHECK-LABEL: vwmul_vx_v4i32_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: lb a0, 0(a1)
-; CHECK-NEXT: vwmul.vx v8, v25, a0
+; CHECK-NEXT: vwmul.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i8, i8* %y
@@ -708,9 +708,9 @@ define <4 x i32> @vwmul_vx_v4i32_i16(<4 x i16>* %x, i16* %y) {
; CHECK-LABEL: vwmul_vx_v4i32_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: lh a0, 0(a1)
-; CHECK-NEXT: vwmul.vx v8, v25, a0
+; CHECK-NEXT: vwmul.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i16, i16* %y
@@ -726,11 +726,11 @@ define <4 x i32> @vwmul_vx_v4i32_i32(<4 x i16>* %x, i32* %y) {
; CHECK-LABEL: vwmul_vx_v4i32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lw a0, 0(a1)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v25
-; CHECK-NEXT: vmul.vx v8, v26, a0
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmul.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i32, i32* %y
@@ -748,24 +748,24 @@ define <2 x i64> @vwmul_vx_v2i64_i8(<2 x i32>* %x, i8* %y) {
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: lb a1, 0(a1)
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: srai a0, a1, 31
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT: vsext.vf2 v27, v25
-; RV32-NEXT: vmul.vv v8, v26, v27
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vmul.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vwmul_vx_v2i64_i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: lb a0, 0(a1)
-; RV64-NEXT: vwmul.vx v8, v25, a0
+; RV64-NEXT: vwmul.vx v8, v9, a0
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i8, i8* %y
@@ -784,24 +784,24 @@ define <2 x i64> @vwmul_vx_v2i64_i16(<2 x i32>* %x, i16* %y) {
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: lh a1, 0(a1)
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: srai a0, a1, 31
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT: vsext.vf2 v27, v25
-; RV32-NEXT: vmul.vv v8, v26, v27
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vmul.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vwmul_vx_v2i64_i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: lh a0, 0(a1)
-; RV64-NEXT: vwmul.vx v8, v25, a0
+; RV64-NEXT: vwmul.vx v8, v9, a0
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i16, i16* %y
@@ -820,24 +820,24 @@ define <2 x i64> @vwmul_vx_v2i64_i32(<2 x i32>* %x, i32* %y) {
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: srai a0, a1, 31
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT: vsext.vf2 v27, v25
-; RV32-NEXT: vmul.vv v8, v26, v27
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vmul.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vwmul_vx_v2i64_i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: lw a0, 0(a1)
-; RV64-NEXT: vwmul.vx v8, v25, a0
+; RV64-NEXT: vwmul.vx v8, v9, a0
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i32, i32* %y
@@ -857,25 +857,25 @@ define <2 x i64> @vwmul_vx_v2i64_i64(<2 x i32>* %x, i64* %y) {
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: vle32.v v25, (a0)
+; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-NEXT: vsext.vf2 v27, v25
-; RV32-NEXT: vmul.vv v8, v26, v27
+; RV32-NEXT: vsext.vf2 v10, v8
+; RV32-NEXT: vmul.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vwmul_vx_v2i64_i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; RV64-NEXT: vle32.v v25, (a0)
+; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: ld a0, 0(a1)
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV64-NEXT: vsext.vf2 v26, v25
-; RV64-NEXT: vmul.vx v8, v26, a0
+; RV64-NEXT: vsext.vf2 v9, v8
+; RV64-NEXT: vmul.vx v8, v9, a0
; RV64-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load i64, i64* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
index 45083b5304573..7d3ca3bd1c214 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
@@ -6,9 +6,9 @@ define <2 x i16> @vwmulu_v2i16(<2 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: vwmulu_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = load <2 x i8>, <2 x i8>* %y
@@ -22,9 +22,9 @@ define <4 x i16> @vwmulu_v4i16(<4 x i8>* %x, <4 x i8>* %y) {
; CHECK-LABEL: vwmulu_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = load <4 x i8>, <4 x i8>* %y
@@ -38,9 +38,9 @@ define <2 x i32> @vwmulu_v2i32(<2 x i16>* %x, <2 x i16>* %y) {
; CHECK-LABEL: vwmulu_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = load <2 x i16>, <2 x i16>* %y
@@ -54,9 +54,9 @@ define <8 x i16> @vwmulu_v8i16(<8 x i8>* %x, <8 x i8>* %y) {
; CHECK-LABEL: vwmulu_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vle8.v v10, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -70,9 +70,9 @@ define <4 x i32> @vwmulu_v4i32(<4 x i16>* %x, <4 x i16>* %y) {
; CHECK-LABEL: vwmulu_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load <4 x i16>, <4 x i16>* %y
@@ -86,9 +86,9 @@ define <2 x i64> @vwmulu_v2i64(<2 x i32>* %x, <2 x i32>* %y) {
; CHECK-LABEL: vwmulu_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v9, v10
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = load <2 x i32>, <2 x i32>* %y
@@ -102,9 +102,9 @@ define <16 x i16> @vwmulu_v16i16(<16 x i8>* %x, <16 x i8>* %y) {
; CHECK-LABEL: vwmulu_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle8.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vle8.v v11, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -118,9 +118,9 @@ define <8 x i32> @vwmulu_v8i32(<8 x i16>* %x, <8 x i16>* %y) {
; CHECK-LABEL: vwmulu_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vle16.v v11, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = load <8 x i16>, <8 x i16>* %y
@@ -134,9 +134,9 @@ define <4 x i64> @vwmulu_v4i64(<4 x i32>* %x, <4 x i32>* %y) {
; CHECK-LABEL: vwmulu_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v25, v26
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vle32.v v11, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y
@@ -151,9 +151,9 @@ define <32 x i16> @vwmulu_v32i16(<32 x i8>* %x, <32 x i8>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vle8.v v28, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v26, v28
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vle8.v v14, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -167,9 +167,9 @@ define <16 x i32> @vwmulu_v16i32(<16 x i16>* %x, <16 x i16>* %y) {
; CHECK-LABEL: vwmulu_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle16.v v28, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v26, v28
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vle16.v v14, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = load <16 x i16>, <16 x i16>* %y
@@ -183,9 +183,9 @@ define <8 x i64> @vwmulu_v8i64(<8 x i32>* %x, <8 x i32>* %y) {
; CHECK-LABEL: vwmulu_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle32.v v28, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v26, v28
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vle32.v v14, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v12, v14
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y
@@ -200,9 +200,9 @@ define <64 x i16> @vwmulu_v64i16(<64 x i8>* %x, <64 x i8>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vle8.v v16, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v28, v16
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vle8.v v20, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -217,9 +217,9 @@ define <32 x i32> @vwmulu_v32i32(<32 x i16>* %x, <32 x i16>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v28, v16
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vle16.v v20, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = load <32 x i16>, <32 x i16>* %y
@@ -233,9 +233,9 @@ define <16 x i64> @vwmulu_v16i64(<16 x i32>* %x, <16 x i32>* %y) {
; CHECK-LABEL: vwmulu_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vle32.v v16, (a1)
-; CHECK-NEXT: vwmulu.vv v8, v28, v16
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v20, (a1)
+; CHECK-NEXT: vwmulu.vv v8, v16, v20
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = load <16 x i32>, <16 x i32>* %y
@@ -356,12 +356,12 @@ define <2 x i32> @vwmulu_v2i32_v2i8(<2 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: vwmulu_v2i32_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vle8.v v26, (a0)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vzext.vf2 v27, v25
-; CHECK-NEXT: vzext.vf2 v25, v26
-; CHECK-NEXT: vwmulu.vv v8, v25, v27
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vzext.vf2 v11, v9
+; CHECK-NEXT: vwmulu.vv v8, v11, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = load <2 x i8>, <2 x i8>* %y
@@ -375,11 +375,11 @@ define <4 x i32> @vwmulu_v4i32_v4i8_v4i16(<4 x i8>* %x, <4 x i16>* %y) {
; CHECK-LABEL: vwmulu_v4i32_v4i8_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vle16.v v26, (a1)
+; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v27, v25
-; CHECK-NEXT: vwmulu.vv v8, v27, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vwmulu.vv v8, v10, v9
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = load <4 x i16>, <4 x i16>* %y
@@ -393,10 +393,10 @@ define <4 x i64> @vwmulu_v4i64_v4i32_v4i8(<4 x i32>* %x, <4 x i8>* %y) {
; CHECK-LABEL: vwmulu_v4i64_v4i32_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vzext.vf4 v27, v25
-; CHECK-NEXT: vwmulu.vv v8, v26, v27
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vzext.vf4 v11, v8
+; CHECK-NEXT: vwmulu.vv v8, v10, v11
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i8>, <4 x i8>* %y
@@ -410,8 +410,8 @@ define <2 x i16> @vwmulu_vx_v2i16(<2 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmulu_vx_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <2 x i8>, <2 x i8>* %x
%b = insertelement <2 x i8> undef, i8 %y, i32 0
@@ -426,8 +426,8 @@ define <4 x i16> @vwmulu_vx_v4i16(<4 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmulu_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <4 x i8>, <4 x i8>* %x
%b = insertelement <4 x i8> undef, i8 %y, i32 0
@@ -442,8 +442,8 @@ define <2 x i32> @vwmulu_vx_v2i32(<2 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmulu_vx_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <2 x i16>, <2 x i16>* %x
%b = insertelement <2 x i16> undef, i16 %y, i32 0
@@ -458,8 +458,8 @@ define <8 x i16> @vwmulu_vx_v8i16(<8 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmulu_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -474,8 +474,8 @@ define <4 x i32> @vwmulu_vx_v4i32(<4 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmulu_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle16.v v9, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = insertelement <4 x i16> undef, i16 %y, i32 0
@@ -490,8 +490,8 @@ define <2 x i64> @vwmulu_vx_v2i64(<2 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmulu_vx_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v9, a1
; CHECK-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %x
%b = insertelement <2 x i32> undef, i32 %y, i64 0
@@ -506,8 +506,8 @@ define <16 x i16> @vwmulu_vx_v16i16(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: vwmulu_vx_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v10, a1
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -522,8 +522,8 @@ define <8 x i32> @vwmulu_vx_v8i32(<8 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmulu_vx_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle16.v v10, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v10, a1
; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x
%b = insertelement <8 x i16> undef, i16 %y, i32 0
@@ -538,8 +538,8 @@ define <4 x i64> @vwmulu_vx_v4i64(<4 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmulu_vx_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v25, a1
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v10, a1
; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x
%b = insertelement <4 x i32> undef, i32 %y, i64 0
@@ -555,8 +555,8 @@ define <32 x i16> @vwmulu_vx_v32i16(<32 x i8>* %x, i8 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle8.v v26, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v26, a1
+; CHECK-NEXT: vle8.v v12, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v12, a1
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -571,8 +571,8 @@ define <16 x i32> @vwmulu_vx_v16i32(<16 x i16>* %x, i16 %y) {
; CHECK-LABEL: vwmulu_vx_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v26, a1
+; CHECK-NEXT: vle16.v v12, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v12, a1
; CHECK-NEXT: ret
%a = load <16 x i16>, <16 x i16>* %x
%b = insertelement <16 x i16> undef, i16 %y, i32 0
@@ -587,8 +587,8 @@ define <8 x i64> @vwmulu_vx_v8i64(<8 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmulu_vx_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v26, a1
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v12, a1
; CHECK-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x
%b = insertelement <8 x i32> undef, i32 %y, i64 0
@@ -604,8 +604,8 @@ define <64 x i16> @vwmulu_vx_v64i16(<64 x i8>* %x, i8 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
-; CHECK-NEXT: vle8.v v28, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v28, a1
+; CHECK-NEXT: vle8.v v16, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v16, a1
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -621,8 +621,8 @@ define <32 x i32> @vwmulu_vx_v32i32(<32 x i16>* %x, i16 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
-; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v28, a1
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v16, a1
; CHECK-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x
%b = insertelement <32 x i16> undef, i16 %y, i32 0
@@ -637,8 +637,8 @@ define <16 x i64> @vwmulu_vx_v16i64(<16 x i32>* %x, i32 %y) {
; CHECK-LABEL: vwmulu_vx_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle32.v v28, (a0)
-; CHECK-NEXT: vwmulu.vx v8, v28, a1
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vwmulu.vx v8, v16, a1
; CHECK-NEXT: ret
%a = load <16 x i32>, <16 x i32>* %x
%b = insertelement <16 x i32> undef, i32 %y, i64 0
@@ -653,9 +653,9 @@ define <8 x i16> @vwmulu_vx_v8i16_i8(<8 x i8>* %x, i8* %y) {
; CHECK-LABEL: vwmulu_vx_v8i16_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: lbu a0, 0(a1)
-; CHECK-NEXT: vwmulu.vx v8, v25, a0
+; CHECK-NEXT: vwmulu.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i8, i8* %y
@@ -671,11 +671,11 @@ define <8 x i16> @vwmulu_vx_v8i16_i16(<8 x i8>* %x, i16* %y) {
; CHECK-LABEL: vwmulu_vx_v8i16_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: lh a0, 0(a1)
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v25
-; CHECK-NEXT: vmul.vx v8, v26, a0
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmul.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load i16, i16* %y
@@ -690,9 +690,9 @@ define <4 x i32> @vwmulu_vx_v4i32_i8(<4 x i16>* %x, i8* %y) {
; CHECK-LABEL: vwmulu_vx_v4i32_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: lbu a0, 0(a1)
-; CHECK-NEXT: vwmulu.vx v8, v25, a0
+; CHECK-NEXT: vwmulu.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i8, i8* %y
@@ -708,9 +708,9 @@ define <4 x i32> @vwmulu_vx_v4i32_i16(<4 x i16>* %x, i16* %y) {
; CHECK-LABEL: vwmulu_vx_v4i32_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: lhu a0, 0(a1)
-; CHECK-NEXT: vwmulu.vx v8, v25, a0
+; CHECK-NEXT: vwmulu.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i16, i16* %y
@@ -726,11 +726,11 @@ define <4 x i32> @vwmulu_vx_v4i32_i32(<4 x i16>* %x, i32* %y) {
; CHECK-LABEL: vwmulu_vx_v4i32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lw a0, 0(a1)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v25
-; CHECK-NEXT: vmul.vx v8, v26, a0
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmul.vx v8, v9, a0
; CHECK-NEXT: ret
%a = load <4 x i16>, <4 x i16>* %x
%b = load i32, i32* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
index 76eb5aea6f489..4edd829aeb1e2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
@@ -1375,9 +1375,9 @@ define <2 x i64> @vxor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v25, v0.t
+; RV32-NEXT: vxor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1401,9 +1401,9 @@ define <2 x i64> @vxor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v25
+; RV32-NEXT: vxor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1505,9 +1505,9 @@ define <4 x i64> @vxor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v26, v0.t
+; RV32-NEXT: vxor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1531,9 +1531,9 @@ define <4 x i64> @vxor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v26
+; RV32-NEXT: vxor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1635,9 +1635,9 @@ define <8 x i64> @vxor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v28, v0.t
+; RV32-NEXT: vxor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1661,9 +1661,9 @@ define <8 x i64> @vxor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v28
+; RV32-NEXT: vxor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
index 52a9d2bc590ca..a49d44455bb8f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -419,18 +419,18 @@ define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x
; CHECK-LABEL: insert_nxv4i1_nxv1i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v25, v26, 0
+; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0)
ret <vscale x 4 x i1> %vec
@@ -440,20 +440,20 @@ define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x
; CHECK-LABEL: insert_nxv4i1_nxv1i1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v25, v26, a0
+; CHECK-NEXT: vslideup.vx v9, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2)
ret <vscale x 4 x i1> %vec
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
index 30fa63f8d1df8..c2b1a54cdfeac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
@@ -16,9 +16,9 @@ define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %
; CHECK-LABEL: insertelt_nxv1f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
ret <vscale x 1 x half> %r
@@ -28,10 +28,10 @@ define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %
; CHECK-LABEL: insertelt_nxv1f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r
@@ -51,9 +51,9 @@ define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %
; CHECK-LABEL: insertelt_nxv2f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
ret <vscale x 2 x half> %r
@@ -63,10 +63,10 @@ define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %
; CHECK-LABEL: insertelt_nxv2f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r
@@ -86,9 +86,9 @@ define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %
; CHECK-LABEL: insertelt_nxv4f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
ret <vscale x 4 x half> %r
@@ -98,10 +98,10 @@ define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %
; CHECK-LABEL: insertelt_nxv4f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r
@@ -121,9 +121,9 @@ define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %
; CHECK-LABEL: insertelt_nxv8f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
ret <vscale x 8 x half> %r
@@ -133,10 +133,10 @@ define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %
; CHECK-LABEL: insertelt_nxv8f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r
@@ -156,9 +156,9 @@ define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, hal
; CHECK-LABEL: insertelt_nxv16f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
ret <vscale x 16 x half> %r
@@ -168,10 +168,10 @@ define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, hal
; CHECK-LABEL: insertelt_nxv16f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r
@@ -226,9 +226,9 @@ define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, floa
; CHECK-LABEL: insertelt_nxv1f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
ret <vscale x 1 x float> %r
@@ -238,10 +238,10 @@ define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, floa
; CHECK-LABEL: insertelt_nxv1f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
ret <vscale x 1 x float> %r
@@ -261,9 +261,9 @@ define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, floa
; CHECK-LABEL: insertelt_nxv2f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
ret <vscale x 2 x float> %r
@@ -273,10 +273,10 @@ define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, floa
; CHECK-LABEL: insertelt_nxv2f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
ret <vscale x 2 x float> %r
@@ -296,9 +296,9 @@ define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, floa
; CHECK-LABEL: insertelt_nxv4f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 3
ret <vscale x 4 x float> %r
@@ -308,10 +308,10 @@ define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, floa
; CHECK-LABEL: insertelt_nxv4f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
ret <vscale x 4 x float> %r
@@ -331,9 +331,9 @@ define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, floa
; CHECK-LABEL: insertelt_nxv8f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 3
ret <vscale x 8 x float> %r
@@ -343,10 +343,10 @@ define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, floa
; CHECK-LABEL: insertelt_nxv8f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
ret <vscale x 8 x float> %r
@@ -401,9 +401,9 @@ define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, do
; CHECK-LABEL: insertelt_nxv1f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
ret <vscale x 1 x double> %r
@@ -413,10 +413,10 @@ define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, do
; CHECK-LABEL: insertelt_nxv1f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
ret <vscale x 1 x double> %r
@@ -436,9 +436,9 @@ define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, do
; CHECK-LABEL: insertelt_nxv2f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 3
ret <vscale x 2 x double> %r
@@ -448,10 +448,10 @@ define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, do
; CHECK-LABEL: insertelt_nxv2f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
ret <vscale x 2 x double> %r
@@ -471,9 +471,9 @@ define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, do
; CHECK-LABEL: insertelt_nxv4f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 3
ret <vscale x 4 x double> %r
@@ -483,10 +483,10 @@ define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, do
; CHECK-LABEL: insertelt_nxv4f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
ret <vscale x 4 x double> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
index e76dc336941e2..992d298b2a859 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
@@ -16,9 +16,9 @@ define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %
; CHECK-LABEL: insertelt_nxv1f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
ret <vscale x 1 x half> %r
@@ -28,10 +28,10 @@ define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %
; CHECK-LABEL: insertelt_nxv1f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r
@@ -51,9 +51,9 @@ define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %
; CHECK-LABEL: insertelt_nxv2f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
ret <vscale x 2 x half> %r
@@ -63,10 +63,10 @@ define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %
; CHECK-LABEL: insertelt_nxv2f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r
@@ -86,9 +86,9 @@ define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %
; CHECK-LABEL: insertelt_nxv4f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
ret <vscale x 4 x half> %r
@@ -98,10 +98,10 @@ define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %
; CHECK-LABEL: insertelt_nxv4f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r
@@ -121,9 +121,9 @@ define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %
; CHECK-LABEL: insertelt_nxv8f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
ret <vscale x 8 x half> %r
@@ -133,10 +133,10 @@ define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %
; CHECK-LABEL: insertelt_nxv8f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r
@@ -156,9 +156,9 @@ define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, hal
; CHECK-LABEL: insertelt_nxv16f16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
ret <vscale x 16 x half> %r
@@ -168,10 +168,10 @@ define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, hal
; CHECK-LABEL: insertelt_nxv16f16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r
@@ -226,9 +226,9 @@ define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, floa
; CHECK-LABEL: insertelt_nxv1f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
ret <vscale x 1 x float> %r
@@ -238,10 +238,10 @@ define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, floa
; CHECK-LABEL: insertelt_nxv1f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
ret <vscale x 1 x float> %r
@@ -261,9 +261,9 @@ define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, floa
; CHECK-LABEL: insertelt_nxv2f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
ret <vscale x 2 x float> %r
@@ -273,10 +273,10 @@ define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, floa
; CHECK-LABEL: insertelt_nxv2f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
ret <vscale x 2 x float> %r
@@ -296,9 +296,9 @@ define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, floa
; CHECK-LABEL: insertelt_nxv4f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 3
ret <vscale x 4 x float> %r
@@ -308,10 +308,10 @@ define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, floa
; CHECK-LABEL: insertelt_nxv4f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
ret <vscale x 4 x float> %r
@@ -331,9 +331,9 @@ define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, floa
; CHECK-LABEL: insertelt_nxv8f32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 3
ret <vscale x 8 x float> %r
@@ -343,10 +343,10 @@ define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, floa
; CHECK-LABEL: insertelt_nxv8f32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
ret <vscale x 8 x float> %r
@@ -401,9 +401,9 @@ define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, do
; CHECK-LABEL: insertelt_nxv1f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
ret <vscale x 1 x double> %r
@@ -413,10 +413,10 @@ define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, do
; CHECK-LABEL: insertelt_nxv1f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
ret <vscale x 1 x double> %r
@@ -436,9 +436,9 @@ define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, do
; CHECK-LABEL: insertelt_nxv2f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 3
ret <vscale x 2 x double> %r
@@ -448,10 +448,10 @@ define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, do
; CHECK-LABEL: insertelt_nxv2f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.s.f v26, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
ret <vscale x 2 x double> %r
@@ -471,9 +471,9 @@ define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, do
; CHECK-LABEL: insertelt_nxv4f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 3
ret <vscale x 4 x double> %r
@@ -483,10 +483,10 @@ define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, do
; CHECK-LABEL: insertelt_nxv4f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.s.f v28, fa0
+; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
ret <vscale x 4 x double> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
index f9290c5abf0e4..cbe815d3b31bc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
@@ -6,14 +6,14 @@ define <vscale x 1 x i1> @insertelt_nxv1i1(<vscale x 1 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 2
+; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 2
ret <vscale x 1 x i1> %y
@@ -23,15 +23,15 @@ define <vscale x 1 x i1> @insertelt_idx_nxv1i1(<vscale x 1 x i1> %x, i1 %elt, i6
; CHECK-LABEL: insertelt_idx_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vx v26, v25, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 1 x i1> %y
@@ -41,14 +41,14 @@ define <vscale x 2 x i1> @insertelt_nxv2i1(<vscale x 2 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 2
+; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 2
ret <vscale x 2 x i1> %y
@@ -58,15 +58,15 @@ define <vscale x 2 x i1> @insertelt_idx_nxv2i1(<vscale x 2 x i1> %x, i1 %elt, i6
; CHECK-LABEL: insertelt_idx_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v26, v25, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 2 x i1> %y
@@ -76,14 +76,14 @@ define <vscale x 4 x i1> @insertelt_nxv4i1(<vscale x 4 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 2
+; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 2
ret <vscale x 4 x i1> %y
@@ -93,15 +93,15 @@ define <vscale x 4 x i1> @insertelt_idx_nxv4i1(<vscale x 4 x i1> %x, i1 %elt, i6
; CHECK-LABEL: insertelt_idx_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v26, v25, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 4 x i1> %y
@@ -111,14 +111,14 @@ define <vscale x 8 x i1> @insertelt_nxv8i1(<vscale x 8 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v26, v25, 2
+; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 2
ret <vscale x 8 x i1> %y
@@ -128,15 +128,15 @@ define <vscale x 8 x i1> @insertelt_idx_nxv8i1(<vscale x 8 x i1> %x, i1 %elt, i6
; CHECK-LABEL: insertelt_idx_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v26, v25, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 8 x i1> %y
@@ -146,14 +146,14 @@ define <vscale x 16 x i1> @insertelt_nxv16i1(<vscale x 16 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v28, v26, 2
+; CHECK-NEXT: vslideup.vi v10, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 16 x i1> %x, i1 %elt, i64 2
ret <vscale x 16 x i1> %y
@@ -163,15 +163,15 @@ define <vscale x 16 x i1> @insertelt_idx_nxv16i1(<vscale x 16 x i1> %x, i1 %elt,
; CHECK-LABEL: insertelt_idx_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v28, v26, a1
+; CHECK-NEXT: vslideup.vx v10, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 16 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 16 x i1> %y
@@ -181,14 +181,14 @@ define <vscale x 32 x i1> @insertelt_nxv32i1(<vscale x 32 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 2
+; CHECK-NEXT: vslideup.vi v12, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 32 x i1> %x, i1 %elt, i64 2
ret <vscale x 32 x i1> %y
@@ -198,15 +198,15 @@ define <vscale x 32 x i1> @insertelt_idx_nxv32i1(<vscale x 32 x i1> %x, i1 %elt,
; CHECK-LABEL: insertelt_idx_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a1
+; CHECK-NEXT: vslideup.vx v12, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <vscale x 32 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 32 x i1> %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
index bdc4f2e48d57a..e2db8c1ee3ecf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
@@ -16,9 +16,9 @@ define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv1i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
ret <vscale x 1 x i8> %r
@@ -28,10 +28,10 @@ define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv1i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r
@@ -51,9 +51,9 @@ define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv2i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
ret <vscale x 2 x i8> %r
@@ -63,10 +63,10 @@ define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv2i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r
@@ -86,9 +86,9 @@ define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv4i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
ret <vscale x 4 x i8> %r
@@ -98,10 +98,10 @@ define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv4i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r
@@ -121,9 +121,9 @@ define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv8i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
ret <vscale x 8 x i8> %r
@@ -133,10 +133,10 @@ define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv8i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r
@@ -156,9 +156,9 @@ define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv16i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
ret <vscale x 16 x i8> %r
@@ -168,10 +168,10 @@ define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv16i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a1
+; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 16 x i8> %r
@@ -191,9 +191,9 @@ define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv32i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
ret <vscale x 32 x i8> %r
@@ -203,10 +203,10 @@ define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv32i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 32 x i8> %r
@@ -261,9 +261,9 @@ define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv1i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
ret <vscale x 1 x i16> %r
@@ -273,10 +273,10 @@ define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv1i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r
@@ -296,9 +296,9 @@ define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv2i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
ret <vscale x 2 x i16> %r
@@ -308,10 +308,10 @@ define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv2i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r
@@ -331,9 +331,9 @@ define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv4i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
ret <vscale x 4 x i16> %r
@@ -343,10 +343,10 @@ define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv4i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r
@@ -366,9 +366,9 @@ define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv8i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
ret <vscale x 8 x i16> %r
@@ -378,10 +378,10 @@ define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv8i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a1
+; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 8 x i16> %r
@@ -401,9 +401,9 @@ define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 s
; CHECK-LABEL: insertelt_nxv16i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
ret <vscale x 16 x i16> %r
@@ -413,10 +413,10 @@ define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 s
; CHECK-LABEL: insertelt_nxv16i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 16 x i16> %r
@@ -471,9 +471,9 @@ define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv1i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
ret <vscale x 1 x i32> %r
@@ -483,10 +483,10 @@ define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv1i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r
@@ -506,9 +506,9 @@ define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv2i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
ret <vscale x 2 x i32> %r
@@ -518,10 +518,10 @@ define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv2i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r
@@ -541,9 +541,9 @@ define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv4i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
ret <vscale x 4 x i32> %r
@@ -553,10 +553,10 @@ define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv4i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a1
+; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 4 x i32> %r
@@ -576,9 +576,9 @@ define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv8i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
ret <vscale x 8 x i32> %r
@@ -588,10 +588,10 @@ define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %elt
; CHECK-LABEL: insertelt_nxv8i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 8 x i32> %r
@@ -636,11 +636,11 @@ define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt)
; CHECK-LABEL: insertelt_nxv1i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vslide1up.vx v26, v25, a1
-; CHECK-NEXT: vslide1up.vx v25, v26, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vslide1up.vx v10, v9, a1
+; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: vsetivli zero, 1, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 0
+; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
ret <vscale x 1 x i64> %r
@@ -650,11 +650,11 @@ define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv1i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vslide1up.vx v26, v25, a1
-; CHECK-NEXT: vslide1up.vx v25, v26, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vslide1up.vx v10, v9, a1
+; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
ret <vscale x 1 x i64> %r
@@ -664,12 +664,12 @@ define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv1i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vslide1up.vx v26, v25, a1
-; CHECK-NEXT: vslide1up.vx v25, v26, a0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vslide1up.vx v10, v9, a1
+; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: addi a0, a2, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a2
+; CHECK-NEXT: vslideup.vx v8, v9, a2
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 1 x i64> %r
@@ -679,11 +679,11 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt)
; CHECK-LABEL: insertelt_nxv2i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vslide1up.vx v28, v26, a1
-; CHECK-NEXT: vslide1up.vx v26, v28, a0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vslide1up.vx v12, v10, a1
+; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: vsetivli zero, 1, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 0
+; CHECK-NEXT: vslideup.vi v8, v10, 0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
ret <vscale x 2 x i64> %r
@@ -693,11 +693,11 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv2i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vslide1up.vx v28, v26, a1
-; CHECK-NEXT: vslide1up.vx v26, v28, a0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vslide1up.vx v12, v10, a1
+; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
ret <vscale x 2 x i64> %r
@@ -707,12 +707,12 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv2i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vslide1up.vx v28, v26, a1
-; CHECK-NEXT: vslide1up.vx v26, v28, a0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vslide1up.vx v12, v10, a1
+; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: addi a0, a2, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a2
+; CHECK-NEXT: vslideup.vx v8, v10, a2
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 2 x i64> %r
@@ -722,11 +722,11 @@ define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt)
; CHECK-LABEL: insertelt_nxv4i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vslide1up.vx v12, v28, a1
-; CHECK-NEXT: vslide1up.vx v28, v12, a0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vslide1up.vx v16, v12, a1
+; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: vsetivli zero, 1, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 0
+; CHECK-NEXT: vslideup.vi v8, v12, 0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
ret <vscale x 4 x i64> %r
@@ -736,11 +736,11 @@ define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv4i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vslide1up.vx v12, v28, a1
-; CHECK-NEXT: vslide1up.vx v28, v12, a0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vslide1up.vx v16, v12, a1
+; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
ret <vscale x 4 x i64> %r
@@ -750,12 +750,12 @@ define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv4i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vslide1up.vx v12, v28, a1
-; CHECK-NEXT: vslide1up.vx v28, v12, a0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vslide1up.vx v16, v12, a1
+; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: addi a0, a2, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a2
+; CHECK-NEXT: vslideup.vx v8, v12, a2
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 4 x i64> %r
@@ -821,9 +821,9 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_imm_c10(<vscale x 2 x i64> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 10
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 10, i32 3
ret <vscale x 2 x i64> %r
@@ -834,10 +834,10 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_idx_c10(<vscale x 2 x i64> %v, i32
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 10
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a1
+; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 10, i32 %idx
ret <vscale x 2 x i64> %r
@@ -859,9 +859,9 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_imm_cn1(<vscale x 2 x i64> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 3
ret <vscale x 2 x i64> %r
@@ -872,10 +872,10 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_idx_cn1(<vscale x 2 x i64> %v, i32
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, -1
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a1
+; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 %idx
ret <vscale x 2 x i64> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
index 8f07f9c1353f4..926aa8b09582b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
@@ -16,9 +16,9 @@ define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv1i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
ret <vscale x 1 x i8> %r
@@ -28,10 +28,10 @@ define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv1i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r
@@ -51,9 +51,9 @@ define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv2i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
ret <vscale x 2 x i8> %r
@@ -63,10 +63,10 @@ define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv2i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r
@@ -86,9 +86,9 @@ define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv4i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
ret <vscale x 4 x i8> %r
@@ -98,10 +98,10 @@ define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv4i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r
@@ -121,9 +121,9 @@ define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv8i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
ret <vscale x 8 x i8> %r
@@ -133,10 +133,10 @@ define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext
; CHECK-LABEL: insertelt_nxv8i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r
@@ -156,9 +156,9 @@ define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv16i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
ret <vscale x 16 x i8> %r
@@ -168,10 +168,10 @@ define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv16i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a1
+; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 16 x i8> %r
@@ -191,9 +191,9 @@ define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv32i8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
ret <vscale x 32 x i8> %r
@@ -203,10 +203,10 @@ define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signe
; CHECK-LABEL: insertelt_nxv32i8_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 32 x i8> %r
@@ -261,9 +261,9 @@ define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv1i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
ret <vscale x 1 x i16> %r
@@ -273,10 +273,10 @@ define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv1i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r
@@ -296,9 +296,9 @@ define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv2i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
ret <vscale x 2 x i16> %r
@@ -308,10 +308,10 @@ define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv2i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r
@@ -331,9 +331,9 @@ define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv4i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
ret <vscale x 4 x i16> %r
@@ -343,10 +343,10 @@ define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv4i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r
@@ -366,9 +366,9 @@ define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv8i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
ret <vscale x 8 x i16> %r
@@ -378,10 +378,10 @@ define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 sign
; CHECK-LABEL: insertelt_nxv8i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a1
+; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 8 x i16> %r
@@ -401,9 +401,9 @@ define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 s
; CHECK-LABEL: insertelt_nxv16i16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
ret <vscale x 16 x i16> %r
@@ -413,10 +413,10 @@ define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 s
; CHECK-LABEL: insertelt_nxv16i16_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 16 x i16> %r
@@ -471,9 +471,9 @@ define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv1i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
ret <vscale x 1 x i32> %r
@@ -483,10 +483,10 @@ define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv1i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r
@@ -506,9 +506,9 @@ define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv2i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
ret <vscale x 2 x i32> %r
@@ -518,10 +518,10 @@ define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv2i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r
@@ -541,9 +541,9 @@ define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv4i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
ret <vscale x 4 x i32> %r
@@ -553,10 +553,10 @@ define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv4i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a1
+; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 4 x i32> %r
@@ -576,9 +576,9 @@ define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv8i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
ret <vscale x 8 x i32> %r
@@ -588,10 +588,10 @@ define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 sign
; CHECK-LABEL: insertelt_nxv8i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 8 x i32> %r
@@ -646,9 +646,9 @@ define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv1i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v25, 3
+; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
ret <vscale x 1 x i64> %r
@@ -658,11 +658,11 @@ define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv1i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: sext.w a0, a1
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v25, a0
+; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 1 x i64> %r
@@ -682,9 +682,9 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv2i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v26, 3
+; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
ret <vscale x 2 x i64> %r
@@ -694,11 +694,11 @@ define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv2i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.s.x v26, a0
+; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: sext.w a0, a1
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v26, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 2 x i64> %r
@@ -718,9 +718,9 @@ define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv4i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vi v8, v28, 3
+; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
ret <vscale x 4 x i64> %r
@@ -730,11 +730,11 @@ define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt
; CHECK-LABEL: insertelt_nxv4i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v28, a0
+; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: sext.w a0, a1
; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; CHECK-NEXT: vslideup.vx v8, v28, a0
+; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 4 x i64> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll b/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
index 7106d797965a6..c696f5106fa47 100644
--- a/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
@@ -7,28 +7,28 @@ define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16
; RV64-1024: # %bb.0: # %entry
; RV64-1024-NEXT: addi a3, zero, 128
; RV64-1024-NEXT: vsetvli zero, a3, e16, m2, ta, mu
-; RV64-1024-NEXT: vle16.v v8, (a1)
-; RV64-1024-NEXT: vle16.v v12, (a2)
+; RV64-1024-NEXT: vle16.v v12, (a1)
+; RV64-1024-NEXT: vle16.v v16, (a2)
; RV64-1024-NEXT: addi a1, zero, 256
; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-1024-NEXT: vmv.v.i v28, 0
+; RV64-1024-NEXT: vmv.v.i v8, 0
; RV64-1024-NEXT: vsetvli zero, a3, e16, m4, tu, mu
-; RV64-1024-NEXT: vmv4r.v v16, v28
-; RV64-1024-NEXT: vslideup.vi v16, v8, 0
+; RV64-1024-NEXT: vmv4r.v v20, v8
+; RV64-1024-NEXT: vslideup.vi v20, v12, 0
; RV64-1024-NEXT: vsetvli zero, a3, e16, m2, ta, mu
-; RV64-1024-NEXT: vmv.v.i v20, 0
+; RV64-1024-NEXT: vmv.v.i v24, 0
; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, tu, mu
-; RV64-1024-NEXT: vslideup.vx v16, v20, a3
+; RV64-1024-NEXT: vslideup.vx v20, v24, a3
; RV64-1024-NEXT: vsetvli zero, zero, e16, m4, ta, mu
-; RV64-1024-NEXT: vid.v v24
-; RV64-1024-NEXT: vsrl.vi v8, v24, 1
-; RV64-1024-NEXT: vrgather.vv v0, v16, v8
+; RV64-1024-NEXT: vid.v v28
+; RV64-1024-NEXT: vsrl.vi v12, v28, 1
+; RV64-1024-NEXT: vrgather.vv v0, v20, v12
; RV64-1024-NEXT: vsetvli zero, a3, e16, m4, tu, mu
-; RV64-1024-NEXT: vslideup.vi v28, v12, 0
+; RV64-1024-NEXT: vslideup.vi v8, v16, 0
; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, tu, mu
-; RV64-1024-NEXT: vslideup.vx v28, v20, a3
+; RV64-1024-NEXT: vslideup.vx v8, v24, a3
; RV64-1024-NEXT: vsetvli zero, zero, e16, m4, ta, mu
-; RV64-1024-NEXT: vrgather.vv v12, v0, v24
+; RV64-1024-NEXT: vrgather.vv v16, v0, v28
; RV64-1024-NEXT: lui a2, 1026731
; RV64-1024-NEXT: addiw a2, a2, -1365
; RV64-1024-NEXT: slli a2, a2, 12
@@ -38,45 +38,45 @@ define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16
; RV64-1024-NEXT: slli a2, a2, 12
; RV64-1024-NEXT: addi a2, a2, -1366
; RV64-1024-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; RV64-1024-NEXT: vmv.s.x v25, a2
+; RV64-1024-NEXT: vmv.s.x v20, a2
; RV64-1024-NEXT: vsetivli zero, 2, e64, m1, tu, mu
-; RV64-1024-NEXT: vmv1r.v v0, v25
-; RV64-1024-NEXT: vslideup.vi v0, v25, 1
+; RV64-1024-NEXT: vmv1r.v v0, v20
+; RV64-1024-NEXT: vslideup.vi v0, v20, 1
; RV64-1024-NEXT: vsetivli zero, 3, e64, m1, tu, mu
-; RV64-1024-NEXT: vslideup.vi v0, v25, 2
+; RV64-1024-NEXT: vslideup.vi v0, v20, 2
; RV64-1024-NEXT: vsetivli zero, 4, e64, m1, tu, mu
-; RV64-1024-NEXT: vslideup.vi v0, v25, 3
+; RV64-1024-NEXT: vslideup.vi v0, v20, 3
; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-1024-NEXT: vrgather.vv v12, v28, v8, v0.t
-; RV64-1024-NEXT: vse16.v v12, (a0)
+; RV64-1024-NEXT: vrgather.vv v16, v8, v12, v0.t
+; RV64-1024-NEXT: vse16.v v16, (a0)
; RV64-1024-NEXT: ret
;
; RV64-2048-LABEL: interleave256:
; RV64-2048: # %bb.0: # %entry
; RV64-2048-NEXT: addi a3, zero, 128
; RV64-2048-NEXT: vsetvli zero, a3, e16, m1, ta, mu
-; RV64-2048-NEXT: vle16.v v28, (a1)
-; RV64-2048-NEXT: vle16.v v30, (a2)
+; RV64-2048-NEXT: vle16.v v10, (a1)
+; RV64-2048-NEXT: vle16.v v12, (a2)
; RV64-2048-NEXT: addi a1, zero, 256
; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV64-2048-NEXT: vmv.v.i v26, 0
+; RV64-2048-NEXT: vmv.v.i v8, 0
; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, tu, mu
-; RV64-2048-NEXT: vmv2r.v v8, v26
-; RV64-2048-NEXT: vslideup.vi v8, v28, 0
+; RV64-2048-NEXT: vmv2r.v v14, v8
+; RV64-2048-NEXT: vslideup.vi v14, v10, 0
; RV64-2048-NEXT: vsetvli zero, a3, e16, m1, ta, mu
-; RV64-2048-NEXT: vmv.v.i v10, 0
+; RV64-2048-NEXT: vmv.v.i v16, 0
; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, tu, mu
-; RV64-2048-NEXT: vslideup.vx v8, v10, a3
+; RV64-2048-NEXT: vslideup.vx v14, v16, a3
; RV64-2048-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV64-2048-NEXT: vid.v v12
-; RV64-2048-NEXT: vsrl.vi v28, v12, 1
-; RV64-2048-NEXT: vrgather.vv v14, v8, v28
+; RV64-2048-NEXT: vid.v v18
+; RV64-2048-NEXT: vsrl.vi v10, v18, 1
+; RV64-2048-NEXT: vrgather.vv v20, v14, v10
; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, tu, mu
-; RV64-2048-NEXT: vslideup.vi v26, v30, 0
+; RV64-2048-NEXT: vslideup.vi v8, v12, 0
; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, tu, mu
-; RV64-2048-NEXT: vslideup.vx v26, v10, a3
+; RV64-2048-NEXT: vslideup.vx v8, v16, a3
; RV64-2048-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV64-2048-NEXT: vrgather.vv v30, v14, v12
+; RV64-2048-NEXT: vrgather.vv v12, v20, v18
; RV64-2048-NEXT: lui a2, 1026731
; RV64-2048-NEXT: addiw a2, a2, -1365
; RV64-2048-NEXT: slli a2, a2, 12
@@ -86,17 +86,17 @@ define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16
; RV64-2048-NEXT: slli a2, a2, 12
; RV64-2048-NEXT: addi a2, a2, -1366
; RV64-2048-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; RV64-2048-NEXT: vmv.s.x v25, a2
+; RV64-2048-NEXT: vmv.s.x v14, a2
; RV64-2048-NEXT: vsetivli zero, 2, e64, m1, tu, mu
-; RV64-2048-NEXT: vmv1r.v v0, v25
-; RV64-2048-NEXT: vslideup.vi v0, v25, 1
+; RV64-2048-NEXT: vmv1r.v v0, v14
+; RV64-2048-NEXT: vslideup.vi v0, v14, 1
; RV64-2048-NEXT: vsetivli zero, 3, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 2
+; RV64-2048-NEXT: vslideup.vi v0, v14, 2
; RV64-2048-NEXT: vsetivli zero, 4, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 3
+; RV64-2048-NEXT: vslideup.vi v0, v14, 3
; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV64-2048-NEXT: vrgather.vv v30, v26, v28, v0.t
-; RV64-2048-NEXT: vse16.v v30, (a0)
+; RV64-2048-NEXT: vrgather.vv v12, v8, v10, v0.t
+; RV64-2048-NEXT: vse16.v v12, (a0)
; RV64-2048-NEXT: ret
entry:
%ve = load <128 x i16>, <128 x i16>* %0, align 256
@@ -235,28 +235,28 @@ define void @interleave512(<512 x i16>* %agg.result, <256 x i16>* %0, <256 x i16
; RV64-2048: # %bb.0: # %entry
; RV64-2048-NEXT: addi a3, zero, 256
; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, ta, mu
-; RV64-2048-NEXT: vle16.v v8, (a1)
-; RV64-2048-NEXT: vle16.v v12, (a2)
+; RV64-2048-NEXT: vle16.v v12, (a1)
+; RV64-2048-NEXT: vle16.v v16, (a2)
; RV64-2048-NEXT: addi a1, zero, 512
; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-2048-NEXT: vmv.v.i v28, 0
+; RV64-2048-NEXT: vmv.v.i v8, 0
; RV64-2048-NEXT: vsetvli zero, a3, e16, m4, tu, mu
-; RV64-2048-NEXT: vmv4r.v v16, v28
-; RV64-2048-NEXT: vslideup.vi v16, v8, 0
+; RV64-2048-NEXT: vmv4r.v v20, v8
+; RV64-2048-NEXT: vslideup.vi v20, v12, 0
; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, ta, mu
-; RV64-2048-NEXT: vmv.v.i v20, 0
+; RV64-2048-NEXT: vmv.v.i v24, 0
; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, tu, mu
-; RV64-2048-NEXT: vslideup.vx v16, v20, a3
+; RV64-2048-NEXT: vslideup.vx v20, v24, a3
; RV64-2048-NEXT: vsetvli zero, zero, e16, m4, ta, mu
-; RV64-2048-NEXT: vid.v v24
-; RV64-2048-NEXT: vsrl.vi v8, v24, 1
-; RV64-2048-NEXT: vrgather.vv v0, v16, v8
+; RV64-2048-NEXT: vid.v v28
+; RV64-2048-NEXT: vsrl.vi v12, v28, 1
+; RV64-2048-NEXT: vrgather.vv v0, v20, v12
; RV64-2048-NEXT: vsetvli zero, a3, e16, m4, tu, mu
-; RV64-2048-NEXT: vslideup.vi v28, v12, 0
+; RV64-2048-NEXT: vslideup.vi v8, v16, 0
; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, tu, mu
-; RV64-2048-NEXT: vslideup.vx v28, v20, a3
+; RV64-2048-NEXT: vslideup.vx v8, v24, a3
; RV64-2048-NEXT: vsetvli zero, zero, e16, m4, ta, mu
-; RV64-2048-NEXT: vrgather.vv v12, v0, v24
+; RV64-2048-NEXT: vrgather.vv v16, v0, v28
; RV64-2048-NEXT: lui a2, 1026731
; RV64-2048-NEXT: addiw a2, a2, -1365
; RV64-2048-NEXT: slli a2, a2, 12
@@ -266,25 +266,25 @@ define void @interleave512(<512 x i16>* %agg.result, <256 x i16>* %0, <256 x i16
; RV64-2048-NEXT: slli a2, a2, 12
; RV64-2048-NEXT: addi a2, a2, -1366
; RV64-2048-NEXT: vsetivli zero, 8, e64, m1, ta, mu
-; RV64-2048-NEXT: vmv.s.x v25, a2
+; RV64-2048-NEXT: vmv.s.x v20, a2
; RV64-2048-NEXT: vsetivli zero, 2, e64, m1, tu, mu
-; RV64-2048-NEXT: vmv1r.v v0, v25
-; RV64-2048-NEXT: vslideup.vi v0, v25, 1
+; RV64-2048-NEXT: vmv1r.v v0, v20
+; RV64-2048-NEXT: vslideup.vi v0, v20, 1
; RV64-2048-NEXT: vsetivli zero, 3, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 2
+; RV64-2048-NEXT: vslideup.vi v0, v20, 2
; RV64-2048-NEXT: vsetivli zero, 4, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 3
+; RV64-2048-NEXT: vslideup.vi v0, v20, 3
; RV64-2048-NEXT: vsetivli zero, 5, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 4
+; RV64-2048-NEXT: vslideup.vi v0, v20, 4
; RV64-2048-NEXT: vsetivli zero, 6, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 5
+; RV64-2048-NEXT: vslideup.vi v0, v20, 5
; RV64-2048-NEXT: vsetivli zero, 7, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 6
+; RV64-2048-NEXT: vslideup.vi v0, v20, 6
; RV64-2048-NEXT: vsetivli zero, 8, e64, m1, tu, mu
-; RV64-2048-NEXT: vslideup.vi v0, v25, 7
+; RV64-2048-NEXT: vslideup.vi v0, v20, 7
; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; RV64-2048-NEXT: vrgather.vv v12, v28, v8, v0.t
-; RV64-2048-NEXT: vse16.v v12, (a0)
+; RV64-2048-NEXT: vrgather.vv v16, v8, v12, v0.t
+; RV64-2048-NEXT: vse16.v v16, (a0)
; RV64-2048-NEXT: ret
entry:
%ve = load <256 x i16>, <256 x i16>* %0, align 512
diff --git a/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll b/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
index 466b9031f71bd..46e1c0a4d8a5a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
@@ -6,9 +6,9 @@ define <vscale x 4 x i5> @trunc_nxv4i32_to_nxv4i5(<vscale x 4 x i32> %a) {
; CHECK-LABEL: trunc_nxv4i32_to_nxv4i5:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%v = trunc <vscale x 4 x i32> %a to <vscale x 4 x i5>
ret <vscale x 4 x i5> %v
@@ -18,9 +18,9 @@ define <vscale x 1 x i5> @trunc_nxv1i32_to_nxv1i5(<vscale x 1 x i32> %a) {
; CHECK-LABEL: trunc_nxv1i32_to_nxv1i5:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v = trunc <vscale x 1 x i32> %a to <vscale x 1 x i5>
ret <vscale x 1 x i5> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
index 7f5986137eeee..4d0cf0fae6100 100644
--- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
@@ -7,11 +7,11 @@
define void @vadd_vint16m1(<vscale x 4 x i16> *%pc, <vscale x 4 x i16> *%pa, <vscale x 4 x i16> *%pb) nounwind {
; CHECK-LABEL: vadd_vint16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v25, (a1)
-; CHECK-NEXT: vl1re16.v v26, (a2)
+; CHECK-NEXT: vl1re16.v v8, (a1)
+; CHECK-NEXT: vl1re16.v v9, (a2)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pa
%vb = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pb
@@ -23,11 +23,11 @@ define void @vadd_vint16m1(<vscale x 4 x i16> *%pc, <vscale x 4 x i16> *%pa, <vs
define void @vadd_vint16m2(<vscale x 8 x i16> *%pc, <vscale x 8 x i16> *%pa, <vscale x 8 x i16> *%pb) nounwind {
; CHECK-LABEL: vadd_vint16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v26, (a1)
-; CHECK-NEXT: vl2re16.v v28, (a2)
+; CHECK-NEXT: vl2re16.v v8, (a1)
+; CHECK-NEXT: vl2re16.v v10, (a2)
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vv v26, v26, v28
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pa
%vb = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pb
@@ -39,11 +39,11 @@ define void @vadd_vint16m2(<vscale x 8 x i16> *%pc, <vscale x 8 x i16> *%pa, <vs
define void @vadd_vint16m4(<vscale x 16 x i16> *%pc, <vscale x 16 x i16> *%pa, <vscale x 16 x i16> *%pb) nounwind {
; CHECK-LABEL: vadd_vint16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v28, (a1)
-; CHECK-NEXT: vl4re16.v v8, (a2)
+; CHECK-NEXT: vl4re16.v v8, (a1)
+; CHECK-NEXT: vl4re16.v v12, (a2)
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vv v28, v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pa
%vb = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pb
@@ -72,10 +72,10 @@ define void @vadd_vint16mf2(<vscale x 2 x i16> *%pc, <vscale x 2 x i16> *%pa, <v
; CHECK-LABEL: vadd_vint16mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vle16.v v26, (a2)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 2 x i16>, <vscale x 2 x i16>* %pa
%vb = load <vscale x 2 x i16>, <vscale x 2 x i16>* %pb
@@ -88,10 +88,10 @@ define void @vadd_vint16mf4(<vscale x 1 x i16> *%pc, <vscale x 1 x i16> *%pa, <v
; CHECK-LABEL: vadd_vint16mf4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vle16.v v25, (a1)
-; CHECK-NEXT: vle16.v v26, (a2)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse16.v v25, (a0)
+; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 1 x i16>, <vscale x 1 x i16>* %pa
%vb = load <vscale x 1 x i16>, <vscale x 1 x i16>* %pb
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
index 94907718bfaf2..73874e2782c16 100644
--- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
@@ -7,11 +7,11 @@
define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vscale x 2 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re32.v v25, (a1)
-; CHECK-NEXT: vl1re32.v v26, (a2)
+; CHECK-NEXT: vl1re32.v v8, (a1)
+; CHECK-NEXT: vl1re32.v v9, (a2)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pa
%vb = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pb
@@ -23,11 +23,11 @@ define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vs
define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vscale x 4 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re32.v v26, (a1)
-; CHECK-NEXT: vl2re32.v v28, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a1)
+; CHECK-NEXT: vl2re32.v v10, (a2)
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vv v26, v26, v28
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pa
%vb = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pb
@@ -39,11 +39,11 @@ define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vs
define void @vadd_vint32m4(<vscale x 8 x i32> *%pc, <vscale x 8 x i32> *%pa, <vscale x 8 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re32.v v28, (a1)
-; CHECK-NEXT: vl4re32.v v8, (a2)
+; CHECK-NEXT: vl4re32.v v8, (a1)
+; CHECK-NEXT: vl4re32.v v12, (a2)
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vv v28, v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pa
%vb = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pb
@@ -72,10 +72,10 @@ define void @vadd_vint32mf2(<vscale x 1 x i32> *%pc, <vscale x 1 x i32> *%pa, <v
; CHECK-LABEL: vadd_vint32mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vle32.v v25, (a1)
-; CHECK-NEXT: vle32.v v26, (a2)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vle32.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 1 x i32>, <vscale x 1 x i32>* %pa
%vb = load <vscale x 1 x i32>, <vscale x 1 x i32>* %pb
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
index ec41245aca746..4edad9c1742e3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
@@ -7,11 +7,11 @@
define void @vadd_vint64m1(<vscale x 1 x i64> *%pc, <vscale x 1 x i64> *%pa, <vscale x 1 x i64> *%pb) nounwind {
; CHECK-LABEL: vadd_vint64m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re64.v v25, (a1)
-; CHECK-NEXT: vl1re64.v v26, (a2)
+; CHECK-NEXT: vl1re64.v v8, (a1)
+; CHECK-NEXT: vl1re64.v v9, (a2)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pa
%vb = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pb
@@ -23,11 +23,11 @@ define void @vadd_vint64m1(<vscale x 1 x i64> *%pc, <vscale x 1 x i64> *%pa, <vs
define void @vadd_vint64m2(<vscale x 2 x i64> *%pc, <vscale x 2 x i64> *%pa, <vscale x 2 x i64> *%pb) nounwind {
; CHECK-LABEL: vadd_vint64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re64.v v26, (a1)
-; CHECK-NEXT: vl2re64.v v28, (a2)
+; CHECK-NEXT: vl2re64.v v8, (a1)
+; CHECK-NEXT: vl2re64.v v10, (a2)
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vv v26, v26, v28
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pa
%vb = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pb
@@ -39,11 +39,11 @@ define void @vadd_vint64m2(<vscale x 2 x i64> *%pc, <vscale x 2 x i64> *%pa, <vs
define void @vadd_vint64m4(<vscale x 4 x i64> *%pc, <vscale x 4 x i64> *%pa, <vscale x 4 x i64> *%pb) nounwind {
; CHECK-LABEL: vadd_vint64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re64.v v28, (a1)
-; CHECK-NEXT: vl4re64.v v8, (a2)
+; CHECK-NEXT: vl4re64.v v8, (a1)
+; CHECK-NEXT: vl4re64.v v12, (a2)
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vv v28, v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pa
%vb = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pb
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
index 2c3e97f1c11ec..793c2dc8cdcb5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
@@ -7,11 +7,11 @@
define void @vadd_vint8m1(<vscale x 8 x i8> *%pc, <vscale x 8 x i8> *%pa, <vscale x 8 x i8> *%pb) nounwind {
; CHECK-LABEL: vadd_vint8m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1r.v v25, (a1)
-; CHECK-NEXT: vl1r.v v26, (a2)
+; CHECK-NEXT: vl1r.v v8, (a1)
+; CHECK-NEXT: vl1r.v v9, (a2)
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vs1r.v v25, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 8 x i8>, <vscale x 8 x i8>* %pa
%vb = load <vscale x 8 x i8>, <vscale x 8 x i8>* %pb
@@ -23,11 +23,11 @@ define void @vadd_vint8m1(<vscale x 8 x i8> *%pc, <vscale x 8 x i8> *%pa, <vscal
define void @vadd_vint8m2(<vscale x 16 x i8> *%pc, <vscale x 16 x i8> *%pa, <vscale x 16 x i8> *%pb) nounwind {
; CHECK-LABEL: vadd_vint8m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2r.v v26, (a1)
-; CHECK-NEXT: vl2r.v v28, (a2)
+; CHECK-NEXT: vl2r.v v8, (a1)
+; CHECK-NEXT: vl2r.v v10, (a2)
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vv v26, v26, v28
-; CHECK-NEXT: vs2r.v v26, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 16 x i8>, <vscale x 16 x i8>* %pa
%vb = load <vscale x 16 x i8>, <vscale x 16 x i8>* %pb
@@ -39,11 +39,11 @@ define void @vadd_vint8m2(<vscale x 16 x i8> *%pc, <vscale x 16 x i8> *%pa, <vsc
define void @vadd_vint8m4(<vscale x 32 x i8> *%pc, <vscale x 32 x i8> *%pa, <vscale x 32 x i8> *%pb) nounwind {
; CHECK-LABEL: vadd_vint8m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4r.v v28, (a1)
-; CHECK-NEXT: vl4r.v v8, (a2)
+; CHECK-NEXT: vl4r.v v8, (a1)
+; CHECK-NEXT: vl4r.v v12, (a2)
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vv v28, v28, v8
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 32 x i8>, <vscale x 32 x i8>* %pa
%vb = load <vscale x 32 x i8>, <vscale x 32 x i8>* %pb
@@ -72,10 +72,10 @@ define void @vadd_vint8mf2(<vscale x 4 x i8> *%pc, <vscale x 4 x i8> *%pa, <vsca
; CHECK-LABEL: vadd_vint8mf2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vle8.v v26, (a2)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 4 x i8>, <vscale x 4 x i8>* %pa
%vb = load <vscale x 4 x i8>, <vscale x 4 x i8>* %pb
@@ -88,10 +88,10 @@ define void @vadd_vint8mf4(<vscale x 2 x i8> *%pc, <vscale x 2 x i8> *%pa, <vsca
; CHECK-LABEL: vadd_vint8mf4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vle8.v v26, (a2)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 2 x i8>, <vscale x 2 x i8>* %pa
%vb = load <vscale x 2 x i8>, <vscale x 2 x i8>* %pb
@@ -104,10 +104,10 @@ define void @vadd_vint8mf8(<vscale x 1 x i8> *%pc, <vscale x 1 x i8> *%pa, <vsca
; CHECK-LABEL: vadd_vint8mf8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle8.v v25, (a1)
-; CHECK-NEXT: vle8.v v26, (a2)
-; CHECK-NEXT: vadd.vv v25, v25, v26
-; CHECK-NEXT: vse8.v v25, (a0)
+; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vle8.v v9, (a2)
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%va = load <vscale x 1 x i8>, <vscale x 1 x i8>* %pa
%vb = load <vscale x 1 x i8>, <vscale x 1 x i8>* %pb
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
index 34a3952730426..4026061158943 100644
--- a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
@@ -8,8 +8,8 @@ define void @test_load_mask_64(<vscale x 64 x i1>* %pa, <vscale x 64 x i1>* %pb)
; CHECK-LABEL: test_load_mask_64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 64 x i1>, <vscale x 64 x i1>* %pa
store <vscale x 64 x i1> %a, <vscale x 64 x i1>* %pb
@@ -20,8 +20,8 @@ define void @test_load_mask_32(<vscale x 32 x i1>* %pa, <vscale x 32 x i1>* %pb)
; CHECK-LABEL: test_load_mask_32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 32 x i1>, <vscale x 32 x i1>* %pa
store <vscale x 32 x i1> %a, <vscale x 32 x i1>* %pb
@@ -32,8 +32,8 @@ define void @test_load_mask_16(<vscale x 16 x i1>* %pa, <vscale x 16 x i1>* %pb)
; CHECK-LABEL: test_load_mask_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 16 x i1>, <vscale x 16 x i1>* %pa
store <vscale x 16 x i1> %a, <vscale x 16 x i1>* %pb
@@ -44,8 +44,8 @@ define void @test_load_mask_8(<vscale x 8 x i1>* %pa, <vscale x 8 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 8 x i1>, <vscale x 8 x i1>* %pa
store <vscale x 8 x i1> %a, <vscale x 8 x i1>* %pb
@@ -56,8 +56,8 @@ define void @test_load_mask_4(<vscale x 4 x i1>* %pa, <vscale x 4 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 4 x i1>, <vscale x 4 x i1>* %pa
store <vscale x 4 x i1> %a, <vscale x 4 x i1>* %pb
@@ -68,8 +68,8 @@ define void @test_load_mask_2(<vscale x 2 x i1>* %pa, <vscale x 2 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 2 x i1>, <vscale x 2 x i1>* %pa
store <vscale x 2 x i1> %a, <vscale x 2 x i1>* %pb
@@ -80,8 +80,8 @@ define void @test_load_mask_1(<vscale x 1 x i1>* %pa, <vscale x 1 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vsm.v v25, (a1)
+; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 1 x i1>, <vscale x 1 x i1>* %pa
store <vscale x 1 x i1> %a, <vscale x 1 x i1>* %pb
diff --git a/llvm/test/CodeGen/RISCV/rvv/localvar.ll b/llvm/test/CodeGen/RISCV/rvv/localvar.ll
index cec21d727da9c..741db4f0e4df7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/localvar.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/localvar.ll
@@ -14,9 +14,9 @@ define void @local_var_mf8() {
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16
-; RV64IV-NEXT: vle8.v v25, (a0)
+; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16
-; RV64IV-NEXT: vle8.v v25, (a0)
+; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add sp, sp, a0
@@ -40,9 +40,9 @@ define void @local_var_m1() {
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16
-; RV64IV-NEXT: vl1r.v v25, (a0)
+; RV64IV-NEXT: vl1r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16
-; RV64IV-NEXT: vl1r.v v25, (a0)
+; RV64IV-NEXT: vl1r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add sp, sp, a0
@@ -67,9 +67,9 @@ define void @local_var_m2() {
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add sp, sp, a0
@@ -101,9 +101,9 @@ define void @local_var_m4() {
; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16
-; RV64IV-NEXT: vl4r.v v28, (a0)
+; RV64IV-NEXT: vl4r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16
-; RV64IV-NEXT: vl4r.v v28, (a0)
+; RV64IV-NEXT: vl4r.v v8, (a0)
; RV64IV-NEXT: addi sp, s0, -32
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -163,9 +163,9 @@ define void @local_var_m2_mix_local_scalar() {
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 32
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 32
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: lw a0, 24(sp)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2
@@ -210,12 +210,12 @@ define void @local_var_m2_with_varsize_object(i64 %n) {
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub a0, s0, a0
; RV64IV-NEXT: addi a0, a0, -32
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub a0, s0, a0
; RV64IV-NEXT: addi a0, a0, -32
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi sp, s0, -32
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -263,9 +263,9 @@ define void @local_var_m2_with_bp(i64 %n) {
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, s1, a0
; RV64IV-NEXT: addi a0, a0, 232
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, s1, 232
-; RV64IV-NEXT: vl2r.v v26, (a0)
+; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: lw a0, 120(s1)
; RV64IV-NEXT: addi sp, s0, -256
; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll
index fbb084c2a19a1..886f2c32b66ca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll
@@ -5,8 +5,8 @@ define <vscale x 1 x i8> @sext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i8>
ret <vscale x 1 x i8> %r
@@ -16,8 +16,8 @@ define <vscale x 1 x i8> @zext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i8>
ret <vscale x 1 x i8> %r
@@ -27,8 +27,8 @@ define <vscale x 1 x i1> @trunc_nxv1i8_nxv1i1(<vscale x 1 x i8> %v) {
; CHECK-LABEL: trunc_nxv1i8_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i8> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -38,8 +38,8 @@ define <vscale x 2 x i8> @sext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i8>
ret <vscale x 2 x i8> %r
@@ -49,8 +49,8 @@ define <vscale x 2 x i8> @zext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i8>
ret <vscale x 2 x i8> %r
@@ -60,8 +60,8 @@ define <vscale x 2 x i1> @trunc_nxv2i8_nxv2i1(<vscale x 2 x i8> %v) {
; CHECK-LABEL: trunc_nxv2i8_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i8> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -71,8 +71,8 @@ define <vscale x 4 x i8> @sext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i8>
ret <vscale x 4 x i8> %r
@@ -82,8 +82,8 @@ define <vscale x 4 x i8> @zext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i8>
ret <vscale x 4 x i8> %r
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @trunc_nxv4i8_nxv4i1(<vscale x 4 x i8> %v) {
; CHECK-LABEL: trunc_nxv4i8_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i8> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
@@ -104,8 +104,8 @@ define <vscale x 8 x i8> @sext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
; CHECK-LABEL: sext_nxv8i1_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
ret <vscale x 8 x i8> %r
@@ -115,8 +115,8 @@ define <vscale x 8 x i8> @zext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
; CHECK-LABEL: zext_nxv8i1_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
ret <vscale x 8 x i8> %r
@@ -126,8 +126,8 @@ define <vscale x 8 x i1> @trunc_nxv8i8_nxv8i1(<vscale x 8 x i8> %v) {
; CHECK-LABEL: trunc_nxv8i8_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 8 x i8> %v to <vscale x 8 x i1>
ret <vscale x 8 x i1> %r
@@ -137,8 +137,8 @@ define <vscale x 16 x i8> @sext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
; CHECK-LABEL: sext_nxv16i1_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
ret <vscale x 16 x i8> %r
@@ -148,8 +148,8 @@ define <vscale x 16 x i8> @zext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
; CHECK-LABEL: zext_nxv16i1_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
ret <vscale x 16 x i8> %r
@@ -159,8 +159,8 @@ define <vscale x 16 x i1> @trunc_nxv16i8_nxv16i1(<vscale x 16 x i8> %v) {
; CHECK-LABEL: trunc_nxv16i8_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 16 x i8> %v to <vscale x 16 x i1>
ret <vscale x 16 x i1> %r
@@ -170,8 +170,8 @@ define <vscale x 32 x i8> @sext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
; CHECK-LABEL: sext_nxv32i1_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 32 x i1> %v to <vscale x 32 x i8>
ret <vscale x 32 x i8> %r
@@ -181,8 +181,8 @@ define <vscale x 32 x i8> @zext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
; CHECK-LABEL: zext_nxv32i1_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 32 x i1> %v to <vscale x 32 x i8>
ret <vscale x 32 x i8> %r
@@ -192,8 +192,8 @@ define <vscale x 32 x i1> @trunc_nxv32i8_nxv32i1(<vscale x 32 x i8> %v) {
; CHECK-LABEL: trunc_nxv32i8_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 32 x i8> %v to <vscale x 32 x i1>
ret <vscale x 32 x i1> %r
@@ -236,8 +236,8 @@ define <vscale x 1 x i16> @sext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i16>
ret <vscale x 1 x i16> %r
@@ -247,8 +247,8 @@ define <vscale x 1 x i16> @zext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i16>
ret <vscale x 1 x i16> %r
@@ -258,8 +258,8 @@ define <vscale x 1 x i1> @trunc_nxv1i16_nxv1i1(<vscale x 1 x i16> %v) {
; CHECK-LABEL: trunc_nxv1i16_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i16> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -269,8 +269,8 @@ define <vscale x 2 x i16> @sext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i16>
ret <vscale x 2 x i16> %r
@@ -280,8 +280,8 @@ define <vscale x 2 x i16> @zext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i16>
ret <vscale x 2 x i16> %r
@@ -291,8 +291,8 @@ define <vscale x 2 x i1> @trunc_nxv2i16_nxv2i1(<vscale x 2 x i16> %v) {
; CHECK-LABEL: trunc_nxv2i16_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i16> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -302,8 +302,8 @@ define <vscale x 4 x i16> @sext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
ret <vscale x 4 x i16> %r
@@ -313,8 +313,8 @@ define <vscale x 4 x i16> @zext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
ret <vscale x 4 x i16> %r
@@ -324,8 +324,8 @@ define <vscale x 4 x i1> @trunc_nxv4i16_nxv4i1(<vscale x 4 x i16> %v) {
; CHECK-LABEL: trunc_nxv4i16_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i16> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
@@ -335,8 +335,8 @@ define <vscale x 8 x i16> @sext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
; CHECK-LABEL: sext_nxv8i1_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
ret <vscale x 8 x i16> %r
@@ -346,8 +346,8 @@ define <vscale x 8 x i16> @zext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
; CHECK-LABEL: zext_nxv8i1_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
ret <vscale x 8 x i16> %r
@@ -357,8 +357,8 @@ define <vscale x 8 x i1> @trunc_nxv8i16_nxv8i1(<vscale x 8 x i16> %v) {
; CHECK-LABEL: trunc_nxv8i16_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 8 x i16> %v to <vscale x 8 x i1>
ret <vscale x 8 x i1> %r
@@ -368,8 +368,8 @@ define <vscale x 16 x i16> @sext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
; CHECK-LABEL: sext_nxv16i1_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 16 x i1> %v to <vscale x 16 x i16>
ret <vscale x 16 x i16> %r
@@ -379,8 +379,8 @@ define <vscale x 16 x i16> @zext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
; CHECK-LABEL: zext_nxv16i1_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 16 x i1> %v to <vscale x 16 x i16>
ret <vscale x 16 x i16> %r
@@ -390,8 +390,8 @@ define <vscale x 16 x i1> @trunc_nxv16i16_nxv16i1(<vscale x 16 x i16> %v) {
; CHECK-LABEL: trunc_nxv16i16_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 16 x i16> %v to <vscale x 16 x i1>
ret <vscale x 16 x i1> %r
@@ -434,8 +434,8 @@ define <vscale x 1 x i32> @sext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i32>
ret <vscale x 1 x i32> %r
@@ -445,8 +445,8 @@ define <vscale x 1 x i32> @zext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i32>
ret <vscale x 1 x i32> %r
@@ -456,8 +456,8 @@ define <vscale x 1 x i1> @trunc_nxv1i32_nxv1i1(<vscale x 1 x i32> %v) {
; CHECK-LABEL: trunc_nxv1i32_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i32> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -467,8 +467,8 @@ define <vscale x 2 x i32> @sext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
ret <vscale x 2 x i32> %r
@@ -478,8 +478,8 @@ define <vscale x 2 x i32> @zext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
ret <vscale x 2 x i32> %r
@@ -489,8 +489,8 @@ define <vscale x 2 x i1> @trunc_nxv2i32_nxv2i1(<vscale x 2 x i32> %v) {
; CHECK-LABEL: trunc_nxv2i32_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i32> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -500,8 +500,8 @@ define <vscale x 4 x i32> @sext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
ret <vscale x 4 x i32> %r
@@ -511,8 +511,8 @@ define <vscale x 4 x i32> @zext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
ret <vscale x 4 x i32> %r
@@ -522,8 +522,8 @@ define <vscale x 4 x i1> @trunc_nxv4i32_nxv4i1(<vscale x 4 x i32> %v) {
; CHECK-LABEL: trunc_nxv4i32_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i32> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
@@ -533,8 +533,8 @@ define <vscale x 8 x i32> @sext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
; CHECK-LABEL: sext_nxv8i1_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
ret <vscale x 8 x i32> %r
@@ -544,8 +544,8 @@ define <vscale x 8 x i32> @zext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
; CHECK-LABEL: zext_nxv8i1_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
ret <vscale x 8 x i32> %r
@@ -555,8 +555,8 @@ define <vscale x 8 x i1> @trunc_nxv8i32_nxv8i1(<vscale x 8 x i32> %v) {
; CHECK-LABEL: trunc_nxv8i32_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 8 x i32> %v to <vscale x 8 x i1>
ret <vscale x 8 x i1> %r
@@ -599,8 +599,8 @@ define <vscale x 1 x i64> @sext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i64>
ret <vscale x 1 x i64> %r
@@ -610,8 +610,8 @@ define <vscale x 1 x i64> @zext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i64>
ret <vscale x 1 x i64> %r
@@ -621,8 +621,8 @@ define <vscale x 1 x i1> @trunc_nxv1i64_nxv1i1(<vscale x 1 x i64> %v) {
; CHECK-LABEL: trunc_nxv1i64_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i64> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -632,8 +632,8 @@ define <vscale x 2 x i64> @sext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
ret <vscale x 2 x i64> %r
@@ -643,8 +643,8 @@ define <vscale x 2 x i64> @zext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
ret <vscale x 2 x i64> %r
@@ -654,8 +654,8 @@ define <vscale x 2 x i1> @trunc_nxv2i64_nxv2i1(<vscale x 2 x i64> %v) {
; CHECK-LABEL: trunc_nxv2i64_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i64> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -665,8 +665,8 @@ define <vscale x 4 x i64> @sext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i64>
ret <vscale x 4 x i64> %r
@@ -676,8 +676,8 @@ define <vscale x 4 x i64> @zext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i64>
ret <vscale x 4 x i64> %r
@@ -687,8 +687,8 @@ define <vscale x 4 x i1> @trunc_nxv4i64_nxv4i1(<vscale x 4 x i64> %v) {
; CHECK-LABEL: trunc_nxv4i64_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i64> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll
index e524230627423..c6801feaf5345 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll
@@ -5,8 +5,8 @@ define <vscale x 1 x i8> @sext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i8>
ret <vscale x 1 x i8> %r
@@ -16,8 +16,8 @@ define <vscale x 1 x i8> @zext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i8>
ret <vscale x 1 x i8> %r
@@ -27,8 +27,8 @@ define <vscale x 1 x i1> @trunc_nxv1i8_nxv1i1(<vscale x 1 x i8> %v) {
; CHECK-LABEL: trunc_nxv1i8_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i8> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -38,8 +38,8 @@ define <vscale x 2 x i8> @sext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i8>
ret <vscale x 2 x i8> %r
@@ -49,8 +49,8 @@ define <vscale x 2 x i8> @zext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i8>
ret <vscale x 2 x i8> %r
@@ -60,8 +60,8 @@ define <vscale x 2 x i1> @trunc_nxv2i8_nxv2i1(<vscale x 2 x i8> %v) {
; CHECK-LABEL: trunc_nxv2i8_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i8> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -71,8 +71,8 @@ define <vscale x 4 x i8> @sext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i8>
ret <vscale x 4 x i8> %r
@@ -82,8 +82,8 @@ define <vscale x 4 x i8> @zext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i8>
ret <vscale x 4 x i8> %r
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @trunc_nxv4i8_nxv4i1(<vscale x 4 x i8> %v) {
; CHECK-LABEL: trunc_nxv4i8_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i8> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
@@ -104,8 +104,8 @@ define <vscale x 8 x i8> @sext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
; CHECK-LABEL: sext_nxv8i1_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
ret <vscale x 8 x i8> %r
@@ -115,8 +115,8 @@ define <vscale x 8 x i8> @zext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
; CHECK-LABEL: zext_nxv8i1_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
ret <vscale x 8 x i8> %r
@@ -126,8 +126,8 @@ define <vscale x 8 x i1> @trunc_nxv8i8_nxv8i1(<vscale x 8 x i8> %v) {
; CHECK-LABEL: trunc_nxv8i8_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 8 x i8> %v to <vscale x 8 x i1>
ret <vscale x 8 x i1> %r
@@ -137,8 +137,8 @@ define <vscale x 16 x i8> @sext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
; CHECK-LABEL: sext_nxv16i1_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
ret <vscale x 16 x i8> %r
@@ -148,8 +148,8 @@ define <vscale x 16 x i8> @zext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
; CHECK-LABEL: zext_nxv16i1_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
ret <vscale x 16 x i8> %r
@@ -159,8 +159,8 @@ define <vscale x 16 x i1> @trunc_nxv16i8_nxv16i1(<vscale x 16 x i8> %v) {
; CHECK-LABEL: trunc_nxv16i8_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 16 x i8> %v to <vscale x 16 x i1>
ret <vscale x 16 x i1> %r
@@ -170,8 +170,8 @@ define <vscale x 32 x i8> @sext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
; CHECK-LABEL: sext_nxv32i1_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 32 x i1> %v to <vscale x 32 x i8>
ret <vscale x 32 x i8> %r
@@ -181,8 +181,8 @@ define <vscale x 32 x i8> @zext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
; CHECK-LABEL: zext_nxv32i1_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 32 x i1> %v to <vscale x 32 x i8>
ret <vscale x 32 x i8> %r
@@ -192,8 +192,8 @@ define <vscale x 32 x i1> @trunc_nxv32i8_nxv32i1(<vscale x 32 x i8> %v) {
; CHECK-LABEL: trunc_nxv32i8_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 32 x i8> %v to <vscale x 32 x i1>
ret <vscale x 32 x i1> %r
@@ -236,8 +236,8 @@ define <vscale x 1 x i16> @sext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i16>
ret <vscale x 1 x i16> %r
@@ -247,8 +247,8 @@ define <vscale x 1 x i16> @zext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i16>
ret <vscale x 1 x i16> %r
@@ -258,8 +258,8 @@ define <vscale x 1 x i1> @trunc_nxv1i16_nxv1i1(<vscale x 1 x i16> %v) {
; CHECK-LABEL: trunc_nxv1i16_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i16> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -269,8 +269,8 @@ define <vscale x 2 x i16> @sext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i16>
ret <vscale x 2 x i16> %r
@@ -280,8 +280,8 @@ define <vscale x 2 x i16> @zext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i16>
ret <vscale x 2 x i16> %r
@@ -291,8 +291,8 @@ define <vscale x 2 x i1> @trunc_nxv2i16_nxv2i1(<vscale x 2 x i16> %v) {
; CHECK-LABEL: trunc_nxv2i16_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i16> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -302,8 +302,8 @@ define <vscale x 4 x i16> @sext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
ret <vscale x 4 x i16> %r
@@ -313,8 +313,8 @@ define <vscale x 4 x i16> @zext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
ret <vscale x 4 x i16> %r
@@ -324,8 +324,8 @@ define <vscale x 4 x i1> @trunc_nxv4i16_nxv4i1(<vscale x 4 x i16> %v) {
; CHECK-LABEL: trunc_nxv4i16_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i16> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
@@ -335,8 +335,8 @@ define <vscale x 8 x i16> @sext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
; CHECK-LABEL: sext_nxv8i1_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
ret <vscale x 8 x i16> %r
@@ -346,8 +346,8 @@ define <vscale x 8 x i16> @zext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
; CHECK-LABEL: zext_nxv8i1_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
ret <vscale x 8 x i16> %r
@@ -357,8 +357,8 @@ define <vscale x 8 x i1> @trunc_nxv8i16_nxv8i1(<vscale x 8 x i16> %v) {
; CHECK-LABEL: trunc_nxv8i16_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 8 x i16> %v to <vscale x 8 x i1>
ret <vscale x 8 x i1> %r
@@ -368,8 +368,8 @@ define <vscale x 16 x i16> @sext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
; CHECK-LABEL: sext_nxv16i1_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 16 x i1> %v to <vscale x 16 x i16>
ret <vscale x 16 x i16> %r
@@ -379,8 +379,8 @@ define <vscale x 16 x i16> @zext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
; CHECK-LABEL: zext_nxv16i1_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 16 x i1> %v to <vscale x 16 x i16>
ret <vscale x 16 x i16> %r
@@ -390,8 +390,8 @@ define <vscale x 16 x i1> @trunc_nxv16i16_nxv16i1(<vscale x 16 x i16> %v) {
; CHECK-LABEL: trunc_nxv16i16_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 16 x i16> %v to <vscale x 16 x i1>
ret <vscale x 16 x i1> %r
@@ -434,8 +434,8 @@ define <vscale x 1 x i32> @sext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i32>
ret <vscale x 1 x i32> %r
@@ -445,8 +445,8 @@ define <vscale x 1 x i32> @zext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i32>
ret <vscale x 1 x i32> %r
@@ -456,8 +456,8 @@ define <vscale x 1 x i1> @trunc_nxv1i32_nxv1i1(<vscale x 1 x i32> %v) {
; CHECK-LABEL: trunc_nxv1i32_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i32> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -467,8 +467,8 @@ define <vscale x 2 x i32> @sext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
ret <vscale x 2 x i32> %r
@@ -478,8 +478,8 @@ define <vscale x 2 x i32> @zext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
ret <vscale x 2 x i32> %r
@@ -489,8 +489,8 @@ define <vscale x 2 x i1> @trunc_nxv2i32_nxv2i1(<vscale x 2 x i32> %v) {
; CHECK-LABEL: trunc_nxv2i32_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i32> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -500,8 +500,8 @@ define <vscale x 4 x i32> @sext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
ret <vscale x 4 x i32> %r
@@ -511,8 +511,8 @@ define <vscale x 4 x i32> @zext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
ret <vscale x 4 x i32> %r
@@ -522,8 +522,8 @@ define <vscale x 4 x i1> @trunc_nxv4i32_nxv4i1(<vscale x 4 x i32> %v) {
; CHECK-LABEL: trunc_nxv4i32_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i32> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
@@ -533,8 +533,8 @@ define <vscale x 8 x i32> @sext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
; CHECK-LABEL: sext_nxv8i1_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
ret <vscale x 8 x i32> %r
@@ -544,8 +544,8 @@ define <vscale x 8 x i32> @zext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
; CHECK-LABEL: zext_nxv8i1_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
ret <vscale x 8 x i32> %r
@@ -555,8 +555,8 @@ define <vscale x 8 x i1> @trunc_nxv8i32_nxv8i1(<vscale x 8 x i32> %v) {
; CHECK-LABEL: trunc_nxv8i32_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 8 x i32> %v to <vscale x 8 x i1>
ret <vscale x 8 x i1> %r
@@ -599,8 +599,8 @@ define <vscale x 1 x i64> @sext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
; CHECK-LABEL: sext_nxv1i1_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 1 x i1> %v to <vscale x 1 x i64>
ret <vscale x 1 x i64> %r
@@ -610,8 +610,8 @@ define <vscale x 1 x i64> @zext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
; CHECK-LABEL: zext_nxv1i1_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v8, v25, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 1 x i1> %v to <vscale x 1 x i64>
ret <vscale x 1 x i64> %r
@@ -621,8 +621,8 @@ define <vscale x 1 x i1> @trunc_nxv1i64_nxv1i1(<vscale x 1 x i64> %v) {
; CHECK-LABEL: trunc_nxv1i64_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vand.vi v25, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 1 x i64> %v to <vscale x 1 x i1>
ret <vscale x 1 x i1> %r
@@ -632,8 +632,8 @@ define <vscale x 2 x i64> @sext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
; CHECK-LABEL: sext_nxv2i1_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
ret <vscale x 2 x i64> %r
@@ -643,8 +643,8 @@ define <vscale x 2 x i64> @zext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
; CHECK-LABEL: zext_nxv2i1_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v8, v26, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
ret <vscale x 2 x i64> %r
@@ -654,8 +654,8 @@ define <vscale x 2 x i1> @trunc_nxv2i64_nxv2i1(<vscale x 2 x i64> %v) {
; CHECK-LABEL: trunc_nxv2i64_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vand.vi v26, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 2 x i64> %v to <vscale x 2 x i1>
ret <vscale x 2 x i1> %r
@@ -665,8 +665,8 @@ define <vscale x 4 x i64> @sext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
; CHECK-LABEL: sext_nxv4i1_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, -1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%r = sext <vscale x 4 x i1> %v to <vscale x 4 x i64>
ret <vscale x 4 x i64> %r
@@ -676,8 +676,8 @@ define <vscale x 4 x i64> @zext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
; CHECK-LABEL: zext_nxv4i1_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v8, v28, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: ret
%r = zext <vscale x 4 x i1> %v to <vscale x 4 x i64>
ret <vscale x 4 x i64> %r
@@ -687,8 +687,8 @@ define <vscale x 4 x i1> @trunc_nxv4i64_nxv4i1(<vscale x 4 x i64> %v) {
; CHECK-LABEL: trunc_nxv4i64_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vand.vi v28, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%r = trunc <vscale x 4 x i64> %v to <vscale x 4 x i1>
ret <vscale x 4 x i1> %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
index 74b3c06831114..9cce462522d6b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
@@ -17,10 +17,10 @@ body: |
; CHECK: liveins: $v0, $v1, $v2, $v3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $v0 = COPY killed renamable $v1
- ; CHECK-NEXT: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype
- ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, 1, 3, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v8, killed renamable $v9, 1, 3, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET implicit $v0
%0:vr = COPY $v0
%1:vr = COPY $v1
diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
index d10339866583b..f53162040c5de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
@@ -134,8 +134,8 @@ define <vscale x 2 x i64> @mgather_nxv2i8_sextload_nxv2i64(<vscale x 2 x i8*> %p
; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vsext.vf8 v26, v9
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vsext.vf8 v10, v9
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_nxv2i8_sextload_nxv2i64:
@@ -156,8 +156,8 @@ define <vscale x 2 x i64> @mgather_nxv2i8_zextload_nxv2i64(<vscale x 2 x i8*> %p
; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vzext.vf8 v26, v9
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vzext.vf8 v10, v9
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_nxv2i8_zextload_nxv2i64:
@@ -196,15 +196,15 @@ define <vscale x 4 x i8> @mgather_truemask_nxv4i8(<vscale x 4 x i8*> %ptrs, <vsc
; RV32-LABEL: mgather_truemask_nxv4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_nxv4i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -250,9 +250,9 @@ define <vscale x 8 x i8> @mgather_baseidx_nxv8i8(i8* %base, <vscale x 8 x i8> %i
; RV32-LABEL: mgather_baseidx_nxv8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
+; RV32-NEXT: vsext.vf4 v12, v8
; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV32-NEXT: vluxei32.v v9, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v9, (a0), v12, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
@@ -357,8 +357,8 @@ define <vscale x 2 x i64> @mgather_nxv2i16_sextload_nxv2i64(<vscale x 2 x i16*>
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v26, v9
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vsext.vf4 v10, v9
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_nxv2i16_sextload_nxv2i64:
@@ -379,8 +379,8 @@ define <vscale x 2 x i64> @mgather_nxv2i16_zextload_nxv2i64(<vscale x 2 x i16*>
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v26, v9
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vzext.vf4 v10, v9
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_nxv2i16_zextload_nxv2i64:
@@ -419,15 +419,15 @@ define <vscale x 4 x i16> @mgather_truemask_nxv4i16(<vscale x 4 x i16*> %ptrs, <
; RV32-LABEL: mgather_truemask_nxv4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_nxv4i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -473,10 +473,10 @@ define <vscale x 8 x i16> @mgather_baseidx_nxv8i8_nxv8i16(i16* %base, <vscale x
; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -498,10 +498,10 @@ define <vscale x 8 x i16> @mgather_baseidx_sext_nxv8i8_nxv8i16(i16* %base, <vsca
; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -524,10 +524,10 @@ define <vscale x 8 x i16> @mgather_baseidx_zext_nxv8i8_nxv8i16(i16* %base, <vsca
; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -550,10 +550,10 @@ define <vscale x 8 x i16> @mgather_baseidx_nxv8i16(i16* %base, <vscale x 8 x i16
; RV32-LABEL: mgather_baseidx_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -617,8 +617,8 @@ define <vscale x 2 x i64> @mgather_nxv2i32_sextload_nxv2i64(<vscale x 2 x i32*>
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v26, v9
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vsext.vf2 v10, v9
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_nxv2i32_sextload_nxv2i64:
@@ -639,8 +639,8 @@ define <vscale x 2 x i64> @mgather_nxv2i32_zextload_nxv2i64(<vscale x 2 x i32*>
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v26, v9
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vzext.vf2 v10, v9
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_nxv2i32_zextload_nxv2i64:
@@ -685,8 +685,8 @@ define <vscale x 4 x i32> @mgather_truemask_nxv4i32(<vscale x 4 x i32*> %ptrs, <
; RV64-LABEL: mgather_truemask_nxv4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -732,9 +732,9 @@ define <vscale x 8 x i32> @mgather_baseidx_nxv8i8_nxv8i32(i32* %base, <vscale x
; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -756,9 +756,9 @@ define <vscale x 8 x i32> @mgather_baseidx_sext_nxv8i8_nxv8i32(i32* %base, <vsca
; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -781,9 +781,9 @@ define <vscale x 8 x i32> @mgather_baseidx_zext_nxv8i8_nxv8i32(i32* %base, <vsca
; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -806,9 +806,9 @@ define <vscale x 8 x i32> @mgather_baseidx_nxv8i16_nxv8i32(i32* %base, <vscale x
; RV32-LABEL: mgather_baseidx_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -830,9 +830,9 @@ define <vscale x 8 x i32> @mgather_baseidx_sext_nxv8i16_nxv8i32(i32* %base, <vsc
; RV32-LABEL: mgather_baseidx_sext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -855,9 +855,9 @@ define <vscale x 8 x i32> @mgather_baseidx_zext_nxv8i16_nxv8i32(i32* %base, <vsc
; RV32-LABEL: mgather_baseidx_zext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -880,8 +880,8 @@ define <vscale x 8 x i32> @mgather_baseidx_nxv8i32(i32* %base, <vscale x 8 x i32
; RV32-LABEL: mgather_baseidx_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -963,8 +963,8 @@ define <vscale x 4 x i64> @mgather_truemask_nxv4i64(<vscale x 4 x i64*> %ptrs, <
; RV32-LABEL: mgather_truemask_nxv4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_nxv4i64:
@@ -1016,10 +1016,10 @@ define <vscale x 8 x i64> @mgather_baseidx_nxv8i8_nxv8i64(i64* %base, <vscale x
; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: vmv8r.v v8, v16
; RV32-NEXT: ret
;
@@ -1088,10 +1088,10 @@ define <vscale x 8 x i64> @mgather_baseidx_nxv8i16_nxv8i64(i64* %base, <vscale x
; RV32-LABEL: mgather_baseidx_nxv8i16_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: vmv8r.v v8, v16
; RV32-NEXT: ret
;
@@ -1160,9 +1160,9 @@ define <vscale x 8 x i64> @mgather_baseidx_nxv8i32_nxv8i64(i64* %base, <vscale x
; RV32-LABEL: mgather_baseidx_nxv8i32_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 3
+; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: vmv8r.v v8, v16
; RV32-NEXT: ret
;
@@ -1378,15 +1378,15 @@ define <vscale x 4 x half> @mgather_truemask_nxv4f16(<vscale x 4 x half*> %ptrs,
; RV32-LABEL: mgather_truemask_nxv4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_nxv4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -1432,10 +1432,10 @@ define <vscale x 8 x half> @mgather_baseidx_nxv8i8_nxv8f16(half* %base, <vscale
; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -1457,10 +1457,10 @@ define <vscale x 8 x half> @mgather_baseidx_sext_nxv8i8_nxv8f16(half* %base, <vs
; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -1483,10 +1483,10 @@ define <vscale x 8 x half> @mgather_baseidx_zext_nxv8i8_nxv8f16(half* %base, <vs
; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -1509,10 +1509,10 @@ define <vscale x 8 x half> @mgather_baseidx_nxv8f16(half* %base, <vscale x 8 x i
; RV32-LABEL: mgather_baseidx_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v10, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
@@ -1600,8 +1600,8 @@ define <vscale x 4 x float> @mgather_truemask_nxv4f32(<vscale x 4 x float*> %ptr
; RV64-LABEL: mgather_truemask_nxv4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -1647,9 +1647,9 @@ define <vscale x 8 x float> @mgather_baseidx_nxv8i8_nxv8f32(float* %base, <vscal
; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -1671,9 +1671,9 @@ define <vscale x 8 x float> @mgather_baseidx_sext_nxv8i8_nxv8f32(float* %base, <
; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -1696,9 +1696,9 @@ define <vscale x 8 x float> @mgather_baseidx_zext_nxv8i8_nxv8f32(float* %base, <
; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -1721,9 +1721,9 @@ define <vscale x 8 x float> @mgather_baseidx_nxv8i16_nxv8f32(float* %base, <vsca
; RV32-LABEL: mgather_baseidx_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -1745,9 +1745,9 @@ define <vscale x 8 x float> @mgather_baseidx_sext_nxv8i16_nxv8f32(float* %base,
; RV32-LABEL: mgather_baseidx_sext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -1770,9 +1770,9 @@ define <vscale x 8 x float> @mgather_baseidx_zext_nxv8i16_nxv8f32(float* %base,
; RV32-LABEL: mgather_baseidx_zext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v8
+; RV32-NEXT: vsll.vi v8, v16, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -1795,8 +1795,8 @@ define <vscale x 8 x float> @mgather_baseidx_nxv8f32(float* %base, <vscale x 8 x
; RV32-LABEL: mgather_baseidx_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 2
-; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2
+; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
@@ -1878,8 +1878,8 @@ define <vscale x 4 x double> @mgather_truemask_nxv4f64(<vscale x 4 x double*> %p
; RV32-LABEL: mgather_truemask_nxv4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_truemask_nxv4f64:
@@ -1931,10 +1931,10 @@ define <vscale x 8 x double> @mgather_baseidx_nxv8i8_nxv8f64(double* %base, <vsc
; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: vmv8r.v v8, v16
; RV32-NEXT: ret
;
@@ -2003,10 +2003,10 @@ define <vscale x 8 x double> @mgather_baseidx_nxv8i16_nxv8f64(double* %base, <vs
; RV32-LABEL: mgather_baseidx_nxv8i16_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: vmv8r.v v8, v16
; RV32-NEXT: ret
;
@@ -2075,9 +2075,9 @@ define <vscale x 8 x double> @mgather_baseidx_nxv8i32_nxv8f64(double* %base, <vs
; RV32-LABEL: mgather_baseidx_nxv8i32_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 3
+; RV32-NEXT: vsll.vi v8, v8, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: vmv8r.v v8, v16
; RV32-NEXT: ret
;
@@ -2218,22 +2218,22 @@ define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(i8* %base, <vscale x 32 x i8>
;
; RV64-LABEL: mgather_baseidx_nxv32i8:
; RV64: # %bb.0:
-; RV64-NEXT: vmv1r.v v25, v0
+; RV64-NEXT: vmv1r.v v16, v0
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vsext.vf8 v16, v8
+; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV64-NEXT: vluxei64.v v12, (a0), v16, v0.t
+; RV64-NEXT: vluxei64.v v12, (a0), v24, v0.t
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a2, a1, 3
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, mu
-; RV64-NEXT: vsext.vf8 v16, v9
+; RV64-NEXT: vsext.vf8 v24, v9
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV64-NEXT: vluxei64.v v13, (a0), v16, v0.t
+; RV64-NEXT: vluxei64.v v13, (a0), v24, v0.t
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, mu
-; RV64-NEXT: vslidedown.vx v0, v25, a1
+; RV64-NEXT: vslidedown.vx v0, v16, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
index 80ecb34b0dee9..1301eb9ce74cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
@@ -44,15 +44,15 @@ define void @mscatter_nxv2i16_truncstore_nxv2i8(<vscale x 2 x i16> %val, <vscale
; RV32-LABEL: mscatter_nxv2i16_truncstore_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i16_truncstore_nxv2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i16> %val to <vscale x 2 x i8>
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
@@ -63,19 +63,19 @@ define void @mscatter_nxv2i32_truncstore_nxv2i8(<vscale x 2 x i32> %val, <vscale
; RV32-LABEL: mscatter_nxv2i32_truncstore_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i32_truncstore_nxv2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i8>
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
@@ -86,23 +86,23 @@ define void @mscatter_nxv2i64_truncstore_nxv2i8(<vscale x 2 x i64> %val, <vscale
; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v11, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v11, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v12, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v12, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8>
call void @llvm.masked.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, i32 1, <vscale x 2 x i1> %m)
@@ -179,9 +179,9 @@ define void @mscatter_baseidx_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale
; RV32-LABEL: mscatter_baseidx_nxv8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v9
+; RV32-NEXT: vsext.vf4 v12, v9
; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i8:
@@ -236,15 +236,15 @@ define void @mscatter_nxv2i32_truncstore_nxv2i16(<vscale x 2 x i32> %val, <vscal
; RV32-LABEL: mscatter_nxv2i32_truncstore_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i32_truncstore_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i16>
call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m)
@@ -255,19 +255,19 @@ define void @mscatter_nxv2i64_truncstore_nxv2i16(<vscale x 2 x i64> %val, <vscal
; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v11, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
+; RV32-NEXT: vnsrl.wi v8, v11, 0
+; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v12, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v8, v12, 0
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16>
call void @llvm.masked.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, i32 2, <vscale x 2 x i1> %m)
@@ -344,10 +344,10 @@ define void @mscatter_baseidx_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16* %base
; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8i16:
@@ -367,10 +367,10 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16*
; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i16:
@@ -391,10 +391,10 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16*
; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i16:
@@ -415,10 +415,10 @@ define void @mscatter_baseidx_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vsca
; RV32-LABEL: mscatter_baseidx_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i16:
@@ -474,15 +474,15 @@ define void @mscatter_nxv2i64_truncstore_nxv2i32(<vscale x 2 x i64> %val, <vscal
; RV32-LABEL: mscatter_nxv2i64_truncstore_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
-; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
+; RV32-NEXT: vnsrl.wi v11, v8, 0
+; RV32-NEXT: vsoxei32.v v11, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv2i64_truncstore_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vnsrl.wi v12, v8, 0
+; RV64-NEXT: vsoxei64.v v12, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32>
call void @llvm.masked.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %tval, <vscale x 2 x i32*> %ptrs, i32 4, <vscale x 2 x i1> %m)
@@ -559,9 +559,9 @@ define void @mscatter_baseidx_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, i32* %base
; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8i32:
@@ -581,9 +581,9 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, i32*
; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i32:
@@ -604,9 +604,9 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, i32*
; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i32:
@@ -627,9 +627,9 @@ define void @mscatter_baseidx_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, i32* %bas
; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8i32:
@@ -649,9 +649,9 @@ define void @mscatter_baseidx_sext_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, i32*
; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i32:
@@ -672,9 +672,9 @@ define void @mscatter_baseidx_zext_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, i32*
; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i32:
@@ -695,8 +695,8 @@ define void @mscatter_baseidx_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vsca
; RV32-LABEL: mscatter_baseidx_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v12, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v12, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i32:
@@ -818,10 +818,10 @@ define void @mscatter_baseidx_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %base
; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8i64:
@@ -884,10 +884,10 @@ define void @mscatter_baseidx_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %bas
; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8i64:
@@ -950,9 +950,9 @@ define void @mscatter_baseidx_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %bas
; RV32-LABEL: mscatter_baseidx_nxv8i32_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v16, 3
+; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i32_nxv8i64:
@@ -1136,10 +1136,10 @@ define void @mscatter_baseidx_nxv8i8_nxv8f16(<vscale x 8 x half> %val, half* %ba
; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8f16:
@@ -1159,10 +1159,10 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, half
; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f16:
@@ -1183,10 +1183,10 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, half
; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f16:
@@ -1207,10 +1207,10 @@ define void @mscatter_baseidx_nxv8f16(<vscale x 8 x half> %val, half* %base, <vs
; RV32-LABEL: mscatter_baseidx_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8f16:
@@ -1332,9 +1332,9 @@ define void @mscatter_baseidx_nxv8i8_nxv8f32(<vscale x 8 x float> %val, float* %
; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8f32:
@@ -1354,9 +1354,9 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8f32(<vscale x 8 x float> %val, flo
; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f32:
@@ -1377,9 +1377,9 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8f32(<vscale x 8 x float> %val, flo
; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f32:
@@ -1400,9 +1400,9 @@ define void @mscatter_baseidx_nxv8i16_nxv8f32(<vscale x 8 x float> %val, float*
; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8f32:
@@ -1422,9 +1422,9 @@ define void @mscatter_baseidx_sext_nxv8i16_nxv8f32(<vscale x 8 x float> %val, fl
; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f32:
@@ -1445,9 +1445,9 @@ define void @mscatter_baseidx_zext_nxv8i16_nxv8f32(<vscale x 8 x float> %val, fl
; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vzext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f32:
@@ -1468,8 +1468,8 @@ define void @mscatter_baseidx_nxv8f32(<vscale x 8 x float> %val, float* %base, <
; RV32-LABEL: mscatter_baseidx_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v12, 2
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsll.vi v12, v12, 2
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8f32:
@@ -1591,10 +1591,10 @@ define void @mscatter_baseidx_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double*
; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8f64:
@@ -1657,10 +1657,10 @@ define void @mscatter_baseidx_nxv8i16_nxv8f64(<vscale x 8 x double> %val, double
; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8f64:
@@ -1723,9 +1723,9 @@ define void @mscatter_baseidx_nxv8i32_nxv8f64(<vscale x 8 x double> %val, double
; RV32-LABEL: mscatter_baseidx_nxv8i32_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v16, 3
+; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_baseidx_nxv8i32_nxv8f64:
@@ -1811,16 +1811,16 @@ declare <vscale x 16 x double*> @llvm.experimental.vector.insert.nxv8p0f64.nxv16
define void @mscatter_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double> %val1, <vscale x 8 x double*> %ptrs0, <vscale x 8 x double*> %ptrs1, <vscale x 16 x i1> %m) {
; RV32-LABEL: mscatter_nxv16f64:
; RV32: # %bb.0:
-; RV32-NEXT: vl4re32.v v28, (a0)
-; RV32-NEXT: vl4re32.v v24, (a1)
+; RV32-NEXT: vl4re32.v v24, (a0)
+; RV32-NEXT: vl4re32.v v28, (a1)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (zero), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v24, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: srli a0, a0, 3
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; RV32-NEXT: vslidedown.vx v0, v0, a0
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v16, (zero), v24, v0.t
+; RV32-NEXT: vsoxei32.v v16, (zero), v28, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_nxv16f64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
index 7ed58d53c5873..78997a99faf9a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
@@ -53,11 +53,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 3
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vid.v v25
-; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
+; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv1i8:
@@ -66,10 +66,10 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV32-BITS-256-NEXT: srli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; RV32-BITS-256-NEXT: vid.v v25
-; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-256-NEXT: vmv1r.v v8, v25
+; RV32-BITS-256-NEXT: vid.v v9
+; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-256-NEXT: vmv1r.v v8, v9
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv1i8:
@@ -78,10 +78,10 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV32-BITS-512-NEXT: srli a0, a0, 3
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; RV32-BITS-512-NEXT: vid.v v25
-; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-512-NEXT: vmv1r.v v8, v25
+; RV32-BITS-512-NEXT: vid.v v9
+; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-512-NEXT: vmv1r.v v8, v9
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv1i8:
@@ -90,11 +90,11 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 3
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vid.v v25
-; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
+; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv1i8:
@@ -103,10 +103,10 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV64-BITS-256-NEXT: srli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; RV64-BITS-256-NEXT: vid.v v25
-; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-256-NEXT: vmv1r.v v8, v25
+; RV64-BITS-256-NEXT: vid.v v9
+; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-256-NEXT: vmv1r.v v8, v9
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv1i8:
@@ -115,10 +115,10 @@ define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV64-BITS-512-NEXT: srli a0, a0, 3
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; RV64-BITS-512-NEXT: vid.v v25
-; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-512-NEXT: vmv1r.v v8, v25
+; RV64-BITS-512-NEXT: vid.v v9
+; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-512-NEXT: vmv1r.v v8, v9
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.experimental.vector.reverse.nxv1i8(<vscale x 1 x i8> %a)
ret <vscale x 1 x i8> %res
@@ -131,11 +131,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vid.v v25
-; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
+; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv2i8:
@@ -144,10 +144,10 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV32-BITS-256-NEXT: srli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV32-BITS-256-NEXT: vid.v v25
-; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-256-NEXT: vmv1r.v v8, v25
+; RV32-BITS-256-NEXT: vid.v v9
+; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-256-NEXT: vmv1r.v v8, v9
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv2i8:
@@ -156,10 +156,10 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV32-BITS-512-NEXT: srli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV32-BITS-512-NEXT: vid.v v25
-; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-512-NEXT: vmv1r.v v8, v25
+; RV32-BITS-512-NEXT: vid.v v9
+; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-512-NEXT: vmv1r.v v8, v9
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i8:
@@ -168,11 +168,11 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vid.v v25
-; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
+; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv2i8:
@@ -181,10 +181,10 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV64-BITS-256-NEXT: srli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV64-BITS-256-NEXT: vid.v v25
-; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-256-NEXT: vmv1r.v v8, v25
+; RV64-BITS-256-NEXT: vid.v v9
+; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-256-NEXT: vmv1r.v v8, v9
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv2i8:
@@ -193,10 +193,10 @@ define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV64-BITS-512-NEXT: srli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV64-BITS-512-NEXT: vid.v v25
-; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-512-NEXT: vmv1r.v v8, v25
+; RV64-BITS-512-NEXT: vid.v v9
+; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-512-NEXT: vmv1r.v v8, v9
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8> %a)
ret <vscale x 2 x i8> %res
@@ -209,11 +209,11 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vid.v v25
-; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0
+; RV32-BITS-UNKNOWN-NEXT: vid.v v9
+; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv4i8:
@@ -222,10 +222,10 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV32-BITS-256-NEXT: srli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; RV32-BITS-256-NEXT: vid.v v25
-; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-256-NEXT: vmv1r.v v8, v25
+; RV32-BITS-256-NEXT: vid.v v9
+; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-256-NEXT: vmv1r.v v8, v9
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv4i8:
@@ -234,10 +234,10 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV32-BITS-512-NEXT: srli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; RV32-BITS-512-NEXT: vid.v v25
-; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-512-NEXT: vmv1r.v v8, v25
+; RV32-BITS-512-NEXT: vid.v v9
+; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-512-NEXT: vmv1r.v v8, v9
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i8:
@@ -246,11 +246,11 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vid.v v25
-; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0
+; RV64-BITS-UNKNOWN-NEXT: vid.v v9
+; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv4i8:
@@ -259,10 +259,10 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV64-BITS-256-NEXT: srli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; RV64-BITS-256-NEXT: vid.v v25
-; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-256-NEXT: vmv1r.v v8, v25
+; RV64-BITS-256-NEXT: vid.v v9
+; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-256-NEXT: vmv1r.v v8, v9
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv4i8:
@@ -271,10 +271,10 @@ define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV64-BITS-512-NEXT: srli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; RV64-BITS-512-NEXT: vid.v v25
-; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-512-NEXT: vmv1r.v v8, v25
+; RV64-BITS-512-NEXT: vid.v v9
+; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-512-NEXT: vmv1r.v v8, v9
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.reverse.nxv4i8(<vscale x 4 x i8> %a)
ret <vscale x 4 x i8> %res
@@ -286,11 +286,11 @@ define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vid.v v26
-; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v26, a0
+; RV32-BITS-UNKNOWN-NEXT: vid.v v10
+; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv8i8:
@@ -298,10 +298,10 @@ define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {
; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; RV32-BITS-256-NEXT: vid.v v25
-; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-256-NEXT: vmv1r.v v8, v25
+; RV32-BITS-256-NEXT: vid.v v9
+; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-256-NEXT: vmv1r.v v8, v9
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv8i8:
@@ -309,10 +309,10 @@ define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {
; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; RV32-BITS-512-NEXT: vid.v v25
-; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV32-BITS-512-NEXT: vmv1r.v v8, v25
+; RV32-BITS-512-NEXT: vid.v v9
+; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV32-BITS-512-NEXT: vmv1r.v v8, v9
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i8:
@@ -320,11 +320,11 @@ define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vid.v v26
-; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v26, a0
+; RV64-BITS-UNKNOWN-NEXT: vid.v v10
+; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26
-; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25
+; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
+; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv8i8:
@@ -332,10 +332,10 @@ define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {
; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; RV64-BITS-256-NEXT: vid.v v25
-; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-256-NEXT: vmv1r.v v8, v25
+; RV64-BITS-256-NEXT: vid.v v9
+; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-256-NEXT: vmv1r.v v8, v9
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv8i8:
@@ -343,10 +343,10 @@ define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) {
; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; RV64-BITS-512-NEXT: vid.v v25
-; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0
-; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26
-; RV64-BITS-512-NEXT: vmv1r.v v8, v25
+; RV64-BITS-512-NEXT: vid.v v9
+; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
+; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
+; RV64-BITS-512-NEXT: vmv1r.v v8, v9
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.reverse.nxv8i8(<vscale x 8 x i8> %a)
ret <vscale x 8 x i8> %res
@@ -359,11 +359,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vid.v v28
-; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v28, v28, a0
+; RV32-BITS-UNKNOWN-NEXT: vid.v v12
+; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v26, v8, v28
-; RV32-BITS-UNKNOWN-NEXT: vmv2r.v v8, v26
+; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
+; RV32-BITS-UNKNOWN-NEXT: vmv2r.v v8, v10
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv16i8:
@@ -372,10 +372,10 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV32-BITS-256-NEXT: slli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; RV32-BITS-256-NEXT: vid.v v26
-; RV32-BITS-256-NEXT: vrsub.vx v28, v26, a0
-; RV32-BITS-256-NEXT: vrgather.vv v26, v8, v28
-; RV32-BITS-256-NEXT: vmv2r.v v8, v26
+; RV32-BITS-256-NEXT: vid.v v10
+; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a0
+; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v12
+; RV32-BITS-256-NEXT: vmv2r.v v8, v10
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv16i8:
@@ -384,10 +384,10 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV32-BITS-512-NEXT: slli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; RV32-BITS-512-NEXT: vid.v v26
-; RV32-BITS-512-NEXT: vrsub.vx v28, v26, a0
-; RV32-BITS-512-NEXT: vrgather.vv v26, v8, v28
-; RV32-BITS-512-NEXT: vmv2r.v v8, v26
+; RV32-BITS-512-NEXT: vid.v v10
+; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a0
+; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v12
+; RV32-BITS-512-NEXT: vmv2r.v v8, v10
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i8:
@@ -396,11 +396,11 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vid.v v28
-; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v28, v28, a0
+; RV64-BITS-UNKNOWN-NEXT: vid.v v12
+; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v26, v8, v28
-; RV64-BITS-UNKNOWN-NEXT: vmv2r.v v8, v26
+; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
+; RV64-BITS-UNKNOWN-NEXT: vmv2r.v v8, v10
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv16i8:
@@ -409,10 +409,10 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV64-BITS-256-NEXT: slli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; RV64-BITS-256-NEXT: vid.v v26
-; RV64-BITS-256-NEXT: vrsub.vx v28, v26, a0
-; RV64-BITS-256-NEXT: vrgather.vv v26, v8, v28
-; RV64-BITS-256-NEXT: vmv2r.v v8, v26
+; RV64-BITS-256-NEXT: vid.v v10
+; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a0
+; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v12
+; RV64-BITS-256-NEXT: vmv2r.v v8, v10
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv16i8:
@@ -421,10 +421,10 @@ define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV64-BITS-512-NEXT: slli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; RV64-BITS-512-NEXT: vid.v v26
-; RV64-BITS-512-NEXT: vrsub.vx v28, v26, a0
-; RV64-BITS-512-NEXT: vrgather.vv v26, v8, v28
-; RV64-BITS-512-NEXT: vmv2r.v v8, v26
+; RV64-BITS-512-NEXT: vid.v v10
+; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a0
+; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v12
+; RV64-BITS-512-NEXT: vmv2r.v v8, v10
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> %a)
ret <vscale x 16 x i8> %res
@@ -440,8 +440,8 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, mu
-; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16
-; RV32-BITS-UNKNOWN-NEXT: vmv4r.v v8, v28
+; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
+; RV32-BITS-UNKNOWN-NEXT: vmv4r.v v8, v12
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_nxv32i8:
@@ -450,10 +450,10 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV32-BITS-256-NEXT: slli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; RV32-BITS-256-NEXT: vid.v v28
-; RV32-BITS-256-NEXT: vrsub.vx v12, v28, a0
-; RV32-BITS-256-NEXT: vrgather.vv v28, v8, v12
-; RV32-BITS-256-NEXT: vmv4r.v v8, v28
+; RV32-BITS-256-NEXT: vid.v v12
+; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a0
+; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v16
+; RV32-BITS-256-NEXT: vmv4r.v v8, v12
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_nxv32i8:
@@ -462,10 +462,10 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; RV32-BITS-512-NEXT: vid.v v28
-; RV32-BITS-512-NEXT: vrsub.vx v12, v28, a0
-; RV32-BITS-512-NEXT: vrgather.vv v28, v8, v12
-; RV32-BITS-512-NEXT: vmv4r.v v8, v28
+; RV32-BITS-512-NEXT: vid.v v12
+; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a0
+; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v16
+; RV32-BITS-512-NEXT: vmv4r.v v8, v12
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i8:
@@ -477,8 +477,8 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, mu
-; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16
-; RV64-BITS-UNKNOWN-NEXT: vmv4r.v v8, v28
+; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
+; RV64-BITS-UNKNOWN-NEXT: vmv4r.v v8, v12
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_nxv32i8:
@@ -487,10 +487,10 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV64-BITS-256-NEXT: slli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; RV64-BITS-256-NEXT: vid.v v28
-; RV64-BITS-256-NEXT: vrsub.vx v12, v28, a0
-; RV64-BITS-256-NEXT: vrgather.vv v28, v8, v12
-; RV64-BITS-256-NEXT: vmv4r.v v8, v28
+; RV64-BITS-256-NEXT: vid.v v12
+; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a0
+; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v16
+; RV64-BITS-256-NEXT: vmv4r.v v8, v12
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_nxv32i8:
@@ -499,10 +499,10 @@ define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; RV64-BITS-512-NEXT: vid.v v28
-; RV64-BITS-512-NEXT: vrsub.vx v12, v28, a0
-; RV64-BITS-512-NEXT: vrgather.vv v28, v8, v12
-; RV64-BITS-512-NEXT: vmv4r.v v8, v28
+; RV64-BITS-512-NEXT: vid.v v12
+; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a0
+; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v16
+; RV64-BITS-512-NEXT: vmv4r.v v8, v12
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.experimental.vector.reverse.nxv32i8(<vscale x 32 x i8> %a)
ret <vscale x 32 x i8> %res
@@ -541,10 +541,10 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; RV32-BITS-512-NEXT: vid.v v28
-; RV32-BITS-512-NEXT: vrsub.vx v28, v28, a0
-; RV32-BITS-512-NEXT: vrgather.vv v20, v8, v28
-; RV32-BITS-512-NEXT: vrgather.vv v16, v12, v28
+; RV32-BITS-512-NEXT: vid.v v16
+; RV32-BITS-512-NEXT: vrsub.vx v24, v16, a0
+; RV32-BITS-512-NEXT: vrgather.vv v20, v8, v24
+; RV32-BITS-512-NEXT: vrgather.vv v16, v12, v24
; RV32-BITS-512-NEXT: vmv8r.v v8, v16
; RV32-BITS-512-NEXT: ret
;
@@ -580,10 +580,10 @@ define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; RV64-BITS-512-NEXT: vid.v v28
-; RV64-BITS-512-NEXT: vrsub.vx v28, v28, a0
-; RV64-BITS-512-NEXT: vrgather.vv v20, v8, v28
-; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v28
+; RV64-BITS-512-NEXT: vid.v v16
+; RV64-BITS-512-NEXT: vrsub.vx v24, v16, a0
+; RV64-BITS-512-NEXT: vrgather.vv v20, v8, v24
+; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v24
; RV64-BITS-512-NEXT: vmv8r.v v8, v16
; RV64-BITS-512-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.experimental.vector.reverse.nxv64i8(<vscale x 64 x i8> %a)
@@ -597,10 +597,10 @@ define <vscale x 1 x i16> @reverse_nxv1i16(<vscale x 1 x i16> %a) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.experimental.vector.reverse.nxv1i16(<vscale x 1 x i16> %a)
ret <vscale x 1 x i16> %res
@@ -613,10 +613,10 @@ define <vscale x 2 x i16> @reverse_nxv2i16(<vscale x 2 x i16> %a) {
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.experimental.vector.reverse.nxv2i16(<vscale x 2 x i16> %a)
ret <vscale x 2 x i16> %res
@@ -629,10 +629,10 @@ define <vscale x 4 x i16> @reverse_nxv4i16(<vscale x 4 x i16> %a) {
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.experimental.vector.reverse.nxv4i16(<vscale x 4 x i16> %a)
ret <vscale x 4 x i16> %res
@@ -644,10 +644,10 @@ define <vscale x 8 x i16> @reverse_nxv8i16(<vscale x 8 x i16> %a) {
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vrsub.vx v28, v26, a0
-; CHECK-NEXT: vrgather.vv v26, v8, v28
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vx v12, v10, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> %a)
ret <vscale x 8 x i16> %res
@@ -660,10 +660,10 @@ define <vscale x 16 x i16> @reverse_nxv16i16(<vscale x 16 x i16> %a) {
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vrsub.vx v12, v28, a0
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: vrsub.vx v16, v12, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.experimental.vector.reverse.nxv16i16(<vscale x 16 x i16> %a)
ret <vscale x 16 x i16> %res
@@ -692,10 +692,10 @@ define <vscale x 1 x i32> @reverse_nxv1i32(<vscale x 1 x i32> %a) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.experimental.vector.reverse.nxv1i32(<vscale x 1 x i32> %a)
ret <vscale x 1 x i32> %res
@@ -708,10 +708,10 @@ define <vscale x 2 x i32> @reverse_nxv2i32(<vscale x 2 x i32> %a) {
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.experimental.vector.reverse.nxv2i32(<vscale x 2 x i32> %a)
ret <vscale x 2 x i32> %res
@@ -724,10 +724,10 @@ define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) {
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vrsub.vx v28, v26, a0
-; CHECK-NEXT: vrgather.vv v26, v8, v28
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vx v12, v10, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
ret <vscale x 4 x i32> %res
@@ -739,10 +739,10 @@ define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) {
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vrsub.vx v12, v28, a0
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: vrsub.vx v16, v12, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32> %a)
ret <vscale x 8 x i32> %res
@@ -771,10 +771,10 @@ define <vscale x 1 x i64> @reverse_nxv1i64(<vscale x 1 x i64> %a) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.experimental.vector.reverse.nxv1i64(<vscale x 1 x i64> %a)
ret <vscale x 1 x i64> %res
@@ -787,10 +787,10 @@ define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) {
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vrsub.vx v28, v26, a0
-; CHECK-NEXT: vrgather.vv v26, v8, v28
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vx v12, v10, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64> %a)
ret <vscale x 2 x i64> %res
@@ -803,10 +803,10 @@ define <vscale x 4 x i64> @reverse_nxv4i64(<vscale x 4 x i64> %a) {
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vrsub.vx v12, v28, a0
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: vrsub.vx v16, v12, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.experimental.vector.reverse.nxv4i64(<vscale x 4 x i64> %a)
ret <vscale x 4 x i64> %res
@@ -838,10 +838,10 @@ define <vscale x 1 x half> @reverse_nxv1f16(<vscale x 1 x half> %a) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 1 x half> @llvm.experimental.vector.reverse.nxv1f16(<vscale x 1 x half> %a)
ret <vscale x 1 x half> %res
@@ -854,10 +854,10 @@ define <vscale x 2 x half> @reverse_nxv2f16(<vscale x 2 x half> %a) {
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.reverse.nxv2f16(<vscale x 2 x half> %a)
ret <vscale x 2 x half> %res
@@ -870,10 +870,10 @@ define <vscale x 4 x half> @reverse_nxv4f16(<vscale x 4 x half> %a) {
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.reverse.nxv4f16(<vscale x 4 x half> %a)
ret <vscale x 4 x half> %res
@@ -885,10 +885,10 @@ define <vscale x 8 x half> @reverse_nxv8f16(<vscale x 8 x half> %a) {
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vrsub.vx v28, v26, a0
-; CHECK-NEXT: vrgather.vv v26, v8, v28
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vx v12, v10, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half> %a)
ret <vscale x 8 x half> %res
@@ -901,10 +901,10 @@ define <vscale x 16 x half> @reverse_nxv16f16(<vscale x 16 x half> %a) {
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vrsub.vx v12, v28, a0
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: vrsub.vx v16, v12, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%res = call <vscale x 16 x half> @llvm.experimental.vector.reverse.nxv16f16(<vscale x 16 x half> %a)
ret <vscale x 16 x half> %res
@@ -933,10 +933,10 @@ define <vscale x 1 x float> @reverse_nxv1f32(<vscale x 1 x float> %a) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 1 x float> @llvm.experimental.vector.reverse.nxv1f32(<vscale x 1 x float> %a)
ret <vscale x 1 x float> %res
@@ -949,10 +949,10 @@ define <vscale x 2 x float> @reverse_nxv2f32(<vscale x 2 x float> %a) {
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 2 x float> @llvm.experimental.vector.reverse.nxv2f32(<vscale x 2 x float> %a)
ret <vscale x 2 x float> %res
@@ -965,10 +965,10 @@ define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) {
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vrsub.vx v28, v26, a0
-; CHECK-NEXT: vrgather.vv v26, v8, v28
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vx v12, v10, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %a)
ret <vscale x 4 x float> %res
@@ -980,10 +980,10 @@ define <vscale x 8 x float> @reverse_nxv8f32(<vscale x 8 x float> %a) {
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vrsub.vx v12, v28, a0
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: vrsub.vx v16, v12, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.experimental.vector.reverse.nxv8f32(<vscale x 8 x float> %a)
ret <vscale x 8 x float> %res
@@ -1012,10 +1012,10 @@ define <vscale x 1 x double> @reverse_nxv1f64(<vscale x 1 x double> %a) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vrsub.vx v26, v25, a0
-; CHECK-NEXT: vrgather.vv v25, v8, v26
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vid.v v9
+; CHECK-NEXT: vrsub.vx v10, v9, a0
+; CHECK-NEXT: vrgather.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%res = call <vscale x 1 x double> @llvm.experimental.vector.reverse.nxv1f64(<vscale x 1 x double> %a)
ret <vscale x 1 x double> %res
@@ -1028,10 +1028,10 @@ define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) {
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vrsub.vx v28, v26, a0
-; CHECK-NEXT: vrgather.vv v26, v8, v28
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vrsub.vx v12, v10, a0
+; CHECK-NEXT: vrgather.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%res = call <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double> %a)
ret <vscale x 2 x double> %res
@@ -1044,10 +1044,10 @@ define <vscale x 4 x double> @reverse_nxv4f64(<vscale x 4 x double> %a) {
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vrsub.vx v12, v28, a0
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: vrsub.vx v16, v12, a0
+; CHECK-NEXT: vrgather.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.experimental.vector.reverse.nxv4f64(<vscale x 4 x double> %a)
ret <vscale x 4 x double> %res
diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
index c37a03a7cc56a..2e4feee53adab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
@@ -20,14 +20,14 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O0-NEXT: addi a1, a1, 16
; SPILL-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; SPILL-O0-NEXT: vfadd.vv v25, v8, v9
+; SPILL-O0-NEXT: vfadd.vv v8, v8, v9
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts at plt
; SPILL-O0-NEXT: addi a1, sp, 16
-; SPILL-O0-NEXT: vl1r.v v25, (a1) # Unknown-size Folded Reload
+; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 16
@@ -35,7 +35,7 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; SPILL-O0-NEXT: vfadd.vv v8, v8, v25
+; SPILL-O0-NEXT: vfadd.vv v8, v8, v9
; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: slli a0, a0, 1
; SPILL-O0-NEXT: add sp, sp, a0
@@ -55,11 +55,11 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O2-NEXT: addi a1, sp, 8
; SPILL-O2-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; SPILL-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; SPILL-O2-NEXT: vfadd.vv v25, v8, v9
+; SPILL-O2-NEXT: vfadd.vv v9, v8, v9
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: add a0, sp, a0
; SPILL-O2-NEXT: addi a0, a0, 8
-; SPILL-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
; SPILL-O2-NEXT: lui a0, %hi(.L.str)
; SPILL-O2-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O2-NEXT: call puts at plt
@@ -67,10 +67,10 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: add a0, sp, a0
; SPILL-O2-NEXT: addi a0, a0, 8
-; SPILL-O2-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; SPILL-O2-NEXT: addi a0, sp, 8
-; SPILL-O2-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload
-; SPILL-O2-NEXT: vfadd.vv v8, v26, v25
+; SPILL-O2-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT: vfadd.vv v8, v9, v8
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: slli a0, a0, 1
; SPILL-O2-NEXT: add sp, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
index 2855d7c0cc979..f3bb908cc8ad6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
@@ -12,9 +12,9 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(i32* %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv1r.v v25, v1
+; SPILL-O0-NEXT: vmv1r.v v8, v1
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -66,9 +66,9 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(i32* %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv1r.v v25, v1
+; SPILL-O0-NEXT: vmv1r.v v8, v1
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -121,9 +121,9 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(i32* %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv2r.v v26, v2
+; SPILL-O0-NEXT: vmv2r.v v8, v2
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -179,9 +179,9 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(i32* %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv4r.v v28, v4
+; SPILL-O0-NEXT: vmv4r.v v8, v4
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs4r.v v28, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -237,9 +237,9 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(i32* %base, i32 %vl) nounwind
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; SPILL-O0-NEXT: vlseg3e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv2r.v v26, v2
+; SPILL-O0-NEXT: vmv2r.v v8, v2
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
index b14bc1a696b2b..aa8ffefdf9300 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
@@ -20,14 +20,14 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O0-NEXT: addi a1, a1, 24
; SPILL-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; SPILL-O0-NEXT: vfadd.vv v25, v8, v9
+; SPILL-O0-NEXT: vfadd.vv v8, v8, v9
; SPILL-O0-NEXT: addi a0, sp, 24
-; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts at plt
; SPILL-O0-NEXT: addi a1, sp, 24
-; SPILL-O0-NEXT: vl1r.v v25, (a1) # Unknown-size Folded Reload
+; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 24
@@ -35,7 +35,7 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; SPILL-O0-NEXT: vfadd.vv v8, v8, v25
+; SPILL-O0-NEXT: vfadd.vv v8, v8, v9
; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: slli a0, a0, 1
; SPILL-O0-NEXT: add sp, sp, a0
@@ -55,11 +55,11 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O2-NEXT: addi a1, sp, 16
; SPILL-O2-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; SPILL-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; SPILL-O2-NEXT: vfadd.vv v25, v8, v9
+; SPILL-O2-NEXT: vfadd.vv v9, v8, v9
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: add a0, sp, a0
; SPILL-O2-NEXT: addi a0, a0, 16
-; SPILL-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
; SPILL-O2-NEXT: lui a0, %hi(.L.str)
; SPILL-O2-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O2-NEXT: call puts at plt
@@ -67,10 +67,10 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: add a0, sp, a0
; SPILL-O2-NEXT: addi a0, a0, 16
-; SPILL-O2-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; SPILL-O2-NEXT: addi a0, sp, 16
-; SPILL-O2-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload
-; SPILL-O2-NEXT: vfadd.vv v8, v26, v25
+; SPILL-O2-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT: vfadd.vv v8, v9, v8
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: slli a0, a0, 1
; SPILL-O2-NEXT: add sp, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
index 517c03772df3e..0b0b29861bf77 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
@@ -12,9 +12,9 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(i32* %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv1r.v v25, v1
+; SPILL-O0-NEXT: vmv1r.v v8, v1
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -66,9 +66,9 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(i32* %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv1r.v v25, v1
+; SPILL-O0-NEXT: vmv1r.v v8, v1
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -121,9 +121,9 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(i32* %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv2r.v v26, v2
+; SPILL-O0-NEXT: vmv2r.v v8, v2
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -179,9 +179,9 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(i32* %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; SPILL-O0-NEXT: vlseg2e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv4r.v v28, v4
+; SPILL-O0-NEXT: vmv4r.v v8, v4
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs4r.v v28, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -237,9 +237,9 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(i32* %base, i64 %vl) nounwind
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; SPILL-O0-NEXT: vlseg3e32.v v0, (a0)
-; SPILL-O0-NEXT: vmv2r.v v26, v2
+; SPILL-O0-NEXT: vmv2r.v v8, v2
; SPILL-O0-NEXT: addi a0, sp, 16
-; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill
+; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: #APP
; SPILL-O0-NEXT: #NO_APP
; SPILL-O0-NEXT: addi a0, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
index ba7905f9c0f32..192a5d18c4156 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
@@ -20,13 +20,13 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: sub a2, s0, a2
; CHECK-NEXT: addi a2, a2, -32
-; CHECK-NEXT: vl1re64.v v25, (a2)
+; CHECK-NEXT: vl1re64.v v8, (a2)
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 1
; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub a2, s0, a2
; CHECK-NEXT: addi a2, a2, -32
-; CHECK-NEXT: vl2re64.v v26, (a2)
+; CHECK-NEXT: vl2re64.v v8, (a2)
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: lw a0, 0(a0)
@@ -64,9 +64,9 @@ define void @rvv_overaligned() nounwind {
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 112
-; CHECK-NEXT: vl1re64.v v25, (a0)
+; CHECK-NEXT: vl1re64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 112
-; CHECK-NEXT: vl2re64.v v26, (a0)
+; CHECK-NEXT: vl2re64.v v8, (a0)
; CHECK-NEXT: lw a0, 64(sp)
; CHECK-NEXT: addi sp, s0, -128
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
@@ -108,9 +108,9 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: add a2, s1, a2
; CHECK-NEXT: addi a2, a2, 104
-; CHECK-NEXT: vl1re64.v v25, (a2)
+; CHECK-NEXT: vl1re64.v v8, (a2)
; CHECK-NEXT: addi a2, s1, 104
-; CHECK-NEXT: vl2re64.v v26, (a2)
+; CHECK-NEXT: vl2re64.v v8, (a2)
; CHECK-NEXT: lw a2, 64(s1)
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
index fe14dd6ea6142..e645593810308 100644
--- a/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
@@ -7,10 +7,10 @@ define <vscale x 2 x i32> @saddo_nvx2i32(<vscale x 2 x i32> %x, <vscale x 2 x i3
; CHECK-LABEL: saddo_nvx2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsadd.vv v25, v8, v9
-; CHECK-NEXT: vadd.vv v26, v8, v9
-; CHECK-NEXT: vmsne.vv v0, v26, v25
-; CHECK-NEXT: vmerge.vim v8, v26, 0, v0
+; CHECK-NEXT: vsadd.vv v10, v8, v9
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vv v0, v8, v10
+; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
%b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/select-fp.ll b/llvm/test/CodeGen/RISCV/rvv/select-fp.ll
index ed49db889f817..936aa1750b0d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/select-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/select-fp.ll
@@ -8,8 +8,8 @@ define <vscale x 1 x half> @select_nxv1f16(i1 zeroext %c, <vscale x 1 x half> %a
; CHECK-LABEL: select_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -22,8 +22,8 @@ define <vscale x 1 x half> @selectcc_nxv1f16(half %a, half %b, <vscale x 1 x hal
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -36,8 +36,8 @@ define <vscale x 2 x half> @select_nxv2f16(i1 zeroext %c, <vscale x 2 x half> %a
; CHECK-LABEL: select_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -50,8 +50,8 @@ define <vscale x 2 x half> @selectcc_nxv2f16(half %a, half %b, <vscale x 2 x hal
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -64,8 +64,8 @@ define <vscale x 4 x half> @select_nxv4f16(i1 zeroext %c, <vscale x 4 x half> %a
; CHECK-LABEL: select_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -78,8 +78,8 @@ define <vscale x 4 x half> @selectcc_nxv4f16(half %a, half %b, <vscale x 4 x hal
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -92,8 +92,8 @@ define <vscale x 8 x half> @select_nxv8f16(i1 zeroext %c, <vscale x 8 x half> %a
; CHECK-LABEL: select_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -106,8 +106,8 @@ define <vscale x 8 x half> @selectcc_nxv8f16(half %a, half %b, <vscale x 8 x hal
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -120,8 +120,8 @@ define <vscale x 16 x half> @select_nxv16f16(i1 zeroext %c, <vscale x 16 x half>
; CHECK-LABEL: select_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -134,8 +134,8 @@ define <vscale x 16 x half> @selectcc_nxv16f16(half %a, half %b, <vscale x 16 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -148,8 +148,8 @@ define <vscale x 32 x half> @select_nxv32f16(i1 zeroext %c, <vscale x 32 x half>
; CHECK-LABEL: select_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -162,8 +162,8 @@ define <vscale x 32 x half> @selectcc_nxv32f16(half %a, half %b, <vscale x 32 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -176,8 +176,8 @@ define <vscale x 1 x float> @select_nxv1f32(i1 zeroext %c, <vscale x 1 x float>
; CHECK-LABEL: select_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -190,8 +190,8 @@ define <vscale x 1 x float> @selectcc_nxv1f32(float %a, float %b, <vscale x 1 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -204,8 +204,8 @@ define <vscale x 2 x float> @select_nxv2f32(i1 zeroext %c, <vscale x 2 x float>
; CHECK-LABEL: select_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -218,8 +218,8 @@ define <vscale x 2 x float> @selectcc_nxv2f32(float %a, float %b, <vscale x 2 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -232,8 +232,8 @@ define <vscale x 4 x float> @select_nxv4f32(i1 zeroext %c, <vscale x 4 x float>
; CHECK-LABEL: select_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -246,8 +246,8 @@ define <vscale x 4 x float> @selectcc_nxv4f32(float %a, float %b, <vscale x 4 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -260,8 +260,8 @@ define <vscale x 8 x float> @select_nxv8f32(i1 zeroext %c, <vscale x 8 x float>
; CHECK-LABEL: select_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -274,8 +274,8 @@ define <vscale x 8 x float> @selectcc_nxv8f32(float %a, float %b, <vscale x 8 x
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -288,8 +288,8 @@ define <vscale x 16 x float> @select_nxv16f32(i1 zeroext %c, <vscale x 16 x floa
; CHECK-LABEL: select_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -302,8 +302,8 @@ define <vscale x 16 x float> @selectcc_nxv16f32(float %a, float %b, <vscale x 16
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -316,8 +316,8 @@ define <vscale x 1 x double> @select_nxv1f64(i1 zeroext %c, <vscale x 1 x double
; CHECK-LABEL: select_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -330,8 +330,8 @@ define <vscale x 1 x double> @selectcc_nxv1f64(double %a, double %b, <vscale x 1
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -344,8 +344,8 @@ define <vscale x 2 x double> @select_nxv2f64(i1 zeroext %c, <vscale x 2 x double
; CHECK-LABEL: select_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -358,8 +358,8 @@ define <vscale x 2 x double> @selectcc_nxv2f64(double %a, double %b, <vscale x 2
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -372,8 +372,8 @@ define <vscale x 4 x double> @select_nxv4f64(i1 zeroext %c, <vscale x 4 x double
; CHECK-LABEL: select_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -386,8 +386,8 @@ define <vscale x 4 x double> @selectcc_nxv4f64(double %a, double %b, <vscale x 4
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -400,8 +400,8 @@ define <vscale x 8 x double> @select_nxv8f64(i1 zeroext %c, <vscale x 8 x double
; CHECK-LABEL: select_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -414,8 +414,8 @@ define <vscale x 8 x double> @selectcc_nxv8f64(double %a, double %b, <vscale x 8
; CHECK: # %bb.0:
; CHECK-NEXT: feq.d a0, fa0, fa1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/select-int.ll b/llvm/test/CodeGen/RISCV/rvv/select-int.ll
index 52fd26c19be55..8c6ba3106b9b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/select-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/select-int.ll
@@ -8,11 +8,11 @@ define <vscale x 1 x i1> @select_nxv1i1(i1 zeroext %c, <vscale x 1 x i1> %a, <vs
; CHECK-LABEL: select_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b
ret <vscale x 1 x i1> %v
@@ -24,11 +24,11 @@ define <vscale x 1 x i1> @selectcc_nxv1i1(i1 signext %a, i1 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <vscale x 1 x i1> %c, <vscale x 1 x i1> %d
@@ -39,11 +39,11 @@ define <vscale x 2 x i1> @select_nxv2i1(i1 zeroext %c, <vscale x 2 x i1> %a, <vs
; CHECK-LABEL: select_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b
ret <vscale x 2 x i1> %v
@@ -55,11 +55,11 @@ define <vscale x 2 x i1> @selectcc_nxv2i1(i1 signext %a, i1 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <vscale x 2 x i1> %c, <vscale x 2 x i1> %d
@@ -70,11 +70,11 @@ define <vscale x 4 x i1> @select_nxv4i1(i1 zeroext %c, <vscale x 4 x i1> %a, <vs
; CHECK-LABEL: select_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b
ret <vscale x 4 x i1> %v
@@ -86,11 +86,11 @@ define <vscale x 4 x i1> @selectcc_nxv4i1(i1 signext %a, i1 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <vscale x 4 x i1> %c, <vscale x 4 x i1> %d
@@ -101,11 +101,11 @@ define <vscale x 8 x i1> @select_nxv8i1(i1 zeroext %c, <vscale x 8 x i1> %a, <vs
; CHECK-LABEL: select_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b
ret <vscale x 8 x i1> %v
@@ -117,11 +117,11 @@ define <vscale x 8 x i1> @selectcc_nxv8i1(i1 signext %a, i1 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vi v9, v9, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <vscale x 8 x i1> %c, <vscale x 8 x i1> %d
@@ -132,11 +132,11 @@ define <vscale x 16 x i1> @select_nxv16i1(i1 zeroext %c, <vscale x 16 x i1> %a,
; CHECK-LABEL: select_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v9, v10, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b
ret <vscale x 16 x i1> %v
@@ -148,11 +148,11 @@ define <vscale x 16 x i1> @selectcc_nxv16i1(i1 signext %a, i1 signext %b, <vscal
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v9, v10, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d
@@ -163,11 +163,11 @@ define <vscale x 32 x i1> @select_nxv32i1(i1 zeroext %c, <vscale x 32 x i1> %a,
; CHECK-LABEL: select_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v25, v28, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v9, v12, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 32 x i1> %a, <vscale x 32 x i1> %b
ret <vscale x 32 x i1> %v
@@ -179,11 +179,11 @@ define <vscale x 32 x i1> @selectcc_nxv32i1(i1 signext %a, i1 signext %b, <vscal
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v25, v28, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v9, v12, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <vscale x 32 x i1> %c, <vscale x 32 x i1> %d
@@ -195,10 +195,10 @@ define <vscale x 64 x i1> @select_nxv64i1(i1 zeroext %c, <vscale x 64 x i1> %a,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsne.vi v25, v16, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmsne.vi v9, v16, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 64 x i1> %a, <vscale x 64 x i1> %b
ret <vscale x 64 x i1> %v
@@ -211,10 +211,10 @@ define <vscale x 64 x i1> @selectcc_nxv64i1(i1 signext %a, i1 signext %b, <vscal
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmsne.vi v25, v16, 0
-; CHECK-NEXT: vmandnot.mm v26, v8, v25
-; CHECK-NEXT: vmand.mm v25, v0, v25
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmsne.vi v9, v16, 0
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%cmp = icmp ne i1 %a, %b
%v = select i1 %cmp, <vscale x 64 x i1> %c, <vscale x 64 x i1> %d
@@ -225,8 +225,8 @@ define <vscale x 1 x i8> @select_nxv1i8(i1 zeroext %c, <vscale x 1 x i8> %a, <vs
; CHECK-LABEL: select_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b
@@ -239,8 +239,8 @@ define <vscale x 1 x i8> @selectcc_nxv1i8(i8 signext %a, i8 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -252,8 +252,8 @@ define <vscale x 2 x i8> @select_nxv2i8(i1 zeroext %c, <vscale x 2 x i8> %a, <vs
; CHECK-LABEL: select_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b
@@ -266,8 +266,8 @@ define <vscale x 2 x i8> @selectcc_nxv2i8(i8 signext %a, i8 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -279,8 +279,8 @@ define <vscale x 4 x i8> @select_nxv4i8(i1 zeroext %c, <vscale x 4 x i8> %a, <vs
; CHECK-LABEL: select_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b
@@ -293,8 +293,8 @@ define <vscale x 4 x i8> @selectcc_nxv4i8(i8 signext %a, i8 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -306,8 +306,8 @@ define <vscale x 8 x i8> @select_nxv8i8(i1 zeroext %c, <vscale x 8 x i8> %a, <vs
; CHECK-LABEL: select_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b
@@ -320,8 +320,8 @@ define <vscale x 8 x i8> @selectcc_nxv8i8(i8 signext %a, i8 signext %b, <vscale
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -333,8 +333,8 @@ define <vscale x 16 x i8> @select_nxv16i8(i1 zeroext %c, <vscale x 16 x i8> %a,
; CHECK-LABEL: select_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
@@ -347,8 +347,8 @@ define <vscale x 16 x i8> @selectcc_nxv16i8(i8 signext %a, i8 signext %b, <vscal
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -360,8 +360,8 @@ define <vscale x 32 x i8> @select_nxv32i8(i1 zeroext %c, <vscale x 32 x i8> %a,
; CHECK-LABEL: select_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b
@@ -374,8 +374,8 @@ define <vscale x 32 x i8> @selectcc_nxv32i8(i8 signext %a, i8 signext %b, <vscal
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i8 %a, %b
@@ -414,8 +414,8 @@ define <vscale x 1 x i16> @select_nxv1i16(i1 zeroext %c, <vscale x 1 x i16> %a,
; CHECK-LABEL: select_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -429,8 +429,8 @@ define <vscale x 1 x i16> @selectcc_nxv1i16(i16 signext %a, i16 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -443,8 +443,8 @@ define <vscale x 2 x i16> @select_nxv2i16(i1 zeroext %c, <vscale x 2 x i16> %a,
; CHECK-LABEL: select_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -458,8 +458,8 @@ define <vscale x 2 x i16> @selectcc_nxv2i16(i16 signext %a, i16 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -472,8 +472,8 @@ define <vscale x 4 x i16> @select_nxv4i16(i1 zeroext %c, <vscale x 4 x i16> %a,
; CHECK-LABEL: select_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -487,8 +487,8 @@ define <vscale x 4 x i16> @selectcc_nxv4i16(i16 signext %a, i16 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -501,8 +501,8 @@ define <vscale x 8 x i16> @select_nxv8i16(i1 zeroext %c, <vscale x 8 x i16> %a,
; CHECK-LABEL: select_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -516,8 +516,8 @@ define <vscale x 8 x i16> @selectcc_nxv8i16(i16 signext %a, i16 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -530,8 +530,8 @@ define <vscale x 16 x i16> @select_nxv16i16(i1 zeroext %c, <vscale x 16 x i16> %
; CHECK-LABEL: select_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -545,8 +545,8 @@ define <vscale x 16 x i16> @selectcc_nxv16i16(i16 signext %a, i16 signext %b, <v
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -559,8 +559,8 @@ define <vscale x 32 x i16> @select_nxv32i16(i1 zeroext %c, <vscale x 32 x i16> %
; CHECK-LABEL: select_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -574,8 +574,8 @@ define <vscale x 32 x i16> @selectcc_nxv32i16(i16 signext %a, i16 signext %b, <v
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -588,8 +588,8 @@ define <vscale x 1 x i32> @select_nxv1i32(i1 zeroext %c, <vscale x 1 x i32> %a,
; CHECK-LABEL: select_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -603,8 +603,8 @@ define <vscale x 1 x i32> @selectcc_nxv1i32(i32 signext %a, i32 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -617,8 +617,8 @@ define <vscale x 2 x i32> @select_nxv2i32(i1 zeroext %c, <vscale x 2 x i32> %a,
; CHECK-LABEL: select_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -632,8 +632,8 @@ define <vscale x 2 x i32> @selectcc_nxv2i32(i32 signext %a, i32 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -646,8 +646,8 @@ define <vscale x 4 x i32> @select_nxv4i32(i1 zeroext %c, <vscale x 4 x i32> %a,
; CHECK-LABEL: select_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -661,8 +661,8 @@ define <vscale x 4 x i32> @selectcc_nxv4i32(i32 signext %a, i32 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -675,8 +675,8 @@ define <vscale x 8 x i32> @select_nxv8i32(i1 zeroext %c, <vscale x 8 x i32> %a,
; CHECK-LABEL: select_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -690,8 +690,8 @@ define <vscale x 8 x i32> @selectcc_nxv8i32(i32 signext %a, i32 signext %b, <vsc
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -704,8 +704,8 @@ define <vscale x 16 x i32> @select_nxv16i32(i1 zeroext %c, <vscale x 16 x i32> %
; CHECK-LABEL: select_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -719,8 +719,8 @@ define <vscale x 16 x i32> @selectcc_nxv16i32(i32 signext %a, i32 signext %b, <v
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -733,8 +733,8 @@ define <vscale x 1 x i64> @select_nxv1i64(i1 zeroext %c, <vscale x 1 x i64> %a,
; CHECK-LABEL: select_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
@@ -750,8 +750,8 @@ define <vscale x 1 x i64> @selectcc_nxv1i64(i64 signext %a, i64 signext %b, <vsc
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: ret
@@ -761,8 +761,8 @@ define <vscale x 1 x i64> @selectcc_nxv1i64(i64 signext %a, i64 signext %b, <vsc
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v10, a0
+; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: ret
@@ -775,8 +775,8 @@ define <vscale x 2 x i64> @select_nxv2i64(i1 zeroext %c, <vscale x 2 x i64> %a,
; CHECK-LABEL: select_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
@@ -792,8 +792,8 @@ define <vscale x 2 x i64> @selectcc_nxv2i64(i64 signext %a, i64 signext %b, <vsc
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v12, a0
+; RV32-NEXT: vmsne.vi v0, v12, 0
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32-NEXT: vmerge.vvm v8, v10, v8, v0
; RV32-NEXT: ret
@@ -803,8 +803,8 @@ define <vscale x 2 x i64> @selectcc_nxv2i64(i64 signext %a, i64 signext %b, <vsc
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v12, a0
+; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
; RV64-NEXT: ret
@@ -817,8 +817,8 @@ define <vscale x 4 x i64> @select_nxv4i64(i1 zeroext %c, <vscale x 4 x i64> %a,
; CHECK-LABEL: select_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
@@ -834,8 +834,8 @@ define <vscale x 4 x i64> @selectcc_nxv4i64(i64 signext %a, i64 signext %b, <vsc
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vmsne.vi v0, v16, 0
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vmerge.vvm v8, v12, v8, v0
; RV32-NEXT: ret
@@ -845,8 +845,8 @@ define <vscale x 4 x i64> @selectcc_nxv4i64(i64 signext %a, i64 signext %b, <vsc
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vmsne.vi v0, v16, 0
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64-NEXT: vmerge.vvm v8, v12, v8, v0
; RV64-NEXT: ret
@@ -859,8 +859,8 @@ define <vscale x 8 x i64> @select_nxv8i64(i1 zeroext %c, <vscale x 8 x i64> %a,
; CHECK-LABEL: select_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
@@ -876,8 +876,8 @@ define <vscale x 8 x i64> @selectcc_nxv8i64(i64 signext %a, i64 signext %b, <vsc
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0
; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
-; RV32-NEXT: vmsne.vi v0, v25, 0
+; RV32-NEXT: vmv.v.x v24, a0
+; RV32-NEXT: vmsne.vi v0, v24, 0
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
; RV32-NEXT: ret
@@ -887,8 +887,8 @@ define <vscale x 8 x i64> @selectcc_nxv8i64(i64 signext %a, i64 signext %b, <vsc
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
-; RV64-NEXT: vmsne.vi v0, v25, 0
+; RV64-NEXT: vmv.v.x v24, a0
+; RV64-NEXT: vmsne.vi v0, v24, 0
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/select-sra.ll b/llvm/test/CodeGen/RISCV/rvv/select-sra.ll
index 50120961b15b4..f1c4bddb26cd7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/select-sra.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/select-sra.ll
@@ -11,10 +11,10 @@ define <4 x i32> @vselect_of_consts(<4 x i1> %cc) {
; RV32-NEXT: lui a0, 284280
; RV32-NEXT: addi a0, a0, 291
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v8, a0
; RV32-NEXT: lui a0, 214376
; RV32-NEXT: addi a0, a0, -2030
-; RV32-NEXT: vmerge.vxm v8, v25, a0, v0
+; RV32-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-NEXT: ret
;
; RV64-LABEL: vselect_of_consts:
@@ -22,10 +22,10 @@ define <4 x i32> @vselect_of_consts(<4 x i1> %cc) {
; RV64-NEXT: lui a0, 284280
; RV64-NEXT: addiw a0, a0, 291
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: lui a0, 214376
; RV64-NEXT: addiw a0, a0, -2030
-; RV64-NEXT: vmerge.vxm v8, v25, a0, v0
+; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-NEXT: ret
%v = select <4 x i1> %cc, <4 x i32> <i32 878082066, i32 878082066, i32 878082066, i32 878082066>, <4 x i32> <i32 1164411171, i32 1164411171, i32 1164411171, i32 1164411171>
ret <4 x i32> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
index c4ee90b67ea5a..c1c124624f6e1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
@@ -289,9 +289,9 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_one_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmflt.vv v26, v10, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vmflt.vv v13, v10, v8
+; CHECK-NEXT: vmor.mm v0, v13, v12
; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -301,9 +301,9 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_one_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmfgt.vf v11, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -315,9 +315,9 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_one_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmflt.vf v11, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -351,9 +351,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ord_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v10, v10
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v12, v10, v10
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -363,10 +363,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v25, v26, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfeq.vf v12, v10, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -378,10 +378,10 @@ define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ord_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v25, v26, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfeq.vf v12, v10, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -393,9 +393,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <v
; CHECK-LABEL: fcmp_ord_vv_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v10, v10
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v12, v10, v10
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -405,10 +405,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v25, v26, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfeq.vf v12, v10, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -420,9 +420,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ueq_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmflt.vv v26, v10, v8
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vmflt.vv v13, v10, v8
+; CHECK-NEXT: vmnor.mm v0, v13, v12
; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -432,9 +432,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmfgt.vf v11, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -446,9 +446,9 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmflt.vf v11, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -482,8 +482,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ugt_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v12, v8, v10
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -493,8 +493,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -506,8 +506,8 @@ define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ugt_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -541,8 +541,8 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_uge_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -552,8 +552,8 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -565,8 +565,8 @@ define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uge_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -600,8 +600,8 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ult_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v12, v10, v8
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -611,8 +611,8 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -624,8 +624,8 @@ define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ult_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -659,8 +659,8 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ule_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v12, v10, v8
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -670,8 +670,8 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -683,8 +683,8 @@ define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ule_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -774,9 +774,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_uno_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v10, v10
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v12, v10, v10
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -786,10 +786,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v25, v26, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfne.vf v12, v10, fa0
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -801,10 +801,10 @@ define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uno_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v25, v26, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfne.vf v12, v10, fa0
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -816,9 +816,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <v
; CHECK-LABEL: fcmp_uno_vv_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v10, v10
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v12, v10, v10
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -828,10 +828,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v25, v26, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfne.vf v12, v10, fa0
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -1123,9 +1123,9 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_one_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmflt.vv v26, v12, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vmflt.vv v17, v12, v8
+; CHECK-NEXT: vmor.mm v0, v17, v16
; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1135,9 +1135,9 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_one_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmfgt.vf v13, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1149,9 +1149,9 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_one_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmflt.vf v13, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1185,9 +1185,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ord_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v12, v12
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v16, v12, v12
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1197,10 +1197,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ord_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfeq.vf v25, v28, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfeq.vf v16, v12, fa0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1212,10 +1212,10 @@ define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ord_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfeq.vf v25, v28, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfeq.vf v16, v12, fa0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1227,9 +1227,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <
; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v12, v12
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v16, v12, v12
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1239,10 +1239,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f32_nonans(<vscale x 8 x float> %va, f
; CHECK-LABEL: fcmp_ord_vf_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfeq.vf v25, v28, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfeq.vf v16, v12, fa0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1254,9 +1254,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ueq_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmflt.vv v26, v12, v8
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vmflt.vv v17, v12, v8
+; CHECK-NEXT: vmnor.mm v0, v17, v16
; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1266,9 +1266,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ueq_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmfgt.vf v13, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1280,9 +1280,9 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ueq_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmflt.vf v13, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1316,8 +1316,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ugt_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v16, v8, v12
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1327,8 +1327,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ugt_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1340,8 +1340,8 @@ define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ugt_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1375,8 +1375,8 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_uge_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1386,8 +1386,8 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uge_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1399,8 +1399,8 @@ define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uge_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1434,8 +1434,8 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ult_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v16, v12, v8
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1445,8 +1445,8 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ult_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1458,8 +1458,8 @@ define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ult_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1493,8 +1493,8 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ule_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v16, v12, v8
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1504,8 +1504,8 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ule_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1517,8 +1517,8 @@ define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ule_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1608,9 +1608,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_uno_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v12, v12
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v16, v12, v12
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1620,10 +1620,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uno_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfne.vf v25, v28, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfne.vf v16, v12, fa0
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1635,10 +1635,10 @@ define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uno_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfne.vf v25, v28, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfne.vf v16, v12, fa0
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1650,9 +1650,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <
; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v12, v12
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v16, v12, v12
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1662,10 +1662,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f32_nonans(<vscale x 8 x float> %va, f
; CHECK-LABEL: fcmp_uno_vf_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfne.vf v25, v28, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfne.vf v16, v12, fa0
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1957,9 +1957,9 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_one_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmflt.vv v26, v16, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmflt.vv v25, v16, v8
+; CHECK-NEXT: vmor.mm v0, v25, v24
; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1969,9 +1969,9 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_one_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmfgt.vf v17, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -1983,9 +1983,9 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_one_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmflt.vf v17, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2019,9 +2019,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ord_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v16, v16
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2032,9 +2032,9 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v25, v16, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2047,9 +2047,9 @@ define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v25, v16, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v25, v26
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v24, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2061,9 +2061,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v16, v16
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2074,9 +2074,9 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v25, v16, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2088,9 +2088,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ueq_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmflt.vv v26, v16, v8
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmflt.vv v25, v16, v8
+; CHECK-NEXT: vmnor.mm v0, v25, v24
; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2100,9 +2100,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ueq_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmfgt.vf v17, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2114,9 +2114,9 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ueq_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmflt.vf v17, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2150,8 +2150,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ugt_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v16
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v24, v8, v16
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2161,8 +2161,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ugt_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2174,8 +2174,8 @@ define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ugt_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2209,8 +2209,8 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_uge_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2220,8 +2220,8 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_uge_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2233,8 +2233,8 @@ define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_uge_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2268,8 +2268,8 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ult_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v16, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v24, v16, v8
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2279,8 +2279,8 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ult_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2292,8 +2292,8 @@ define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ult_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2327,8 +2327,8 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ule_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v16, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v24, v16, v8
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2338,8 +2338,8 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ule_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2351,8 +2351,8 @@ define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ule_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2442,9 +2442,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_uno_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v16, v16
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v24, v16, v16
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2455,9 +2455,9 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v25, v16, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vf v24, v16, fa0
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2470,9 +2470,9 @@ define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v25, v16, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmfne.vf v24, v16, fa0
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v24, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2484,9 +2484,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v16, v16
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v24, v16, v16
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2497,9 +2497,9 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v25, v16, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vf v24, v16, fa0
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2514,13 +2514,13 @@ define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.d.w ft0, zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v25, v16, ft0
+; CHECK-NEXT: vmfeq.vf v24, v16, ft0
; CHECK-NEXT: vmfeq.vf v0, v8, ft0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v0, v25, a0
+; CHECK-NEXT: vslideup.vx v0, v24, a0
; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
ret <vscale x 16 x i1> %vc
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
index 6ddaa042f831d..572fe9d46d2dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
@@ -289,9 +289,9 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_one_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmflt.vv v26, v10, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vmflt.vv v13, v10, v8
+; CHECK-NEXT: vmor.mm v0, v13, v12
; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -301,9 +301,9 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_one_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmfgt.vf v11, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -315,9 +315,9 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_one_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmflt.vf v11, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -351,9 +351,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ord_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v10, v10
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v12, v10, v10
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -363,10 +363,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v25, v26, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfeq.vf v12, v10, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -378,10 +378,10 @@ define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ord_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v25, v26, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfeq.vf v12, v10, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -393,9 +393,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <v
; CHECK-LABEL: fcmp_ord_vv_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v10, v10
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v12, v10, v10
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -405,10 +405,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfeq.vf v25, v26, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfeq.vf v12, v10, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
+; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -420,9 +420,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ueq_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmflt.vv v26, v10, v8
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vmflt.vv v13, v10, v8
+; CHECK-NEXT: vmnor.mm v0, v13, v12
; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -432,9 +432,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmfgt.vf v11, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -446,9 +446,9 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmflt.vf v11, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v11, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -482,8 +482,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ugt_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v12, v8, v10
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -493,8 +493,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -506,8 +506,8 @@ define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ugt_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -541,8 +541,8 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_uge_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v12, v8, v10
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -552,8 +552,8 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -565,8 +565,8 @@ define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uge_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -600,8 +600,8 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ult_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v12, v10, v8
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -611,8 +611,8 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -624,8 +624,8 @@ define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ult_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -659,8 +659,8 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_ule_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v12, v10, v8
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -670,8 +670,8 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -683,8 +683,8 @@ define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_ule_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v10, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -774,9 +774,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-LABEL: fcmp_uno_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v10, v10
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v12, v10, v10
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -786,10 +786,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v25, v26, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfne.vf v12, v10, fa0
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -801,10 +801,10 @@ define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-LABEL: fcmp_uno_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v25, v26, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfne.vf v12, v10, fa0
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -816,9 +816,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <v
; CHECK-LABEL: fcmp_uno_vv_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v10, v10
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v12, v10, v10
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -828,10 +828,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vmfne.vf v25, v26, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vmfne.vf v12, v10, fa0
+; CHECK-NEXT: vmfne.vv v10, v8, v8
+; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -1123,9 +1123,9 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_one_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmflt.vv v26, v12, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vmflt.vv v17, v12, v8
+; CHECK-NEXT: vmor.mm v0, v17, v16
; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1135,9 +1135,9 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_one_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmfgt.vf v13, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1149,9 +1149,9 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_one_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmflt.vf v13, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1185,9 +1185,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ord_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v12, v12
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v16, v12, v12
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1197,10 +1197,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ord_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfeq.vf v25, v28, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfeq.vf v16, v12, fa0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1212,10 +1212,10 @@ define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ord_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfeq.vf v25, v28, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfeq.vf v16, v12, fa0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1227,9 +1227,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <
; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v12, v12
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v16, v12, v12
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1239,10 +1239,10 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f32_nonans(<vscale x 8 x float> %va, f
; CHECK-LABEL: fcmp_ord_vf_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfeq.vf v25, v28, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfeq.vf v16, v12, fa0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8
+; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1254,9 +1254,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ueq_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmflt.vv v26, v12, v8
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vmflt.vv v17, v12, v8
+; CHECK-NEXT: vmnor.mm v0, v17, v16
; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1266,9 +1266,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ueq_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmfgt.vf v13, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1280,9 +1280,9 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ueq_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmflt.vf v13, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v13, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1316,8 +1316,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ugt_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v16, v8, v12
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1327,8 +1327,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ugt_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1340,8 +1340,8 @@ define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ugt_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1375,8 +1375,8 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_uge_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v16, v8, v12
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1386,8 +1386,8 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uge_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1399,8 +1399,8 @@ define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uge_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1434,8 +1434,8 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ult_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v16, v12, v8
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1445,8 +1445,8 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ult_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1458,8 +1458,8 @@ define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ult_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1493,8 +1493,8 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_ule_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v16, v12, v8
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1504,8 +1504,8 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ule_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1517,8 +1517,8 @@ define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_ule_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v12, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1608,9 +1608,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: fcmp_uno_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v12, v12
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v16, v12, v12
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1620,10 +1620,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uno_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfne.vf v25, v28, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfne.vf v16, v12, fa0
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1635,10 +1635,10 @@ define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: fcmp_uno_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfne.vf v25, v28, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfne.vf v16, v12, fa0
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1650,9 +1650,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <
; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v12, v12
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v16, v12, v12
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1662,10 +1662,10 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f32_nonans(<vscale x 8 x float> %va, f
; CHECK-LABEL: fcmp_uno_vf_nxv8f32_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vmfne.vf v25, v28, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vmfne.vf v16, v12, fa0
+; CHECK-NEXT: vmfne.vv v12, v8, v8
+; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1957,9 +1957,9 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_one_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmflt.vv v26, v16, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmflt.vv v25, v16, v8
+; CHECK-NEXT: vmor.mm v0, v25, v24
; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -1969,9 +1969,9 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_one_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmfgt.vf v17, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -1983,9 +1983,9 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_one_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmflt.vf v17, v8, fa0
+; CHECK-NEXT: vmor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2019,9 +2019,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ord_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v16, v16
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2032,9 +2032,9 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v25, v16, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2047,9 +2047,9 @@ define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v25, v16, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v25, v26
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v24, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2061,9 +2061,9 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v16, v16
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2074,9 +2074,9 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfeq.vf v25, v16, fa0
-; CHECK-NEXT: vmfeq.vv v26, v8, v8
-; CHECK-NEXT: vmand.mm v0, v26, v25
+; CHECK-NEXT: vmfeq.vf v24, v16, fa0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8
+; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2088,9 +2088,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ueq_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmflt.vv v26, v16, v8
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmflt.vv v25, v16, v8
+; CHECK-NEXT: vmnor.mm v0, v25, v24
; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2100,9 +2100,9 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ueq_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmfgt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmfgt.vf v17, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2114,9 +2114,9 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ueq_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmflt.vf v26, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v26, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmflt.vf v17, v8, fa0
+; CHECK-NEXT: vmnor.mm v0, v17, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2150,8 +2150,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ugt_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v16
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v24, v8, v16
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2161,8 +2161,8 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ugt_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2174,8 +2174,8 @@ define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ugt_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2209,8 +2209,8 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_uge_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v16
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v24, v8, v16
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2220,8 +2220,8 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_uge_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2233,8 +2233,8 @@ define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_uge_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2268,8 +2268,8 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ult_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v16, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vv v24, v16, v8
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2279,8 +2279,8 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ult_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfge.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfge.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2292,8 +2292,8 @@ define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ult_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfle.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfle.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2327,8 +2327,8 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_ule_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v16, v8
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vv v24, v16, v8
+; CHECK-NEXT: vmnand.mm v0, v24, v24
; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2338,8 +2338,8 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ule_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmfgt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2351,8 +2351,8 @@ define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-LABEL: fcmp_ule_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmflt.vf v16, v8, fa0
+; CHECK-NEXT: vmnand.mm v0, v16, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2442,9 +2442,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-LABEL: fcmp_uno_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v16, v16
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v24, v16, v16
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2455,9 +2455,9 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v25, v16, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vf v24, v16, fa0
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2470,9 +2470,9 @@ define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v25, v16, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v25, v26
+; CHECK-NEXT: vmfne.vf v24, v16, fa0
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v24, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2484,9 +2484,9 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v16, v16
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vv v24, v16, v16
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc
@@ -2497,9 +2497,9 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64_nonans(<vscale x 8 x double> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
-; CHECK-NEXT: vmfne.vf v25, v16, fa0
-; CHECK-NEXT: vmfne.vv v26, v8, v8
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmfne.vf v24, v16, fa0
+; CHECK-NEXT: vmfne.vv v16, v8, v8
+; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -2514,13 +2514,13 @@ define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.d.x ft0, zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmfeq.vf v25, v16, ft0
+; CHECK-NEXT: vmfeq.vf v24, v16, ft0
; CHECK-NEXT: vmfeq.vf v0, v8, ft0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v0, v25, a0
+; CHECK-NEXT: vslideup.vx v0, v24, a0
; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
ret <vscale x 16 x i1> %vc
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
index bf7c9e218a2b8..2d6caeee8784f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
@@ -27,8 +27,8 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmseq.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmseq.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -98,8 +98,8 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -145,8 +145,8 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsltu.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -180,8 +180,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_uge_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -193,8 +193,8 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsleu.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -206,8 +206,8 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -16
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.i v9, -16
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -313,8 +313,8 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsltu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsltu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -435,8 +435,8 @@ define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ule_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -482,8 +482,8 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmslt.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -517,8 +517,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sge_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsle.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -530,8 +530,8 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsle.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -543,8 +543,8 @@ define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -16
-; CHECK-NEXT: vmsle.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.i v9, -16
+; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -626,8 +626,8 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmslt.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmslt.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -722,8 +722,8 @@ define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sle_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsle.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -769,8 +769,8 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmseq.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmseq.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -840,8 +840,8 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -887,8 +887,8 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsltu.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -922,8 +922,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_uge_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsleu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -935,8 +935,8 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsleu.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -948,8 +948,8 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -16
-; CHECK-NEXT: vmsleu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.i v10, -16
+; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1034,9 +1034,9 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i32 %vl) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i32 %vl)
%vc = icmp uge <vscale x 8 x i8> %va, %splat
@@ -1069,8 +1069,8 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsltu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsltu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1177,8 +1177,8 @@ define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ule_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsleu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1224,8 +1224,8 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmslt.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1259,8 +1259,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sge_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsle.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1272,8 +1272,8 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsle.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1285,8 +1285,8 @@ define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -16
-; CHECK-NEXT: vmsle.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.i v10, -16
+; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1368,8 +1368,8 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmslt.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmslt.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1464,8 +1464,8 @@ define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sle_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsle.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1511,8 +1511,8 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmseq.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmseq.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1582,8 +1582,8 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1629,8 +1629,8 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsltu.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1664,8 +1664,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_uge_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsleu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1677,8 +1677,8 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsleu.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1690,8 +1690,8 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, -16
-; CHECK-NEXT: vmsleu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.i v12, -16
+; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1797,8 +1797,8 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsltu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsltu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1905,8 +1905,8 @@ define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ule_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsleu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1952,8 +1952,8 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmslt.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1987,8 +1987,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sge_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsle.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2000,8 +2000,8 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsle.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2013,8 +2013,8 @@ define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, -16
-; CHECK-NEXT: vmsle.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.i v12, -16
+; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2096,8 +2096,8 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmslt.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmslt.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2192,8 +2192,8 @@ define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sle_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsle.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -3096,10 +3096,10 @@ define <vscale x 16 x i1> @icmp_eq_vi_nx16i64(<vscale x 16 x i64> %va) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v25, v16, 0
+; CHECK-NEXT: vmseq.vi v24, v16, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v0, v25, a0
+; CHECK-NEXT: vslideup.vx v0, v24, a0
; CHECK-NEXT: ret
%vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer
ret <vscale x 16 x i1> %vc
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
index 199c07c39c655..b83640584d115 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
@@ -27,8 +27,8 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmseq.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmseq.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -98,8 +98,8 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsne.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -145,8 +145,8 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsltu.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -180,8 +180,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_uge_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -193,8 +193,8 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsleu.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -206,8 +206,8 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -16
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.i v9, -16
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -292,9 +292,9 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, i64 %vl) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i64 %vl)
%vc = icmp uge <vscale x 8 x i8> %va, %splat
@@ -327,8 +327,8 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsltu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsltu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -449,8 +449,8 @@ define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ule_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -496,8 +496,8 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmslt.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -531,8 +531,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sge_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsle.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -544,8 +544,8 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsle.vv v0, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -557,8 +557,8 @@ define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -16
-; CHECK-NEXT: vmsle.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.i v9, -16
+; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -640,8 +640,8 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmslt.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmslt.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -736,8 +736,8 @@ define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sle_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsle.vv v0, v25, v8
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -783,8 +783,8 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmseq.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmseq.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -854,8 +854,8 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -901,8 +901,8 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsltu.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -936,8 +936,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_uge_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsleu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -949,8 +949,8 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsleu.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -962,8 +962,8 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -16
-; CHECK-NEXT: vmsleu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.i v10, -16
+; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1069,8 +1069,8 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsltu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsltu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1177,8 +1177,8 @@ define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ule_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsleu.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1224,8 +1224,8 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmslt.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1259,8 +1259,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sge_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsle.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1272,8 +1272,8 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v26
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsle.vv v0, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1285,8 +1285,8 @@ define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, -16
-; CHECK-NEXT: vmsle.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.i v10, -16
+; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1368,8 +1368,8 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmslt.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmslt.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1464,8 +1464,8 @@ define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sle_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsle.vv v0, v26, v8
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -1511,8 +1511,8 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmseq.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmseq.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1582,8 +1582,8 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsne.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1629,8 +1629,8 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsltu.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1664,8 +1664,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_uge_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsleu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1677,8 +1677,8 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsleu.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1690,8 +1690,8 @@ define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, -16
-; CHECK-NEXT: vmsleu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.i v12, -16
+; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1797,8 +1797,8 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsltu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsltu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1905,8 +1905,8 @@ define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ule_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsleu.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1952,8 +1952,8 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmslt.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -1987,8 +1987,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sge_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsle.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2000,8 +2000,8 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v28
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsle.vv v0, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2013,8 +2013,8 @@ define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, -16
-; CHECK-NEXT: vmsle.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.i v12, -16
+; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2096,8 +2096,8 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmslt.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmslt.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2192,8 +2192,8 @@ define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sle_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vmsle.vv v0, v28, v8
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -2950,10 +2950,10 @@ define <vscale x 16 x i1> @icmp_eq_vi_nx16i64(<vscale x 16 x i64> %va) {
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v25, v16, 0
+; CHECK-NEXT: vmseq.vi v24, v16, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vslideup.vx v0, v25, a0
+; CHECK-NEXT: vslideup.vx v0, v24, a0
; CHECK-NEXT: ret
%vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer
ret <vscale x 16 x i1> %vc
diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index 9d926ab64eba0..bc817b2b96f56 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -9,9 +9,9 @@ define void @sink_splat_mul(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB0_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vmul.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB0_1
@@ -45,9 +45,9 @@ define void @sink_splat_add(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB1_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB1_1
@@ -81,9 +81,9 @@ define void @sink_splat_sub(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB2_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vadd.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB2_1
@@ -117,9 +117,9 @@ define void @sink_splat_rsub(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB3_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vrsub.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vrsub.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB3_1
@@ -153,9 +153,9 @@ define void @sink_splat_and(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB4_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vand.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB4_1
@@ -189,9 +189,9 @@ define void @sink_splat_or(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB5_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vor.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB5_1
@@ -225,9 +225,9 @@ define void @sink_splat_xor(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB6_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vxor.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB6_1
@@ -272,10 +272,10 @@ define void @sink_splat_mul_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB7_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmul.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vmul.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB7_3
@@ -365,10 +365,10 @@ define void @sink_splat_add_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB8_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vadd.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB8_3
@@ -458,10 +458,10 @@ define void @sink_splat_sub_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB9_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsub.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vsub.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB9_3
@@ -551,10 +551,10 @@ define void @sink_splat_rsub_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB10_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vrsub.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB10_3
@@ -644,10 +644,10 @@ define void @sink_splat_and_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB11_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vand.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vand.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB11_3
@@ -737,10 +737,10 @@ define void @sink_splat_or_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB12_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vor.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vor.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB12_3
@@ -830,10 +830,10 @@ define void @sink_splat_xor_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB13_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vxor.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vxor.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB13_3
@@ -912,9 +912,9 @@ define void @sink_splat_shl(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB14_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsll.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB14_1
@@ -948,9 +948,9 @@ define void @sink_splat_lshr(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB15_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB15_1
@@ -984,9 +984,9 @@ define void @sink_splat_ashr(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: .LBB16_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vsra.vx v25, v25, a1
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsra.vx v8, v8, a1
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a2, .LBB16_1
@@ -1031,10 +1031,10 @@ define void @sink_splat_shl_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB17_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsll.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vsll.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB17_3
@@ -1124,10 +1124,10 @@ define void @sink_splat_lshr_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: .LBB18_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a2)
+; CHECK-NEXT: vl2re32.v v8, (a2)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsrl.vx v26, v26, a1
-; CHECK-NEXT: vs2r.v v26, (a2)
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vs2r.v v8, (a2)
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bne a5, t0, .LBB18_3
@@ -1217,10 +1217,10 @@ define void @sink_splat_ashr_scalable(i32* nocapture %a) {
; CHECK-NEXT: mv a3, a0
; CHECK-NEXT: .LBB19_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl2re32.v v26, (a3)
+; CHECK-NEXT: vl2re32.v v8, (a3)
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vs2r.v v26, (a3)
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vs2r.v v8, (a3)
; CHECK-NEXT: add a4, a4, a7
; CHECK-NEXT: add a3, a3, a5
; CHECK-NEXT: bne a4, a2, .LBB19_3
@@ -1300,9 +1300,9 @@ define void @sink_splat_fmul(float* nocapture %a, float %x) {
; CHECK-NEXT: .LBB20_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfmul.vf v25, v25, ft0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfmul.vf v8, v8, ft0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB20_1
@@ -1337,9 +1337,9 @@ define void @sink_splat_fdiv(float* nocapture %a, float %x) {
; CHECK-NEXT: .LBB21_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfdiv.vf v25, v25, ft0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfdiv.vf v8, v8, ft0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB21_1
@@ -1374,9 +1374,9 @@ define void @sink_splat_frdiv(float* nocapture %a, float %x) {
; CHECK-NEXT: .LBB22_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfrdiv.vf v25, v25, ft0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfrdiv.vf v8, v8, ft0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB22_1
@@ -1411,9 +1411,9 @@ define void @sink_splat_fadd(float* nocapture %a, float %x) {
; CHECK-NEXT: .LBB23_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfadd.vf v25, v25, ft0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfadd.vf v8, v8, ft0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB23_1
@@ -1448,9 +1448,9 @@ define void @sink_splat_fsub(float* nocapture %a, float %x) {
; CHECK-NEXT: .LBB24_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfsub.vf v25, v25, ft0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfsub.vf v8, v8, ft0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB24_1
@@ -1485,9 +1485,9 @@ define void @sink_splat_frsub(float* nocapture %a, float %x) {
; CHECK-NEXT: .LBB25_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vfrsub.vf v25, v25, ft0
-; CHECK-NEXT: vse32.v v25, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vfrsub.vf v8, v8, ft0
+; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: addi a1, a1, -4
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bnez a1, .LBB25_1
@@ -1532,10 +1532,10 @@ define void @sink_splat_fmul_scalable(float* nocapture %a, float %x) {
; CHECK-NEXT: mv a4, a0
; CHECK-NEXT: .LBB26_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl1re32.v v25, (a4)
+; CHECK-NEXT: vl1re32.v v8, (a4)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmul.vf v25, v25, ft0
-; CHECK-NEXT: vs1r.v v25, (a4)
+; CHECK-NEXT: vfmul.vf v8, v8, ft0
+; CHECK-NEXT: vs1r.v v8, (a4)
; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7
; CHECK-NEXT: bne a5, a1, .LBB26_3
@@ -1625,10 +1625,10 @@ define void @sink_splat_fdiv_scalable(float* nocapture %a, float %x) {
; CHECK-NEXT: mv a4, a0
; CHECK-NEXT: .LBB27_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl1re32.v v25, (a4)
+; CHECK-NEXT: vl1re32.v v8, (a4)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vf v25, v25, ft0
-; CHECK-NEXT: vs1r.v v25, (a4)
+; CHECK-NEXT: vfdiv.vf v8, v8, ft0
+; CHECK-NEXT: vs1r.v v8, (a4)
; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7
; CHECK-NEXT: bne a5, a1, .LBB27_3
@@ -1718,10 +1718,10 @@ define void @sink_splat_frdiv_scalable(float* nocapture %a, float %x) {
; CHECK-NEXT: mv a4, a0
; CHECK-NEXT: .LBB28_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl1re32.v v25, (a4)
+; CHECK-NEXT: vl1re32.v v8, (a4)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfrdiv.vf v25, v25, ft0
-; CHECK-NEXT: vs1r.v v25, (a4)
+; CHECK-NEXT: vfrdiv.vf v8, v8, ft0
+; CHECK-NEXT: vs1r.v v8, (a4)
; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7
; CHECK-NEXT: bne a5, a1, .LBB28_3
@@ -1811,10 +1811,10 @@ define void @sink_splat_fadd_scalable(float* nocapture %a, float %x) {
; CHECK-NEXT: mv a4, a0
; CHECK-NEXT: .LBB29_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl1re32.v v25, (a4)
+; CHECK-NEXT: vl1re32.v v8, (a4)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfadd.vf v25, v25, ft0
-; CHECK-NEXT: vs1r.v v25, (a4)
+; CHECK-NEXT: vfadd.vf v8, v8, ft0
+; CHECK-NEXT: vs1r.v v8, (a4)
; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7
; CHECK-NEXT: bne a5, a1, .LBB29_3
@@ -1904,10 +1904,10 @@ define void @sink_splat_fsub_scalable(float* nocapture %a, float %x) {
; CHECK-NEXT: mv a4, a0
; CHECK-NEXT: .LBB30_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl1re32.v v25, (a4)
+; CHECK-NEXT: vl1re32.v v8, (a4)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vf v25, v25, ft0
-; CHECK-NEXT: vs1r.v v25, (a4)
+; CHECK-NEXT: vfsub.vf v8, v8, ft0
+; CHECK-NEXT: vs1r.v v8, (a4)
; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7
; CHECK-NEXT: bne a5, a1, .LBB30_3
@@ -1997,10 +1997,10 @@ define void @sink_splat_frsub_scalable(float* nocapture %a, float %x) {
; CHECK-NEXT: mv a4, a0
; CHECK-NEXT: .LBB31_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vl1re32.v v25, (a4)
+; CHECK-NEXT: vl1re32.v v8, (a4)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfrsub.vf v25, v25, ft0
-; CHECK-NEXT: vs1r.v v25, (a4)
+; CHECK-NEXT: vfrsub.vf v8, v8, ft0
+; CHECK-NEXT: vs1r.v v8, (a4)
; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7
; CHECK-NEXT: bne a5, a1, .LBB31_3
@@ -2080,10 +2080,10 @@ define void @sink_splat_fma(float* noalias nocapture %a, float* nocapture readon
; CHECK-NEXT: .LBB32_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, ft0, v25
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, ft0, v8
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: addi a0, a0, 16
@@ -2122,10 +2122,10 @@ define void @sink_splat_fma_commute(float* noalias nocapture %a, float* nocaptur
; CHECK-NEXT: .LBB33_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
-; CHECK-NEXT: vle32.v v26, (a1)
-; CHECK-NEXT: vfmacc.vf v26, ft0, v25
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: vfmacc.vf v9, ft0, v8
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: addi a0, a0, 16
@@ -2175,12 +2175,12 @@ define dso_local void @sink_splat_fma_scalable(float* noalias nocapture %a, floa
; CHECK-NEXT: .LBB34_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add a2, a0, a5
-; CHECK-NEXT: vl1re32.v v25, (a2)
+; CHECK-NEXT: vl1re32.v v8, (a2)
; CHECK-NEXT: add a4, a1, a5
-; CHECK-NEXT: vl1re32.v v26, (a4)
+; CHECK-NEXT: vl1re32.v v9, (a4)
; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmacc.vf v26, ft0, v25
-; CHECK-NEXT: vs1r.v v26, (a2)
+; CHECK-NEXT: vfmacc.vf v9, ft0, v8
+; CHECK-NEXT: vs1r.v v9, (a2)
; CHECK-NEXT: add a3, a3, t1
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: bne a3, t0, .LBB34_3
@@ -2279,12 +2279,12 @@ define dso_local void @sink_splat_fma_commute_scalable(float* noalias nocapture
; CHECK-NEXT: .LBB35_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add a2, a0, a5
-; CHECK-NEXT: vl1re32.v v25, (a2)
+; CHECK-NEXT: vl1re32.v v8, (a2)
; CHECK-NEXT: add a4, a1, a5
-; CHECK-NEXT: vl1re32.v v26, (a4)
+; CHECK-NEXT: vl1re32.v v9, (a4)
; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmacc.vf v26, ft0, v25
-; CHECK-NEXT: vs1r.v v26, (a2)
+; CHECK-NEXT: vfmacc.vf v9, ft0, v8
+; CHECK-NEXT: vs1r.v v9, (a2)
; CHECK-NEXT: add a3, a3, t1
; CHECK-NEXT: add a5, a5, a7
; CHECK-NEXT: bne a3, t0, .LBB35_3
diff --git a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
index dcf6de2c71a8c..aef5554ffa3de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll
@@ -54,8 +54,8 @@ define <vscale x 8 x i8> @add_stepvector_nxv8i8() {
; CHECK-LABEL: add_stepvector_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vsll.vi v8, v25, 1
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsll.vi v8, v8, 1
; CHECK-NEXT: ret
entry:
%0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
@@ -68,9 +68,9 @@ define <vscale x 8 x i8> @mul_stepvector_nxv8i8() {
; CHECK-LABEL: mul_stepvector_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vid.v v25
+; CHECK-NEXT: vid.v v8
; CHECK-NEXT: addi a0, zero, 3
-; CHECK-NEXT: vmul.vx v8, v25, a0
+; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: ret
entry:
%0 = insertelement <vscale x 8 x i8> poison, i8 3, i32 0
@@ -84,8 +84,8 @@ define <vscale x 8 x i8> @shl_stepvector_nxv8i8() {
; CHECK-LABEL: shl_stepvector_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vid.v v25
-; CHECK-NEXT: vsll.vi v8, v25, 2
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsll.vi v8, v8, 2
; CHECK-NEXT: ret
entry:
%0 = insertelement <vscale x 8 x i8> poison, i8 2, i32 0
@@ -195,8 +195,8 @@ define <vscale x 16 x i16> @add_stepvector_nxv16i16() {
; CHECK-LABEL: add_stepvector_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vsll.vi v8, v28, 1
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsll.vi v8, v8, 1
; CHECK-NEXT: ret
entry:
%0 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
@@ -209,9 +209,9 @@ define <vscale x 16 x i16> @mul_stepvector_nxv16i16() {
; CHECK-LABEL: mul_stepvector_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vid.v v28
+; CHECK-NEXT: vid.v v8
; CHECK-NEXT: addi a0, zero, 3
-; CHECK-NEXT: vmul.vx v8, v28, a0
+; CHECK-NEXT: vmul.vx v8, v8, a0
; CHECK-NEXT: ret
entry:
%0 = insertelement <vscale x 16 x i16> poison, i16 3, i32 0
@@ -225,8 +225,8 @@ define <vscale x 16 x i16> @shl_stepvector_nxv16i16() {
; CHECK-LABEL: shl_stepvector_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vsll.vi v8, v28, 2
+; CHECK-NEXT: vid.v v8
+; CHECK-NEXT: vsll.vi v8, v8, 2
; CHECK-NEXT: ret
entry:
%0 = insertelement <vscale x 16 x i16> poison, i16 2, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll b/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
index 6908e6280fbd2..837cbc3789a48 100644
--- a/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
@@ -8,15 +8,15 @@ define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq0(<vscale x 1 x i16> %x)
; RV32-NEXT: lui a0, 1048571
; RV32-NEXT: addi a0, a0, -1365
; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT: vmul.vx v25, v8, a0
-; RV32-NEXT: vsll.vi v26, v25, 15
-; RV32-NEXT: vsrl.vi v25, v25, 1
-; RV32-NEXT: vor.vv v25, v25, v26
+; RV32-NEXT: vmul.vx v8, v8, a0
+; RV32-NEXT: vsll.vi v9, v8, 15
+; RV32-NEXT: vsrl.vi v8, v8, 1
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: lui a0, 3
; RV32-NEXT: addi a0, a0, -1366
-; RV32-NEXT: vmsgtu.vx v0, v25, a0
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v8, v25, -1, v0
+; RV32-NEXT: vmsgtu.vx v0, v8, a0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmerge.vim v8, v8, -1, v0
; RV32-NEXT: ret
;
; RV64-LABEL: test_urem_vec_even_divisor_eq0:
@@ -24,15 +24,15 @@ define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq0(<vscale x 1 x i16> %x)
; RV64-NEXT: lui a0, 1048571
; RV64-NEXT: addiw a0, a0, -1365
; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT: vmul.vx v25, v8, a0
-; RV64-NEXT: vsll.vi v26, v25, 15
-; RV64-NEXT: vsrl.vi v25, v25, 1
-; RV64-NEXT: vor.vv v25, v25, v26
+; RV64-NEXT: vmul.vx v8, v8, a0
+; RV64-NEXT: vsll.vi v9, v8, 15
+; RV64-NEXT: vsrl.vi v8, v8, 1
+; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: lui a0, 3
; RV64-NEXT: addiw a0, a0, -1366
-; RV64-NEXT: vmsgtu.vx v0, v25, a0
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v8, v25, -1, v0
+; RV64-NEXT: vmsgtu.vx v0, v8, a0
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmerge.vim v8, v8, -1, v0
; RV64-NEXT: ret
%ins1 = insertelement <vscale x 1 x i16> poison, i16 6, i32 0
%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -50,12 +50,12 @@ define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq0(<vscale x 1 x i16> %x)
; RV32-NEXT: lui a0, 1048573
; RV32-NEXT: addi a0, a0, -819
; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT: vmul.vx v25, v8, a0
+; RV32-NEXT: vmul.vx v8, v8, a0
; RV32-NEXT: lui a0, 3
; RV32-NEXT: addi a0, a0, 819
-; RV32-NEXT: vmsgtu.vx v0, v25, a0
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v8, v25, -1, v0
+; RV32-NEXT: vmsgtu.vx v0, v8, a0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmerge.vim v8, v8, -1, v0
; RV32-NEXT: ret
;
; RV64-LABEL: test_urem_vec_odd_divisor_eq0:
@@ -63,12 +63,12 @@ define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq0(<vscale x 1 x i16> %x)
; RV64-NEXT: lui a0, 1048573
; RV64-NEXT: addiw a0, a0, -819
; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT: vmul.vx v25, v8, a0
+; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: lui a0, 3
; RV64-NEXT: addiw a0, a0, 819
-; RV64-NEXT: vmsgtu.vx v0, v25, a0
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v8, v25, -1, v0
+; RV64-NEXT: vmsgtu.vx v0, v8, a0
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmerge.vim v8, v8, -1, v0
; RV64-NEXT: ret
%ins1 = insertelement <vscale x 1 x i16> poison, i16 5, i32 0
%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -85,36 +85,36 @@ define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq1(<vscale x 1 x i16> %x)
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT: vsub.vx v25, v8, a0
+; RV32-NEXT: vsub.vx v8, v8, a0
; RV32-NEXT: lui a0, 1048571
; RV32-NEXT: addi a0, a0, -1365
-; RV32-NEXT: vmul.vx v25, v25, a0
-; RV32-NEXT: vsll.vi v26, v25, 15
-; RV32-NEXT: vsrl.vi v25, v25, 1
-; RV32-NEXT: vor.vv v25, v25, v26
+; RV32-NEXT: vmul.vx v8, v8, a0
+; RV32-NEXT: vsll.vi v9, v8, 15
+; RV32-NEXT: vsrl.vi v8, v8, 1
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: lui a0, 3
; RV32-NEXT: addi a0, a0, -1366
-; RV32-NEXT: vmsgtu.vx v0, v25, a0
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v8, v25, -1, v0
+; RV32-NEXT: vmsgtu.vx v0, v8, a0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmerge.vim v8, v8, -1, v0
; RV32-NEXT: ret
;
; RV64-LABEL: test_urem_vec_even_divisor_eq1:
; RV64: # %bb.0:
; RV64-NEXT: addi a0, zero, 1
; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT: vsub.vx v25, v8, a0
+; RV64-NEXT: vsub.vx v8, v8, a0
; RV64-NEXT: lui a0, 1048571
; RV64-NEXT: addiw a0, a0, -1365
-; RV64-NEXT: vmul.vx v25, v25, a0
-; RV64-NEXT: vsll.vi v26, v25, 15
-; RV64-NEXT: vsrl.vi v25, v25, 1
-; RV64-NEXT: vor.vv v25, v25, v26
+; RV64-NEXT: vmul.vx v8, v8, a0
+; RV64-NEXT: vsll.vi v9, v8, 15
+; RV64-NEXT: vsrl.vi v8, v8, 1
+; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: lui a0, 3
; RV64-NEXT: addiw a0, a0, -1366
-; RV64-NEXT: vmsgtu.vx v0, v25, a0
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v8, v25, -1, v0
+; RV64-NEXT: vmsgtu.vx v0, v8, a0
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmerge.vim v8, v8, -1, v0
; RV64-NEXT: ret
%ins1 = insertelement <vscale x 1 x i16> poison, i16 6, i32 0
%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -131,30 +131,30 @@ define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq1(<vscale x 1 x i16> %x)
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT: vsub.vx v25, v8, a0
+; RV32-NEXT: vsub.vx v8, v8, a0
; RV32-NEXT: lui a0, 1048573
; RV32-NEXT: addi a0, a0, -819
-; RV32-NEXT: vmul.vx v25, v25, a0
+; RV32-NEXT: vmul.vx v8, v8, a0
; RV32-NEXT: lui a0, 3
; RV32-NEXT: addi a0, a0, 818
-; RV32-NEXT: vmsgtu.vx v0, v25, a0
-; RV32-NEXT: vmv.v.i v25, 0
-; RV32-NEXT: vmerge.vim v8, v25, -1, v0
+; RV32-NEXT: vmsgtu.vx v0, v8, a0
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmerge.vim v8, v8, -1, v0
; RV32-NEXT: ret
;
; RV64-LABEL: test_urem_vec_odd_divisor_eq1:
; RV64: # %bb.0:
; RV64-NEXT: addi a0, zero, 1
; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT: vsub.vx v25, v8, a0
+; RV64-NEXT: vsub.vx v8, v8, a0
; RV64-NEXT: lui a0, 1048573
; RV64-NEXT: addiw a0, a0, -819
-; RV64-NEXT: vmul.vx v25, v25, a0
+; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: lui a0, 3
; RV64-NEXT: addiw a0, a0, 818
-; RV64-NEXT: vmsgtu.vx v0, v25, a0
-; RV64-NEXT: vmv.v.i v25, 0
-; RV64-NEXT: vmerge.vim v8, v25, -1, v0
+; RV64-NEXT: vmsgtu.vx v0, v8, a0
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmerge.vim v8, v8, -1, v0
; RV64-NEXT: ret
%ins1 = insertelement <vscale x 1 x i16> poison, i16 5, i32 0
%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
index 3de4f09d432db..5dbc445133238 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vaadd.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vaadd.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vaadd.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
index 4ff5c8aaca964..113d0c8c3f7fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vaaddu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vaaddu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vaaddu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
index b471a2bacf569..d46ec9cda5ac8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
@@ -895,8 +895,8 @@ define <vscale x 1 x i64> @intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vadc.vvm v8, v8, v25, v0
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vadc.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -923,8 +923,8 @@ define <vscale x 2 x i64> @intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vadc.vvm v8, v8, v26, v0
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vadc.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -951,8 +951,8 @@ define <vscale x 4 x i64> @intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vadc.vvm v8, v8, v28, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vadc.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
index 60d1e8ca66389..1fdd00683a290 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
@@ -1778,8 +1778,8 @@ define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1806,9 +1806,9 @@ define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1835,8 +1835,8 @@ define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1863,9 +1863,9 @@ define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1892,8 +1892,8 @@ define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1920,9 +1920,9 @@ define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
index e61245cc90949..11efdaf9f6b4b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
@@ -673,8 +673,8 @@ define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -716,8 +716,8 @@ define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -759,8 +759,8 @@ define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
index 766ab56c40219..2c0de9f7d45b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
@@ -642,7 +642,7 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: mv a4, zero
; CHECK-NEXT: vsetvli a5, zero, e8, m8, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: sub a0, a1, a2
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
@@ -651,7 +651,7 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-NEXT: mv a4, a0
; CHECK-NEXT: .LBB49_4:
; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 128 x i8> undef, i8 -1, i32 0
@@ -1532,7 +1532,7 @@ declare <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32>, <vscale x
define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a4, a1, 2
@@ -1551,7 +1551,7 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB117_4:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i32> undef, i32 -1, i32 0
@@ -1569,11 +1569,11 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a4, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmset.m v25
+; CHECK-NEXT: vmset.m v24
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, mu
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v25, a4
+; CHECK-NEXT: vslidedown.vx v0, v24, a4
; CHECK-NEXT: bltu a0, a3, .LBB118_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a3
@@ -1585,7 +1585,7 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB118_4:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i32> undef, i32 -1, i32 0
@@ -1606,7 +1606,7 @@ declare i32 @llvm.vscale.i32()
define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m) {
; CHECK-LABEL: vadd_vi_nxv32i32_evl_nx8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a4, a0, 2
@@ -1625,7 +1625,7 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <v
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB119_4:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i32> undef, i32 -1, i32 0
@@ -1658,12 +1658,12 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, <
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: srli a1, a0, 2
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
-; RV64-NEXT: vslidedown.vx v25, v0, a1
+; RV64-NEXT: vslidedown.vx v24, v0, a1
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t
; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, mu
-; RV64-NEXT: vmv1r.v v0, v25
+; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
; RV64-NEXT: ret
%elt.head = insertelement <vscale x 32 x i32> undef, i32 -1, i32 0
@@ -1707,9 +1707,9 @@ define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v25, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1733,9 +1733,9 @@ define <vscale x 1 x i64> @vadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v25
+; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1811,9 +1811,9 @@ define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v26, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1837,9 +1837,9 @@ define <vscale x 2 x i64> @vadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v26
+; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1915,9 +1915,9 @@ define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v28, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1941,9 +1941,9 @@ define <vscale x 4 x i64> @vadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vadd.vv v8, v8, v28
+; RV32-NEXT: vadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
index 2e83a369fb754..7852acb65a7bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vand_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vand.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vand.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vand.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vand_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vand.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vand.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vand.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vand_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vand.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vand.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vand.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
index ffe219aa4eb94..2dc5b572ca8fc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
@@ -1082,8 +1082,8 @@ define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vand.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -1148,8 +1148,8 @@ define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vand.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -1214,8 +1214,8 @@ define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vand.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
index ceef36302f79b..84a8fa65ea66a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
@@ -1495,9 +1495,9 @@ define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v25, v0.t
+; RV32-NEXT: vand.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1521,9 +1521,9 @@ define <vscale x 1 x i64> @vand_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v25
+; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1599,9 +1599,9 @@ define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v26, v0.t
+; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1625,9 +1625,9 @@ define <vscale x 2 x i64> @vand_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v26
+; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1703,9 +1703,9 @@ define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v28, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1729,9 +1729,9 @@ define <vscale x 4 x i64> @vand_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vand.vv v8, v8, v28
+; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
index 57bd4292f8674..e58808643c8e1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vasub.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vasub.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vasub.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
index 66d9f080a9ef0..51480d67fb7e6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vasubu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vasubu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vasubu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
index 31106a9b56171..10751b759e680 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
@@ -820,8 +820,8 @@ define <vscale x 1 x i8> @intrinsic_vcompress_um_nxv1i8_nxv1i8(<vscale x 1 x i8>
; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vcompress.vm v25, v8, v0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vcompress.vm v9, v8, v0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
index 39b775f5ae3d0..e814c9652c704 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
@@ -820,8 +820,8 @@ define <vscale x 1 x i8> @intrinsic_vcompress_um_nxv1i8_nxv1i8(<vscale x 1 x i8>
; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vcompress.vm v25, v8, v0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vcompress.vm v9, v8, v0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
index ad6b91a0fb3e5..60f4e9755a1f5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vdiv.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vdiv.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vdiv.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vdiv.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vdiv.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vdiv.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
index d293070c3c860..8b667763c6511 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
@@ -28,11 +28,11 @@ define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -91,11 +91,11 @@ define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -130,11 +130,11 @@ define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -169,11 +169,11 @@ define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -208,11 +208,11 @@ define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vsrl.vi v28, v26, 7
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v8, v10, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v10, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -247,11 +247,11 @@ define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vsrl.vi v8, v28, 7
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v8, v12, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v12, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -326,10 +326,10 @@ define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -365,10 +365,10 @@ define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -404,10 +404,10 @@ define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -443,10 +443,10 @@ define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vsrl.vi v28, v26, 15
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v10, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -482,10 +482,10 @@ define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vsrl.vi v8, v28, 15
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v12, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -560,11 +560,11 @@ define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -600,11 +600,11 @@ define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -640,11 +640,11 @@ define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsrl.vi v28, v26, 31
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -680,11 +680,11 @@ define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsrl.vi v8, v28, 31
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -751,8 +751,8 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vdiv.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -774,12 +774,12 @@ define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmulh.vv v25, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmulh.vv v8, v8, v9
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v26, v25, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vsrl.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
@@ -807,8 +807,8 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vdiv.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -830,12 +830,12 @@ define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmulh.vv v26, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmulh.vv v8, v8, v10
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v28, v26, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vsrl.vx v10, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
@@ -863,8 +863,8 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vdiv.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
@@ -886,12 +886,12 @@ define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmulh.vv v28, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmulh.vv v8, v8, v12
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v8, v28, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vsrl.vx v12, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
index 0a37a6bd8c0d1..22910da428ea8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
@@ -28,11 +28,11 @@ define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -67,11 +67,11 @@ define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -106,11 +106,11 @@ define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -145,11 +145,11 @@ define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -184,11 +184,11 @@ define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vsrl.vi v28, v26, 7
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v8, v10, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v10, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -223,11 +223,11 @@ define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vsrl.vi v8, v28, 7
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v8, v12, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v12, v8, 7
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -302,10 +302,10 @@ define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -341,10 +341,10 @@ define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -380,10 +380,10 @@ define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -419,10 +419,10 @@ define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vsrl.vi v28, v26, 15
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v10, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -458,10 +458,10 @@ define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vsrl.vi v8, v28, 15
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vsrl.vi v12, v8, 15
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -536,11 +536,11 @@ define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -576,11 +576,11 @@ define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v9, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -616,11 +616,11 @@ define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vsrl.vi v28, v26, 31
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v8, v10, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v10, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -656,11 +656,11 @@ define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vsrl.vi v8, v28, 31
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v8, v12, v8
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vsrl.vi v12, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -742,11 +742,11 @@ define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 12
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
+; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v26, v25, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vadd.vv v8, v25, v26
+; CHECK-NEXT: vsrl.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -788,11 +788,11 @@ define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 12
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
+; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v28, v26, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vadd.vv v8, v26, v28
+; CHECK-NEXT: vsrl.vx v10, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -834,11 +834,11 @@ define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 12
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
+; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v8, v28, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vadd.vv v8, v28, v8
+; CHECK-NEXT: vsrl.vx v12, v8, a0
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
index 01709a1b0eb55..97160b8e93457 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
@@ -10,13 +10,13 @@ define <vscale x 8 x i7> @vdiv_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vdiv_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vv v25, v8, v8
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vadd.vv v26, v26, v26
-; CHECK-NEXT: vsra.vi v26, v26, 1
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vadd.vv v9, v9, v9
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vdiv.vv v8, v25, v26, v0.t
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> undef, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> undef, <vscale x 8 x i32> zeroinitializer
@@ -969,9 +969,9 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v25, v0.t
+; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -995,9 +995,9 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v25
+; RV32-NEXT: vdiv.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1047,9 +1047,9 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v26, v0.t
+; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1073,9 +1073,9 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v26
+; RV32-NEXT: vdiv.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1125,9 +1125,9 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v28, v0.t
+; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1151,9 +1151,9 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdiv.vv v8, v8, v28
+; RV32-NEXT: vdiv.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
index 36ae2c34ea96f..47322163d6c86 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vdivu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vdivu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vdivu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vdivu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vdivu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vdivu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
index bd01a919638c1..5a693dc1887bc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
@@ -28,8 +28,8 @@ define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -88,8 +88,8 @@ define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -124,8 +124,8 @@ define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -160,8 +160,8 @@ define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -196,8 +196,8 @@ define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v26, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -232,8 +232,8 @@ define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v28, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -305,8 +305,8 @@ define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -342,8 +342,8 @@ define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -379,8 +379,8 @@ define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -416,8 +416,8 @@ define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v26, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -453,8 +453,8 @@ define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v28, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -527,8 +527,8 @@ define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -564,8 +564,8 @@ define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -601,8 +601,8 @@ define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v26, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -638,8 +638,8 @@ define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v28, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -703,8 +703,8 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vdivu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -724,10 +724,10 @@ define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmulhu.vv v25, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v8, v25, a0
+; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
@@ -753,8 +753,8 @@ define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x
; CHECK-LABEL: vdivu_vi_nxv1i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vi v25, v9, 4
-; CHECK-NEXT: vsrl.vv v8, v8, v25
+; CHECK-NEXT: vadd.vi v9, v9, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -782,8 +782,8 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vdivu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -803,10 +803,10 @@ define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmulhu.vv v26, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmulhu.vv v8, v8, v10
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v8, v26, a0
+; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
@@ -832,8 +832,8 @@ define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x
; CHECK-LABEL: vdivu_vi_nxv2i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vi v26, v10, 4
-; CHECK-NEXT: vsrl.vv v8, v8, v26
+; CHECK-NEXT: vadd.vi v10, v10, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -861,8 +861,8 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vdivu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
@@ -882,10 +882,10 @@ define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmulhu.vv v28, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmulhu.vv v8, v8, v12
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v8, v28, a0
+; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
@@ -911,8 +911,8 @@ define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x
; CHECK-LABEL: vdivu_vi_nxv4i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vi v28, v12, 4
-; CHECK-NEXT: vsrl.vv v8, v8, v28
+; CHECK-NEXT: vadd.vi v12, v12, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
index a351185ea6510..daddce030d9a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
@@ -28,8 +28,8 @@ define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -64,8 +64,8 @@ define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -100,8 +100,8 @@ define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -136,8 +136,8 @@ define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -172,8 +172,8 @@ define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v26, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -208,8 +208,8 @@ define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v28, 5
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 5
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -281,8 +281,8 @@ define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -318,8 +318,8 @@ define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -355,8 +355,8 @@ define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -392,8 +392,8 @@ define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v26, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v28, 13
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 13
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -503,8 +503,8 @@ define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -540,8 +540,8 @@ define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v25, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -577,8 +577,8 @@ define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v26, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -614,8 +614,8 @@ define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v8, v28, 29
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v8, v8, 29
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -689,9 +689,9 @@ define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 61
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v8, v25, a0
+; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -716,8 +716,8 @@ define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x
; CHECK-LABEL: vdivu_vi_nxv1i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vi v25, v9, 4
-; CHECK-NEXT: vsrl.vv v8, v8, v25
+; CHECK-NEXT: vadd.vi v9, v9, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -755,9 +755,9 @@ define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 61
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v8, v26, a0
+; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -782,8 +782,8 @@ define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x
; CHECK-LABEL: vdivu_vi_nxv2i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vi v26, v10, 4
-; CHECK-NEXT: vsrl.vv v8, v8, v26
+; CHECK-NEXT: vadd.vi v10, v10, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -821,9 +821,9 @@ define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 61
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v8, v28, a0
+; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -848,8 +848,8 @@ define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x
; CHECK-LABEL: vdivu_vi_nxv4i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vi v28, v12, 4
-; CHECK-NEXT: vsrl.vv v8, v8, v28
+; CHECK-NEXT: vadd.vi v12, v12, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
index 57f0c640d84d3..a45f1b23e7736 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
@@ -11,11 +11,11 @@ define <vscale x 8 x i7> @vdivu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 127
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, mu
-; CHECK-NEXT: vand.vx v25, v8, a2
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vand.vx v26, v26, a2
+; CHECK-NEXT: vand.vx v8, v8, a2
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vdivu.vv v8, v25, v26, v0.t
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> undef, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> undef, <vscale x 8 x i32> zeroinitializer
@@ -968,9 +968,9 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v25, v0.t
+; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -994,9 +994,9 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v25
+; RV32-NEXT: vdivu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1046,9 +1046,9 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v26, v0.t
+; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1072,9 +1072,9 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v26
+; RV32-NEXT: vdivu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1124,9 +1124,9 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v28, v0.t
+; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1150,9 +1150,9 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vdivu.vv v8, v8, v28
+; RV32-NEXT: vdivu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll
index 8be4d1c6abf07..ae1f11fd41969 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll
@@ -5,8 +5,8 @@ define <vscale x 1 x i16> @vsext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -16,8 +16,8 @@ define <vscale x 1 x i16> @vzext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -27,8 +27,8 @@ define <vscale x 1 x i32> @vsext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -38,8 +38,8 @@ define <vscale x 1 x i32> @vzext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -49,8 +49,8 @@ define <vscale x 1 x i64> @vsext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -60,8 +60,8 @@ define <vscale x 1 x i64> @vzext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -71,8 +71,8 @@ define <vscale x 2 x i16> @vsext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -82,8 +82,8 @@ define <vscale x 2 x i16> @vzext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -93,8 +93,8 @@ define <vscale x 2 x i32> @vsext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -104,8 +104,8 @@ define <vscale x 2 x i32> @vzext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -115,8 +115,8 @@ define <vscale x 2 x i64> @vsext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -126,8 +126,8 @@ define <vscale x 2 x i64> @vzext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -137,8 +137,8 @@ define <vscale x 4 x i16> @vsext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -148,8 +148,8 @@ define <vscale x 4 x i16> @vzext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -159,8 +159,8 @@ define <vscale x 4 x i32> @vsext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -170,8 +170,8 @@ define <vscale x 4 x i32> @vzext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -181,8 +181,8 @@ define <vscale x 4 x i64> @vsext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -192,8 +192,8 @@ define <vscale x 4 x i64> @vzext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -203,8 +203,8 @@ define <vscale x 8 x i16> @vsext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -214,8 +214,8 @@ define <vscale x 8 x i16> @vzext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -225,8 +225,8 @@ define <vscale x 8 x i32> @vsext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -236,8 +236,8 @@ define <vscale x 8 x i32> @vzext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -269,8 +269,8 @@ define <vscale x 16 x i16> @vsext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
@@ -280,8 +280,8 @@ define <vscale x 16 x i16> @vzext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vzext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
@@ -335,8 +335,8 @@ define <vscale x 1 x i32> @vsext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -346,8 +346,8 @@ define <vscale x 1 x i32> @vzext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -357,8 +357,8 @@ define <vscale x 1 x i64> @vsext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -368,8 +368,8 @@ define <vscale x 1 x i64> @vzext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -379,8 +379,8 @@ define <vscale x 2 x i32> @vsext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -390,8 +390,8 @@ define <vscale x 2 x i32> @vzext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -401,8 +401,8 @@ define <vscale x 2 x i64> @vsext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -412,8 +412,8 @@ define <vscale x 2 x i64> @vzext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -423,8 +423,8 @@ define <vscale x 4 x i32> @vsext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -434,8 +434,8 @@ define <vscale x 4 x i32> @vzext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -445,8 +445,8 @@ define <vscale x 4 x i64> @vsext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -456,8 +456,8 @@ define <vscale x 4 x i64> @vzext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -467,8 +467,8 @@ define <vscale x 8 x i32> @vsext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -478,8 +478,8 @@ define <vscale x 8 x i32> @vzext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vzext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -533,8 +533,8 @@ define <vscale x 1 x i64> @vsext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vsext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -544,8 +544,8 @@ define <vscale x 1 x i64> @vzext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vzext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -555,8 +555,8 @@ define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vsext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -566,8 +566,8 @@ define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vzext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -577,8 +577,8 @@ define <vscale x 4 x i64> @vsext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vsext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -588,8 +588,8 @@ define <vscale x 4 x i64> @vzext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vzext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll
index 0d139367aa4e3..aee93842d6135 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll
@@ -5,8 +5,8 @@ define <vscale x 1 x i16> @vsext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -16,8 +16,8 @@ define <vscale x 1 x i16> @vzext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -27,8 +27,8 @@ define <vscale x 1 x i32> @vsext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -38,8 +38,8 @@ define <vscale x 1 x i32> @vzext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -49,8 +49,8 @@ define <vscale x 1 x i64> @vsext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -60,8 +60,8 @@ define <vscale x 1 x i64> @vzext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -71,8 +71,8 @@ define <vscale x 2 x i16> @vsext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -82,8 +82,8 @@ define <vscale x 2 x i16> @vzext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -93,8 +93,8 @@ define <vscale x 2 x i32> @vsext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -104,8 +104,8 @@ define <vscale x 2 x i32> @vzext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -115,8 +115,8 @@ define <vscale x 2 x i64> @vsext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -126,8 +126,8 @@ define <vscale x 2 x i64> @vzext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -137,8 +137,8 @@ define <vscale x 4 x i16> @vsext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -148,8 +148,8 @@ define <vscale x 4 x i16> @vzext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -159,8 +159,8 @@ define <vscale x 4 x i32> @vsext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -170,8 +170,8 @@ define <vscale x 4 x i32> @vzext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -181,8 +181,8 @@ define <vscale x 4 x i64> @vsext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -192,8 +192,8 @@ define <vscale x 4 x i64> @vzext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -203,8 +203,8 @@ define <vscale x 8 x i16> @vsext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -214,8 +214,8 @@ define <vscale x 8 x i16> @vzext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -225,8 +225,8 @@ define <vscale x 8 x i32> @vsext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -236,8 +236,8 @@ define <vscale x 8 x i32> @vzext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -269,8 +269,8 @@ define <vscale x 16 x i16> @vsext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
@@ -280,8 +280,8 @@ define <vscale x 16 x i16> @vzext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vzext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
@@ -335,8 +335,8 @@ define <vscale x 1 x i32> @vsext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -346,8 +346,8 @@ define <vscale x 1 x i32> @vzext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -357,8 +357,8 @@ define <vscale x 1 x i64> @vsext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -368,8 +368,8 @@ define <vscale x 1 x i64> @vzext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -379,8 +379,8 @@ define <vscale x 2 x i32> @vsext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -390,8 +390,8 @@ define <vscale x 2 x i32> @vzext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -401,8 +401,8 @@ define <vscale x 2 x i64> @vsext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -412,8 +412,8 @@ define <vscale x 2 x i64> @vzext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -423,8 +423,8 @@ define <vscale x 4 x i32> @vsext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -434,8 +434,8 @@ define <vscale x 4 x i32> @vzext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -445,8 +445,8 @@ define <vscale x 4 x i64> @vsext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -456,8 +456,8 @@ define <vscale x 4 x i64> @vzext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -467,8 +467,8 @@ define <vscale x 8 x i32> @vsext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -478,8 +478,8 @@ define <vscale x 8 x i32> @vzext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vzext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -533,8 +533,8 @@ define <vscale x 1 x i64> @vsext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vsext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -544,8 +544,8 @@ define <vscale x 1 x i64> @vzext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vzext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -555,8 +555,8 @@ define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vsext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -566,8 +566,8 @@ define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vzext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -577,8 +577,8 @@ define <vscale x 4 x i64> @vsext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vsext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -588,8 +588,8 @@ define <vscale x 4 x i64> @vzext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vzext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
index c3c40aed36706..eb990e28e877d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
@@ -32,9 +32,9 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <
; CHECK-LABEL: vfadd_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -46,9 +46,9 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h
; CHECK-LABEL: vfadd_vf_nxv1f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25
+; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -86,9 +86,9 @@ define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b, <
; CHECK-LABEL: vfadd_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -100,9 +100,9 @@ define <vscale x 2 x half> @vfadd_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h
; CHECK-LABEL: vfadd_vf_nxv2f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25
+; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -140,9 +140,9 @@ define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b, <
; CHECK-LABEL: vfadd_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -154,9 +154,9 @@ define <vscale x 4 x half> @vfadd_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h
; CHECK-LABEL: vfadd_vf_nxv4f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25
+; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -194,9 +194,9 @@ define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <
; CHECK-LABEL: vfadd_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -208,9 +208,9 @@ define <vscale x 8 x half> @vfadd_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h
; CHECK-LABEL: vfadd_vf_nxv8f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26
+; CHECK-NEXT: vfadd.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -248,9 +248,9 @@ define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b
; CHECK-LABEL: vfadd_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -262,9 +262,9 @@ define <vscale x 16 x half> @vfadd_vf_nxv16f16_unmasked(<vscale x 16 x half> %va
; CHECK-LABEL: vfadd_vf_nxv16f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28
+; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <vscale x 1 x float> @vfadd_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK-LABEL: vfadd_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -370,9 +370,9 @@ define <vscale x 1 x float> @vfadd_vf_nxv1f32_unmasked(<vscale x 1 x float> %va,
; CHECK-LABEL: vfadd_vf_nxv1f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25
+; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -410,9 +410,9 @@ define <vscale x 2 x float> @vfadd_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK-LABEL: vfadd_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -424,9 +424,9 @@ define <vscale x 2 x float> @vfadd_vf_nxv2f32_unmasked(<vscale x 2 x float> %va,
; CHECK-LABEL: vfadd_vf_nxv2f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25
+; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -464,9 +464,9 @@ define <vscale x 4 x float> @vfadd_vf_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-LABEL: vfadd_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -478,9 +478,9 @@ define <vscale x 4 x float> @vfadd_vf_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vfadd_vf_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26
+; CHECK-NEXT: vfadd.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -518,9 +518,9 @@ define <vscale x 8 x float> @vfadd_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: vfadd_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -532,9 +532,9 @@ define <vscale x 8 x float> @vfadd_vf_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vfadd_vf_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28
+; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -626,9 +626,9 @@ define <vscale x 1 x double> @vfadd_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK-LABEL: vfadd_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -640,9 +640,9 @@ define <vscale x 1 x double> @vfadd_vf_nxv1f64_unmasked(<vscale x 1 x double> %v
; CHECK-LABEL: vfadd_vf_nxv1f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v25
+; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -680,9 +680,9 @@ define <vscale x 2 x double> @vfadd_vf_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-LABEL: vfadd_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -694,9 +694,9 @@ define <vscale x 2 x double> @vfadd_vf_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-LABEL: vfadd_vf_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v26
+; CHECK-NEXT: vfadd.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -734,9 +734,9 @@ define <vscale x 4 x double> @vfadd_vf_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-LABEL: vfadd_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
@@ -748,9 +748,9 @@ define <vscale x 4 x double> @vfadd_vf_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-LABEL: vfadd_vf_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v8, v28
+; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
index 6763f13e09dce..a4657bd8949c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
@@ -56,8 +56,8 @@ define <vscale x 1 x half> @vfcopysign_exttrunc_vv_nxv1f16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv1f16_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v9
-; CHECK-NEXT: vfsgnj.vv v8, v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%e = fptrunc <vscale x 1 x float> %vs to <vscale x 1 x half>
%r = call <vscale x 1 x half> @llvm.copysign.nxv1f16(<vscale x 1 x half> %vm, <vscale x 1 x half> %e)
@@ -68,10 +68,10 @@ define <vscale x 1 x half> @vfcopysign_exttrunc_vf_nxv1f16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f16_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -84,8 +84,8 @@ define <vscale x 1 x half> @vfcopynsign_exttrunc_vv_nxv1f16_nxv1f32(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv1f16_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v9
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%n = fneg <vscale x 1 x float> %vs
%eneg = fptrunc <vscale x 1 x float> %n to <vscale x 1 x half>
@@ -97,10 +97,10 @@ define <vscale x 1 x half> @vfcopynsign_exttrunc_vf_nxv1f16_nxv1f32(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f16_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -114,10 +114,10 @@ define <vscale x 1 x half> @vfcopysign_exttrunc_vv_nxv1f16_nxv1f64(<vscale x 1 x
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv1f16_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v9
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v9, v10
+; CHECK-NEXT: vfsgnj.vv v8, v8, v9
; CHECK-NEXT: ret
%e = fptrunc <vscale x 1 x double> %vs to <vscale x 1 x half>
%r = call <vscale x 1 x half> @llvm.copysign.nxv1f16(<vscale x 1 x half> %vm, <vscale x 1 x half> %e)
@@ -128,12 +128,12 @@ define <vscale x 1 x half> @vfcopysign_exttrunc_vf_nxv1f16_nxv1f64(<vscale x 1 x
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f16_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v26
-; CHECK-NEXT: vfsgnj.vv v8, v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v10
+; CHECK-NEXT: vfsgnj.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -146,10 +146,10 @@ define <vscale x 1 x half> @vfcopynsign_exttrunc_vv_nxv1f16_nxv1f64(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv1f16_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v9
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v9, v10
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
; CHECK-NEXT: ret
%n = fneg <vscale x 1 x double> %vs
%eneg = fptrunc <vscale x 1 x double> %n to <vscale x 1 x half>
@@ -161,12 +161,12 @@ define <vscale x 1 x half> @vfcopynsign_exttrunc_vf_nxv1f16_nxv1f64(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f16_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v26
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v10
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -324,8 +324,8 @@ define <vscale x 8 x half> @vfcopysign_exttrunc_vv_nxv8f16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv8f16_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v12
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%e = fptrunc <vscale x 8 x float> %vs to <vscale x 8 x half>
%r = call <vscale x 8 x half> @llvm.copysign.nxv8f16(<vscale x 8 x half> %vm, <vscale x 8 x half> %e)
@@ -336,10 +336,10 @@ define <vscale x 8 x half> @vfcopysign_exttrunc_vf_nxv8f16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f16_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -352,8 +352,8 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vv_nxv8f16_nxv8f32(<vscale x 8
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv8f16_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v12
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%n = fneg <vscale x 8 x float> %vs
%eneg = fptrunc <vscale x 8 x float> %n to <vscale x 8 x half>
@@ -365,10 +365,10 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vf_nxv8f16_nxv8f32(<vscale x 8
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f16_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -382,10 +382,10 @@ define <vscale x 8 x half> @vfcopysign_exttrunc_vv_nxv8f16_nxv8f64(<vscale x 8 x
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv8f16_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v16
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%e = fptrunc <vscale x 8 x double> %vs to <vscale x 8 x half>
%r = call <vscale x 8 x half> @llvm.copysign.nxv8f16(<vscale x 8 x half> %vm, <vscale x 8 x half> %e)
@@ -398,10 +398,10 @@ define <vscale x 8 x half> @vfcopysign_exttrunc_vf_nxv8f16_nxv8f64(<vscale x 8 x
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v16
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -414,10 +414,10 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vv_nxv8f16_nxv8f64(<vscale x 8
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv8f16_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v16
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%n = fneg <vscale x 8 x double> %vs
%eneg = fptrunc <vscale x 8 x double> %n to <vscale x 8 x half>
@@ -431,10 +431,10 @@ define <vscale x 8 x half> @vfcopynsign_exttrunc_vf_nxv8f16_nxv8f64(<vscale x 8
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v16
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v28
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v12
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -592,9 +592,9 @@ define <vscale x 1 x float> @vfcopysign_exttrunc_vv_nxv1f32_nxv1f16(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv1f32_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v9
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v25
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%e = fpext <vscale x 1 x half> %vs to <vscale x 1 x float>
%r = call <vscale x 1 x float> @llvm.copysign.nxv1f32(<vscale x 1 x float> %vm, <vscale x 1 x float> %e)
@@ -605,10 +605,10 @@ define <vscale x 1 x float> @vfcopysign_exttrunc_vf_nxv1f32_nxv1f16(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f32_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -621,9 +621,9 @@ define <vscale x 1 x float> @vfcopynsign_exttrunc_vv_nxv1f32_nxv1f16(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv1f32_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v9
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v25
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%n = fneg <vscale x 1 x half> %vs
%eneg = fpext <vscale x 1 x half> %n to <vscale x 1 x float>
@@ -635,10 +635,10 @@ define <vscale x 1 x float> @vfcopynsign_exttrunc_vf_nxv1f32_nxv1f16(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f32_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -652,8 +652,8 @@ define <vscale x 1 x float> @vfcopysign_exttrunc_vv_nxv1f32_nxv1f64(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv1f32_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v9
-; CHECK-NEXT: vfsgnj.vv v8, v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%e = fptrunc <vscale x 1 x double> %vs to <vscale x 1 x float>
%r = call <vscale x 1 x float> @llvm.copysign.nxv1f32(<vscale x 1 x float> %vm, <vscale x 1 x float> %e)
@@ -664,10 +664,10 @@ define <vscale x 1 x float> @vfcopysign_exttrunc_vf_nxv1f32_nxv1f64(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f32_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -680,8 +680,8 @@ define <vscale x 1 x float> @vfcopynsign_exttrunc_vv_nxv1f32_nxv1f64(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv1f32_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v9
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%n = fneg <vscale x 1 x double> %vs
%eneg = fptrunc <vscale x 1 x double> %n to <vscale x 1 x float>
@@ -693,10 +693,10 @@ define <vscale x 1 x float> @vfcopynsign_exttrunc_vf_nxv1f32_nxv1f64(<vscale x 1
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f32_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v25
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v10, v9
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -854,9 +854,9 @@ define <vscale x 8 x float> @vfcopysign_exttrunc_vv_nxv8f32_nxv8f16(<vscale x 8
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v28
+; CHECK-NEXT: vfsgnj.vv v8, v8, v16
; CHECK-NEXT: ret
%e = fpext <vscale x 8 x half> %vs to <vscale x 8 x float>
%r = call <vscale x 8 x float> @llvm.copysign.nxv8f32(<vscale x 8 x float> %vm, <vscale x 8 x float> %e)
@@ -867,10 +867,10 @@ define <vscale x 8 x float> @vfcopysign_exttrunc_vf_nxv8f32_nxv8f16(<vscale x 8
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v28, v26
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v16, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v28
+; CHECK-NEXT: vfsgnj.vv v8, v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -883,9 +883,9 @@ define <vscale x 8 x float> @vfcopynsign_exttrunc_vv_nxv8f32_nxv8f16(<vscale x 8
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v28
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v16
; CHECK-NEXT: ret
%n = fneg <vscale x 8 x half> %vs
%eneg = fpext <vscale x 8 x half> %n to <vscale x 8 x float>
@@ -897,10 +897,10 @@ define <vscale x 8 x float> @vfcopynsign_exttrunc_vf_nxv8f32_nxv8f16(<vscale x 8
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v28, v26
+; CHECK-NEXT: vfmv.v.f v12, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v16, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v28
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -914,8 +914,8 @@ define <vscale x 8 x float> @vfcopysign_exttrunc_vv_nxv8f32_nxv8f64(<vscale x 8
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv8f32_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v16
-; CHECK-NEXT: vfsgnj.vv v8, v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v12, v16
+; CHECK-NEXT: vfsgnj.vv v8, v8, v12
; CHECK-NEXT: ret
%e = fptrunc <vscale x 8 x double> %vs to <vscale x 8 x float>
%r = call <vscale x 8 x float> @llvm.copysign.nxv8f32(<vscale x 8 x float> %vm, <vscale x 8 x float> %e)
@@ -928,8 +928,8 @@ define <vscale x 8 x float> @vfcopysign_exttrunc_vf_nxv8f32_nxv8f64(<vscale x 8
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v16
-; CHECK-NEXT: vfsgnj.vv v8, v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v12, v16
+; CHECK-NEXT: vfsgnj.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -942,8 +942,8 @@ define <vscale x 8 x float> @vfcopynsign_exttrunc_vv_nxv8f32_nxv8f64(<vscale x 8
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv8f32_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v16
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v12, v16
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v12
; CHECK-NEXT: ret
%n = fneg <vscale x 8 x double> %vs
%eneg = fptrunc <vscale x 8 x double> %n to <vscale x 8 x float>
@@ -957,8 +957,8 @@ define <vscale x 8 x float> @vfcopynsign_exttrunc_vf_nxv8f32_nxv8f64(<vscale x 8
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v16
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v12, v16
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %s, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
@@ -1068,11 +1068,11 @@ define <vscale x 1 x double> @vfcopysign_exttrunc_vv_nxv1f64_nxv1f16(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv1f64_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v9
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfsgnj.vv v8, v8, v9
; CHECK-NEXT: ret
%e = fpext <vscale x 1 x half> %vs to <vscale x 1 x double>
%r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %e)
@@ -1083,12 +1083,12 @@ define <vscale x 1 x double> @vfcopysign_exttrunc_vf_nxv1f64_nxv1f16(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f64_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v26
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v25
+; CHECK-NEXT: vfsgnj.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -1101,11 +1101,11 @@ define <vscale x 1 x double> @vfcopynsign_exttrunc_vv_nxv1f64_nxv1f16(<vscale x
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv1f64_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v9
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
; CHECK-NEXT: ret
%n = fneg <vscale x 1 x half> %vs
%eneg = fpext <vscale x 1 x half> %n to <vscale x 1 x double>
@@ -1117,12 +1117,12 @@ define <vscale x 1 x double> @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f16(<vscale x
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f64_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v26
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v25
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -1136,9 +1136,9 @@ define <vscale x 1 x double> @vfcopysign_exttrunc_vv_nxv1f64_nxv1f32(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv1f64_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v9
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v25
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%e = fpext <vscale x 1 x float> %vs to <vscale x 1 x double>
%r = call <vscale x 1 x double> @llvm.copysign.nxv1f64(<vscale x 1 x double> %vm, <vscale x 1 x double> %e)
@@ -1149,10 +1149,10 @@ define <vscale x 1 x double> @vfcopysign_exttrunc_vf_nxv1f64_nxv1f32(<vscale x 1
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv1f64_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v26
+; CHECK-NEXT: vfsgnj.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -1165,9 +1165,9 @@ define <vscale x 1 x double> @vfcopynsign_exttrunc_vv_nxv1f64_nxv1f32(<vscale x
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv1f64_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v9
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v25
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%n = fneg <vscale x 1 x float> %vs
%eneg = fpext <vscale x 1 x float> %n to <vscale x 1 x double>
@@ -1179,10 +1179,10 @@ define <vscale x 1 x double> @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f32(<vscale x
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv1f64_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v26, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v26
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -1340,11 +1340,11 @@ define <vscale x 8 x double> @vfcopysign_exttrunc_vv_nxv8f64_nxv8f16(<vscale x 8
; CHECK-LABEL: vfcopysign_exttrunc_vv_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v16
+; CHECK-NEXT: vfwcvt.f.f.v v20, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v16, v28
+; CHECK-NEXT: vfwcvt.f.f.v v24, v20
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v16
+; CHECK-NEXT: vfsgnj.vv v8, v8, v24
; CHECK-NEXT: ret
%e = fpext <vscale x 8 x half> %vs to <vscale x 8 x double>
%r = call <vscale x 8 x double> @llvm.copysign.nxv8f64(<vscale x 8 x double> %vm, <vscale x 8 x double> %e)
@@ -1355,12 +1355,12 @@ define <vscale x 8 x double> @vfcopysign_exttrunc_vf_nxv8f64_nxv8f16(<vscale x 8
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v28, v26
+; CHECK-NEXT: vfmv.v.f v16, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v20, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v16, v28
+; CHECK-NEXT: vfwcvt.f.f.v v24, v20
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v16
+; CHECK-NEXT: vfsgnj.vv v8, v8, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -1373,11 +1373,11 @@ define <vscale x 8 x double> @vfcopynsign_exttrunc_vv_nxv8f64_nxv8f16(<vscale x
; CHECK-LABEL: vfcopynsign_exttrunc_vv_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v16
+; CHECK-NEXT: vfwcvt.f.f.v v20, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v16, v28
+; CHECK-NEXT: vfwcvt.f.f.v v24, v20
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v16
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v24
; CHECK-NEXT: ret
%n = fneg <vscale x 8 x half> %vs
%eneg = fpext <vscale x 8 x half> %n to <vscale x 8 x double>
@@ -1389,12 +1389,12 @@ define <vscale x 8 x double> @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f16(<vscale x
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v28, v26
+; CHECK-NEXT: vfmv.v.f v16, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v20, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v16, v28
+; CHECK-NEXT: vfwcvt.f.f.v v24, v20
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v16
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %s, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -1421,10 +1421,10 @@ define <vscale x 8 x double> @vfcopysign_exttrunc_vf_nxv8f64_nxv8f32(<vscale x 8
; CHECK-LABEL: vfcopysign_exttrunc_vf_nxv8f64_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v16, v28
+; CHECK-NEXT: vfmv.v.f v16, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v24, v16
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v8, v8, v16
+; CHECK-NEXT: vfsgnj.vv v8, v8, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -1451,10 +1451,10 @@ define <vscale x 8 x double> @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f32(<vscale x
; CHECK-LABEL: vfcopynsign_exttrunc_vf_nxv8f64_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
-; CHECK-NEXT: vfwcvt.f.f.v v16, v28
+; CHECK-NEXT: vfmv.v.f v16, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v24, v16
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfsgnjn.vv v8, v8, v16
+; CHECK-NEXT: vfsgnjn.vv v8, v8, v24
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %s, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
index 4146f215730c7..4bf8a4ac42ee8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
@@ -32,9 +32,9 @@ define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <
; CHECK-LABEL: vfdiv_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -46,9 +46,9 @@ define <vscale x 1 x half> @vfdiv_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h
; CHECK-LABEL: vfdiv_vf_nxv1f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -86,9 +86,9 @@ define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b, <
; CHECK-LABEL: vfdiv_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -100,9 +100,9 @@ define <vscale x 2 x half> @vfdiv_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h
; CHECK-LABEL: vfdiv_vf_nxv2f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -140,9 +140,9 @@ define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b, <
; CHECK-LABEL: vfdiv_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -154,9 +154,9 @@ define <vscale x 4 x half> @vfdiv_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h
; CHECK-LABEL: vfdiv_vf_nxv4f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -194,9 +194,9 @@ define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <
; CHECK-LABEL: vfdiv_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -208,9 +208,9 @@ define <vscale x 8 x half> @vfdiv_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h
; CHECK-LABEL: vfdiv_vf_nxv8f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26
+; CHECK-NEXT: vfdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -248,9 +248,9 @@ define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b
; CHECK-LABEL: vfdiv_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -262,9 +262,9 @@ define <vscale x 16 x half> @vfdiv_vf_nxv16f16_unmasked(<vscale x 16 x half> %va
; CHECK-LABEL: vfdiv_vf_nxv16f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28
+; CHECK-NEXT: vfdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <vscale x 1 x float> @vfdiv_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK-LABEL: vfdiv_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -370,9 +370,9 @@ define <vscale x 1 x float> @vfdiv_vf_nxv1f32_unmasked(<vscale x 1 x float> %va,
; CHECK-LABEL: vfdiv_vf_nxv1f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -410,9 +410,9 @@ define <vscale x 2 x float> @vfdiv_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK-LABEL: vfdiv_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -424,9 +424,9 @@ define <vscale x 2 x float> @vfdiv_vf_nxv2f32_unmasked(<vscale x 2 x float> %va,
; CHECK-LABEL: vfdiv_vf_nxv2f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -464,9 +464,9 @@ define <vscale x 4 x float> @vfdiv_vf_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-LABEL: vfdiv_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -478,9 +478,9 @@ define <vscale x 4 x float> @vfdiv_vf_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vfdiv_vf_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26
+; CHECK-NEXT: vfdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -518,9 +518,9 @@ define <vscale x 8 x float> @vfdiv_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: vfdiv_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -532,9 +532,9 @@ define <vscale x 8 x float> @vfdiv_vf_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vfdiv_vf_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28
+; CHECK-NEXT: vfdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -626,9 +626,9 @@ define <vscale x 1 x double> @vfdiv_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK-LABEL: vfdiv_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -640,9 +640,9 @@ define <vscale x 1 x double> @vfdiv_vf_nxv1f64_unmasked(<vscale x 1 x double> %v
; CHECK-LABEL: vfdiv_vf_nxv1f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v25
+; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -680,9 +680,9 @@ define <vscale x 2 x double> @vfdiv_vf_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-LABEL: vfdiv_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -694,9 +694,9 @@ define <vscale x 2 x double> @vfdiv_vf_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-LABEL: vfdiv_vf_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v26
+; CHECK-NEXT: vfdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -734,9 +734,9 @@ define <vscale x 4 x double> @vfdiv_vf_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-LABEL: vfdiv_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
@@ -748,9 +748,9 @@ define <vscale x 4 x double> @vfdiv_vf_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-LABEL: vfdiv_vf_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v8, v28
+; CHECK-NEXT: vfdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
index 8c8927704fd48..dab1544783435 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
@@ -27,10 +27,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv1i1(
define i32 @intrinsic_vfirst_mask_m_i32_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv1i1(
@@ -67,10 +67,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv2i1(
define i32 @intrinsic_vfirst_mask_m_i32_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv2i1(
@@ -107,10 +107,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv4i1(
define i32 @intrinsic_vfirst_mask_m_i32_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv4i1(
@@ -147,10 +147,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv8i1(
define i32 @intrinsic_vfirst_mask_m_i32_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv8i1(
@@ -187,10 +187,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv16i1(
define i32 @intrinsic_vfirst_mask_m_i32_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv16i1(
@@ -227,10 +227,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv32i1(
define i32 @intrinsic_vfirst_mask_m_i32_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv32i1(
@@ -267,10 +267,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv64i1(
define i32 @intrinsic_vfirst_mask_m_i32_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
index 65762fac25817..005d023207bfe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
@@ -27,10 +27,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv1i1(
define i64 @intrinsic_vfirst_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv1i1(
@@ -67,10 +67,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv2i1(
define i64 @intrinsic_vfirst_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv2i1(
@@ -107,10 +107,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv4i1(
define i64 @intrinsic_vfirst_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv4i1(
@@ -147,10 +147,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv8i1(
define i64 @intrinsic_vfirst_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv8i1(
@@ -187,10 +187,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv16i1(
define i64 @intrinsic_vfirst_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv16i1(
@@ -227,10 +227,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv32i1(
define i64 @intrinsic_vfirst_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv32i1(
@@ -267,10 +267,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv64i1(
define i64 @intrinsic_vfirst_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vfirst.m a0, v25, v0.t
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
index a474d5907d95a..23a45a26f0d32 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
@@ -32,9 +32,9 @@ define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <
; CHECK-LABEL: vfmul_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -46,9 +46,9 @@ define <vscale x 1 x half> @vfmul_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h
; CHECK-LABEL: vfmul_vf_nxv1f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -86,9 +86,9 @@ define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b, <
; CHECK-LABEL: vfmul_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -100,9 +100,9 @@ define <vscale x 2 x half> @vfmul_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h
; CHECK-LABEL: vfmul_vf_nxv2f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -140,9 +140,9 @@ define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b, <
; CHECK-LABEL: vfmul_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -154,9 +154,9 @@ define <vscale x 4 x half> @vfmul_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h
; CHECK-LABEL: vfmul_vf_nxv4f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -194,9 +194,9 @@ define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <
; CHECK-LABEL: vfmul_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -208,9 +208,9 @@ define <vscale x 8 x half> @vfmul_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h
; CHECK-LABEL: vfmul_vf_nxv8f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26
+; CHECK-NEXT: vfmul.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -248,9 +248,9 @@ define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b
; CHECK-LABEL: vfmul_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -262,9 +262,9 @@ define <vscale x 16 x half> @vfmul_vf_nxv16f16_unmasked(<vscale x 16 x half> %va
; CHECK-LABEL: vfmul_vf_nxv16f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28
+; CHECK-NEXT: vfmul.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <vscale x 1 x float> @vfmul_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK-LABEL: vfmul_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -370,9 +370,9 @@ define <vscale x 1 x float> @vfmul_vf_nxv1f32_unmasked(<vscale x 1 x float> %va,
; CHECK-LABEL: vfmul_vf_nxv1f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -410,9 +410,9 @@ define <vscale x 2 x float> @vfmul_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK-LABEL: vfmul_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -424,9 +424,9 @@ define <vscale x 2 x float> @vfmul_vf_nxv2f32_unmasked(<vscale x 2 x float> %va,
; CHECK-LABEL: vfmul_vf_nxv2f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -464,9 +464,9 @@ define <vscale x 4 x float> @vfmul_vf_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-LABEL: vfmul_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -478,9 +478,9 @@ define <vscale x 4 x float> @vfmul_vf_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vfmul_vf_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26
+; CHECK-NEXT: vfmul.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -518,9 +518,9 @@ define <vscale x 8 x float> @vfmul_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: vfmul_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -532,9 +532,9 @@ define <vscale x 8 x float> @vfmul_vf_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vfmul_vf_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28
+; CHECK-NEXT: vfmul.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -626,9 +626,9 @@ define <vscale x 1 x double> @vfmul_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK-LABEL: vfmul_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -640,9 +640,9 @@ define <vscale x 1 x double> @vfmul_vf_nxv1f64_unmasked(<vscale x 1 x double> %v
; CHECK-LABEL: vfmul_vf_nxv1f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -680,9 +680,9 @@ define <vscale x 2 x double> @vfmul_vf_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-LABEL: vfmul_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -694,9 +694,9 @@ define <vscale x 2 x double> @vfmul_vf_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-LABEL: vfmul_vf_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v26
+; CHECK-NEXT: vfmul.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -734,9 +734,9 @@ define <vscale x 4 x double> @vfmul_vf_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-LABEL: vfmul_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
@@ -748,9 +748,9 @@ define <vscale x 4 x double> @vfmul_vf_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-LABEL: vfmul_vf_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v8, v28
+; CHECK-NEXT: vfmul.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
index 5a6d5ad01fb71..85d4cdd923191 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
index cfda8166c53be..aa28c03325868 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
index 2d8d9afc4497f..05731ea19ac59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.x.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.x.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.x.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.x.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
index 084c2be2aa4a2..c41dae4d71e59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.x.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.x.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.x.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.x.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
index 6e348bc613ce0..057ce7b68c3da 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.xu.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.xu.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.xu.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.xu.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
index c7e22d42a8453..5ab93002bfbf9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.xu.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.xu.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.xu.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.xu.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
index c7f735ee9bf77..a3fb4007c9dd4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32(<vscal
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
index 4dc5208e4010e..7b68b285fed67 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32(<vscal
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32(
@@ -219,8 +219,8 @@ define <vscale x 1 x float> @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64(
@@ -261,8 +261,8 @@ define <vscale x 2 x float> @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64(
@@ -303,8 +303,8 @@ define <vscale x 4 x float> @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64(
@@ -345,8 +345,8 @@ define <vscale x 8 x float> @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
index 8f691aad14a45..19c33df377e0b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
index e1866ffe0e9a4..fe2166a997848 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
index b762b097286a9..cac42418bf8fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32(<vscal
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
index d9c0605fdb3a9..d96c48495667e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16(<vscale x 2
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16(<vscale x 4
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16(<vscale x 8
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16(<vscale
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32(<vscal
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
index 4d824137eeaf1..c87f39e406764 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16(<vscale x 2 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16(<vscale x 4 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16(<vscale x 8 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16(<vscale x 16
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16(<vscale x 32
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
index 593e12d894f7b..6b1d672afea2f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16(<vscale x 2 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16(<vscale x 4 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16(<vscale x 8 x ha
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16(<vscale x 16
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16(<vscale x 32
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32(<vscale x 1
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
index a340dc7cc7460..daa4633aa0a85 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16(<vscale x 2 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16(<vscale x 4 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16(<vscale x 8 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16(<vscale x 16
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16(<vscale x 32
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
index 793cc88eeabf5..e5f790f766c69 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i8> @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i8> @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16(<vscale x 2 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i8> @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16(<vscale x 4 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i8> @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16(<vscale x 8 x h
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16(
@@ -177,8 +177,8 @@ define <vscale x 16 x i8> @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16(<vscale x 16
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16(
@@ -219,8 +219,8 @@ define <vscale x 32 x i8> @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16(<vscale x 32
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16(
@@ -261,8 +261,8 @@ define <vscale x 1 x i16> @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32(
@@ -303,8 +303,8 @@ define <vscale x 2 x i16> @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32(
@@ -345,8 +345,8 @@ define <vscale x 4 x i16> @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32(
@@ -387,8 +387,8 @@ define <vscale x 8 x i16> @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32(
@@ -429,8 +429,8 @@ define <vscale x 16 x i16> @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32(<vscale x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32(
@@ -471,8 +471,8 @@ define <vscale x 1 x i32> @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64(
@@ -513,8 +513,8 @@ define <vscale x 2 x i32> @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64(
@@ -555,8 +555,8 @@ define <vscale x 4 x i32> @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64(
@@ -597,8 +597,8 @@ define <vscale x 8 x i32> @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
index 4648ad074f7de..c5b1a90a8f5a1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
@@ -9,15 +9,15 @@ define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {
; RV32-LABEL: vfpext_nxv1f16_nxv1f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv1f16_nxv1f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%evec = fpext <vscale x 1 x half> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -28,17 +28,17 @@ define <vscale x 1 x double> @vfpext_nxv1f16_nxv1f64(<vscale x 1 x half> %va) {
; RV32-LABEL: vfpext_nxv1f16_nxv1f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v25, v8
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v8, v25
+; RV32-NEXT: vfwcvt.f.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv1f16_nxv1f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v25, v8
+; RV64-NEXT: vfwcvt.f.f.v v9, v8
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v8, v25
+; RV64-NEXT: vfwcvt.f.f.v v8, v9
; RV64-NEXT: ret
%evec = fpext <vscale x 1 x half> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -49,15 +49,15 @@ define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32(<vscale x 2 x half> %va) {
; RV32-LABEL: vfpext_nxv2f16_nxv2f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv2f16_nxv2f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%evec = fpext <vscale x 2 x half> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -68,17 +68,17 @@ define <vscale x 2 x double> @vfpext_nxv2f16_nxv2f64(<vscale x 2 x half> %va) {
; RV32-LABEL: vfpext_nxv2f16_nxv2f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v25, v8
+; RV32-NEXT: vfwcvt.f.f.v v10, v8
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v8, v25
+; RV32-NEXT: vfwcvt.f.f.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv2f16_nxv2f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v25, v8
+; RV64-NEXT: vfwcvt.f.f.v v10, v8
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v8, v25
+; RV64-NEXT: vfwcvt.f.f.v v8, v10
; RV64-NEXT: ret
%evec = fpext <vscale x 2 x half> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -89,15 +89,15 @@ define <vscale x 4 x float> @vfpext_nxv4f16_nxv4f32(<vscale x 4 x half> %va) {
; RV32-LABEL: vfpext_nxv4f16_nxv4f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v26, v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vfwcvt.f.f.v v10, v8
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv4f16_nxv4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v26, v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vfwcvt.f.f.v v10, v8
+; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%evec = fpext <vscale x 4 x half> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -108,17 +108,17 @@ define <vscale x 4 x double> @vfpext_nxv4f16_nxv4f64(<vscale x 4 x half> %va) {
; RV32-LABEL: vfpext_nxv4f16_nxv4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v26, v8
+; RV32-NEXT: vfwcvt.f.f.v v12, v8
; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v8, v26
+; RV32-NEXT: vfwcvt.f.f.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv4f16_nxv4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v26, v8
+; RV64-NEXT: vfwcvt.f.f.v v12, v8
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v8, v26
+; RV64-NEXT: vfwcvt.f.f.v v8, v12
; RV64-NEXT: ret
%evec = fpext <vscale x 4 x half> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -129,15 +129,15 @@ define <vscale x 8 x float> @vfpext_nxv8f16_nxv8f32(<vscale x 8 x half> %va) {
; RV32-LABEL: vfpext_nxv8f16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v28, v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vfwcvt.f.f.v v12, v8
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv8f16_nxv8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v28, v8
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vfwcvt.f.f.v v12, v8
+; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%evec = fpext <vscale x 8 x half> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -148,17 +148,17 @@ define <vscale x 8 x double> @vfpext_nxv8f16_nxv8f64(<vscale x 8 x half> %va) {
; RV32-LABEL: vfpext_nxv8f16_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v28, v8
+; RV32-NEXT: vfwcvt.f.f.v v16, v8
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v8, v28
+; RV32-NEXT: vfwcvt.f.f.v v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv8f16_nxv8f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v28, v8
+; RV64-NEXT: vfwcvt.f.f.v v16, v8
; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v8, v28
+; RV64-NEXT: vfwcvt.f.f.v v8, v16
; RV64-NEXT: ret
%evec = fpext <vscale x 8 x half> %va to <vscale x 8 x double>
ret <vscale x 8 x double> %evec
@@ -188,15 +188,15 @@ define <vscale x 1 x double> @vfpext_nxv1f32_nxv1f64(<vscale x 1 x float> %va) {
; RV32-LABEL: vfpext_nxv1f32_nxv1f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv1f32_nxv1f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%evec = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -207,15 +207,15 @@ define <vscale x 2 x double> @vfpext_nxv2f32_nxv2f64(<vscale x 2 x float> %va) {
; RV32-LABEL: vfpext_nxv2f32_nxv2f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v26, v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vfwcvt.f.f.v v10, v8
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv2f32_nxv2f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v26, v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vfwcvt.f.f.v v10, v8
+; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
%evec = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -226,15 +226,15 @@ define <vscale x 4 x double> @vfpext_nxv4f32_nxv4f64(<vscale x 4 x float> %va) {
; RV32-LABEL: vfpext_nxv4f32_nxv4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV32-NEXT: vfwcvt.f.f.v v28, v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vfwcvt.f.f.v v12, v8
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vfpext_nxv4f32_nxv4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV64-NEXT: vfwcvt.f.f.v v28, v8
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vfwcvt.f.f.v v12, v8
+; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
%evec = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
index 83d376302f261..692c8fdf472c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
@@ -8,9 +8,9 @@ define <vscale x 1 x i1> @vfptosi_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptosi_nxv1f16_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x half> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
@@ -20,9 +20,9 @@ define <vscale x 1 x i1> @vfptoui_nxv1f16_nxv1i1(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptoui_nxv1f16_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x half> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
@@ -32,8 +32,8 @@ define <vscale x 1 x i8> @vfptosi_nxv1f16_nxv1i8(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptosi_nxv1f16_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x half> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
@@ -43,8 +43,8 @@ define <vscale x 1 x i8> @vfptoui_nxv1f16_nxv1i8(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptoui_nxv1f16_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x half> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
@@ -74,8 +74,8 @@ define <vscale x 1 x i32> @vfptosi_nxv1f16_nxv1i32(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptosi_nxv1f16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x half> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -85,8 +85,8 @@ define <vscale x 1 x i32> @vfptoui_nxv1f16_nxv1i32(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptoui_nxv1f16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x half> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -96,9 +96,9 @@ define <vscale x 1 x i64> @vfptosi_nxv1f16_nxv1i64(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptosi_nxv1f16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x half> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -108,9 +108,9 @@ define <vscale x 1 x i64> @vfptoui_nxv1f16_nxv1i64(<vscale x 1 x half> %va) {
; CHECK-LABEL: vfptoui_nxv1f16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x half> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -120,9 +120,9 @@ define <vscale x 2 x i1> @vfptosi_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptosi_nxv2f16_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x half> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
@@ -132,9 +132,9 @@ define <vscale x 2 x i1> @vfptoui_nxv2f16_nxv2i1(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptoui_nxv2f16_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x half> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
@@ -144,8 +144,8 @@ define <vscale x 2 x i8> @vfptosi_nxv2f16_nxv2i8(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptosi_nxv2f16_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x half> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
@@ -155,8 +155,8 @@ define <vscale x 2 x i8> @vfptoui_nxv2f16_nxv2i8(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptoui_nxv2f16_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x half> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
@@ -186,8 +186,8 @@ define <vscale x 2 x i32> @vfptosi_nxv2f16_nxv2i32(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptosi_nxv2f16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x half> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -197,8 +197,8 @@ define <vscale x 2 x i32> @vfptoui_nxv2f16_nxv2i32(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptoui_nxv2f16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x half> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -208,9 +208,9 @@ define <vscale x 2 x i64> @vfptosi_nxv2f16_nxv2i64(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptosi_nxv2f16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x half> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -220,9 +220,9 @@ define <vscale x 2 x i64> @vfptoui_nxv2f16_nxv2i64(<vscale x 2 x half> %va) {
; CHECK-LABEL: vfptoui_nxv2f16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x half> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -232,9 +232,9 @@ define <vscale x 4 x i1> @vfptosi_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptosi_nxv4f16_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x half> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
@@ -244,9 +244,9 @@ define <vscale x 4 x i1> @vfptoui_nxv4f16_nxv4i1(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptoui_nxv4f16_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x half> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
@@ -256,8 +256,8 @@ define <vscale x 4 x i8> @vfptosi_nxv4f16_nxv4i8(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptosi_nxv4f16_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x half> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
@@ -267,8 +267,8 @@ define <vscale x 4 x i8> @vfptoui_nxv4f16_nxv4i8(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptoui_nxv4f16_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x half> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
@@ -298,8 +298,8 @@ define <vscale x 4 x i32> @vfptosi_nxv4f16_nxv4i32(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptosi_nxv4f16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x half> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -309,8 +309,8 @@ define <vscale x 4 x i32> @vfptoui_nxv4f16_nxv4i32(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptoui_nxv4f16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x half> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -320,9 +320,9 @@ define <vscale x 4 x i64> @vfptosi_nxv4f16_nxv4i64(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptosi_nxv4f16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v8
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x half> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -332,9 +332,9 @@ define <vscale x 4 x i64> @vfptoui_nxv4f16_nxv4i64(<vscale x 4 x half> %va) {
; CHECK-LABEL: vfptoui_nxv4f16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v8
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x half> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -344,9 +344,9 @@ define <vscale x 8 x i1> @vfptosi_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptosi_nxv8f16_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x half> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
@@ -356,9 +356,9 @@ define <vscale x 8 x i1> @vfptoui_nxv8f16_nxv8i1(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptoui_nxv8f16_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x half> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
@@ -368,8 +368,8 @@ define <vscale x 8 x i8> @vfptosi_nxv8f16_nxv8i8(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptosi_nxv8f16_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x half> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
@@ -379,8 +379,8 @@ define <vscale x 8 x i8> @vfptoui_nxv8f16_nxv8i8(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptoui_nxv8f16_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x half> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
@@ -410,8 +410,8 @@ define <vscale x 8 x i32> @vfptosi_nxv8f16_nxv8i32(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptosi_nxv8f16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x half> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -421,8 +421,8 @@ define <vscale x 8 x i32> @vfptoui_nxv8f16_nxv8i32(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptoui_nxv8f16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x half> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -432,9 +432,9 @@ define <vscale x 8 x i64> @vfptosi_nxv8f16_nxv8i64(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptosi_nxv8f16_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v8
+; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v16
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x half> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
@@ -444,9 +444,9 @@ define <vscale x 8 x i64> @vfptoui_nxv8f16_nxv8i64(<vscale x 8 x half> %va) {
; CHECK-LABEL: vfptoui_nxv8f16_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v8
+; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v16
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x half> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
@@ -456,9 +456,9 @@ define <vscale x 16 x i1> @vfptosi_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; CHECK-LABEL: vfptosi_nxv16f16_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vand.vi v26, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 16 x half> %va to <vscale x 16 x i1>
ret <vscale x 16 x i1> %evec
@@ -468,9 +468,9 @@ define <vscale x 16 x i1> @vfptoui_nxv16f16_nxv16i1(<vscale x 16 x half> %va) {
; CHECK-LABEL: vfptoui_nxv16f16_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vand.vi v26, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 16 x half> %va to <vscale x 16 x i1>
ret <vscale x 16 x i1> %evec
@@ -480,8 +480,8 @@ define <vscale x 16 x i8> @vfptosi_nxv16f16_nxv16i8(<vscale x 16 x half> %va) {
; CHECK-LABEL: vfptosi_nxv16f16_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = fptosi <vscale x 16 x half> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec
@@ -491,8 +491,8 @@ define <vscale x 16 x i8> @vfptoui_nxv16f16_nxv16i8(<vscale x 16 x half> %va) {
; CHECK-LABEL: vfptoui_nxv16f16_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = fptoui <vscale x 16 x half> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec
@@ -544,9 +544,9 @@ define <vscale x 32 x i1> @vfptosi_nxv32f16_nxv32i1(<vscale x 32 x half> %va) {
; CHECK-LABEL: vfptosi_nxv32f16_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vand.vi v28, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vand.vi v8, v16, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 32 x half> %va to <vscale x 32 x i1>
ret <vscale x 32 x i1> %evec
@@ -556,9 +556,9 @@ define <vscale x 32 x i1> @vfptoui_nxv32f16_nxv32i1(<vscale x 32 x half> %va) {
; CHECK-LABEL: vfptoui_nxv32f16_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vand.vi v28, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vand.vi v8, v16, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 32 x half> %va to <vscale x 32 x i1>
ret <vscale x 32 x i1> %evec
@@ -568,8 +568,8 @@ define <vscale x 32 x i8> @vfptosi_nxv32f16_nxv32i8(<vscale x 32 x half> %va) {
; CHECK-LABEL: vfptosi_nxv32f16_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = fptosi <vscale x 32 x half> %va to <vscale x 32 x i8>
ret <vscale x 32 x i8> %evec
@@ -579,8 +579,8 @@ define <vscale x 32 x i8> @vfptoui_nxv32f16_nxv32i8(<vscale x 32 x half> %va) {
; CHECK-LABEL: vfptoui_nxv32f16_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = fptoui <vscale x 32 x half> %va to <vscale x 32 x i8>
ret <vscale x 32 x i8> %evec
@@ -610,9 +610,9 @@ define <vscale x 1 x i1> @vfptosi_nxv1f32_nxv1i1(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptosi_nxv1f32_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x float> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
@@ -622,9 +622,9 @@ define <vscale x 1 x i1> @vfptoui_nxv1f32_nxv1i1(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptoui_nxv1f32_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x float> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
@@ -634,9 +634,9 @@ define <vscale x 1 x i8> @vfptosi_nxv1f32_nxv1i8(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptosi_nxv1f32_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x float> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
@@ -646,9 +646,9 @@ define <vscale x 1 x i8> @vfptoui_nxv1f32_nxv1i8(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptoui_nxv1f32_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x float> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
@@ -658,8 +658,8 @@ define <vscale x 1 x i16> @vfptosi_nxv1f32_nxv1i16(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptosi_nxv1f32_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x float> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -669,8 +669,8 @@ define <vscale x 1 x i16> @vfptoui_nxv1f32_nxv1i16(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptoui_nxv1f32_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x float> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -700,8 +700,8 @@ define <vscale x 1 x i64> @vfptosi_nxv1f32_nxv1i64(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptosi_nxv1f32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x float> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -711,8 +711,8 @@ define <vscale x 1 x i64> @vfptoui_nxv1f32_nxv1i64(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfptoui_nxv1f32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x float> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
@@ -722,9 +722,9 @@ define <vscale x 2 x i1> @vfptosi_nxv2f32_nxv2i1(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptosi_nxv2f32_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x float> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
@@ -734,9 +734,9 @@ define <vscale x 2 x i1> @vfptoui_nxv2f32_nxv2i1(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptoui_nxv2f32_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x float> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
@@ -746,9 +746,9 @@ define <vscale x 2 x i8> @vfptosi_nxv2f32_nxv2i8(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptosi_nxv2f32_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x float> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
@@ -758,9 +758,9 @@ define <vscale x 2 x i8> @vfptoui_nxv2f32_nxv2i8(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptoui_nxv2f32_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x float> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
@@ -770,8 +770,8 @@ define <vscale x 2 x i16> @vfptosi_nxv2f32_nxv2i16(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptosi_nxv2f32_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x float> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -781,8 +781,8 @@ define <vscale x 2 x i16> @vfptoui_nxv2f32_nxv2i16(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptoui_nxv2f32_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x float> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -812,8 +812,8 @@ define <vscale x 2 x i64> @vfptosi_nxv2f32_nxv2i64(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptosi_nxv2f32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x float> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -823,8 +823,8 @@ define <vscale x 2 x i64> @vfptoui_nxv2f32_nxv2i64(<vscale x 2 x float> %va) {
; CHECK-LABEL: vfptoui_nxv2f32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x float> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
@@ -834,9 +834,9 @@ define <vscale x 4 x i1> @vfptosi_nxv4f32_nxv4i1(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptosi_nxv4f32_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x float> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
@@ -846,9 +846,9 @@ define <vscale x 4 x i1> @vfptoui_nxv4f32_nxv4i1(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptoui_nxv4f32_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x float> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
@@ -858,9 +858,9 @@ define <vscale x 4 x i8> @vfptosi_nxv4f32_nxv4i8(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptosi_nxv4f32_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x float> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
@@ -870,9 +870,9 @@ define <vscale x 4 x i8> @vfptoui_nxv4f32_nxv4i8(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptoui_nxv4f32_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x float> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
@@ -882,8 +882,8 @@ define <vscale x 4 x i16> @vfptosi_nxv4f32_nxv4i16(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptosi_nxv4f32_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x float> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -893,8 +893,8 @@ define <vscale x 4 x i16> @vfptoui_nxv4f32_nxv4i16(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptoui_nxv4f32_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x float> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -924,8 +924,8 @@ define <vscale x 4 x i64> @vfptosi_nxv4f32_nxv4i64(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptosi_nxv4f32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x float> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -935,8 +935,8 @@ define <vscale x 4 x i64> @vfptoui_nxv4f32_nxv4i64(<vscale x 4 x float> %va) {
; CHECK-LABEL: vfptoui_nxv4f32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x float> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
@@ -946,9 +946,9 @@ define <vscale x 8 x i1> @vfptosi_nxv8f32_nxv8i1(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptosi_nxv8f32_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vand.vi v26, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x float> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
@@ -958,9 +958,9 @@ define <vscale x 8 x i1> @vfptoui_nxv8f32_nxv8i1(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptoui_nxv8f32_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vand.vi v26, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x float> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
@@ -970,9 +970,9 @@ define <vscale x 8 x i8> @vfptosi_nxv8f32_nxv8i8(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptosi_nxv8f32_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x float> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
@@ -982,9 +982,9 @@ define <vscale x 8 x i8> @vfptoui_nxv8f32_nxv8i8(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptoui_nxv8f32_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x float> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
@@ -994,8 +994,8 @@ define <vscale x 8 x i16> @vfptosi_nxv8f32_nxv8i16(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptosi_nxv8f32_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x float> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -1005,8 +1005,8 @@ define <vscale x 8 x i16> @vfptoui_nxv8f32_nxv8i16(<vscale x 8 x float> %va) {
; CHECK-LABEL: vfptoui_nxv8f32_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x float> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -1058,9 +1058,9 @@ define <vscale x 16 x i1> @vfptosi_nxv16f32_nxv16i1(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfptosi_nxv16f32_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vand.vi v28, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vand.vi v8, v16, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 16 x float> %va to <vscale x 16 x i1>
ret <vscale x 16 x i1> %evec
@@ -1070,9 +1070,9 @@ define <vscale x 16 x i1> @vfptoui_nxv16f32_nxv16i1(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfptoui_nxv16f32_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vand.vi v28, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vand.vi v8, v16, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 16 x float> %va to <vscale x 16 x i1>
ret <vscale x 16 x i1> %evec
@@ -1082,9 +1082,9 @@ define <vscale x 16 x i8> @vfptosi_nxv16f32_nxv16i8(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfptosi_nxv16f32_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 16 x float> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec
@@ -1094,9 +1094,9 @@ define <vscale x 16 x i8> @vfptoui_nxv16f32_nxv16i8(<vscale x 16 x float> %va) {
; CHECK-LABEL: vfptoui_nxv16f32_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 16 x float> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %evec
@@ -1106,8 +1106,8 @@ define <vscale x 16 x i16> @vfptosi_nxv16f32_nxv16i16(<vscale x 16 x float> %va)
; CHECK-LABEL: vfptosi_nxv16f32_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = fptosi <vscale x 16 x float> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
@@ -1117,8 +1117,8 @@ define <vscale x 16 x i16> @vfptoui_nxv16f32_nxv16i16(<vscale x 16 x float> %va)
; CHECK-LABEL: vfptoui_nxv16f32_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = fptoui <vscale x 16 x float> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
@@ -1148,9 +1148,9 @@ define <vscale x 1 x i1> @vfptosi_nxv1f64_nxv1i1(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptosi_nxv1f64_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
@@ -1160,9 +1160,9 @@ define <vscale x 1 x i1> @vfptoui_nxv1f64_nxv1i1(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptoui_nxv1f64_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vand.vi v8, v9, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i1>
ret <vscale x 1 x i1> %evec
@@ -1172,11 +1172,11 @@ define <vscale x 1 x i8> @vfptosi_nxv1f64_nxv1i8(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptosi_nxv1f64_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
@@ -1186,11 +1186,11 @@ define <vscale x 1 x i8> @vfptoui_nxv1f64_nxv1i8(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptoui_nxv1f64_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %evec
@@ -1200,9 +1200,9 @@ define <vscale x 1 x i16> @vfptosi_nxv1f64_nxv1i16(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptosi_nxv1f64_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -1212,9 +1212,9 @@ define <vscale x 1 x i16> @vfptoui_nxv1f64_nxv1i16(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptoui_nxv1f64_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
@@ -1224,8 +1224,8 @@ define <vscale x 1 x i32> @vfptosi_nxv1f64_nxv1i32(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptosi_nxv1f64_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptosi <vscale x 1 x double> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -1235,8 +1235,8 @@ define <vscale x 1 x i32> @vfptoui_nxv1f64_nxv1i32(<vscale x 1 x double> %va) {
; CHECK-LABEL: vfptoui_nxv1f64_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = fptoui <vscale x 1 x double> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
@@ -1266,9 +1266,9 @@ define <vscale x 2 x i1> @vfptosi_nxv2f64_nxv2i1(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptosi_nxv2f64_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
@@ -1278,9 +1278,9 @@ define <vscale x 2 x i1> @vfptoui_nxv2f64_nxv2i1(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptoui_nxv2f64_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vand.vi v25, v25, 1
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vand.vi v8, v10, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i1>
ret <vscale x 2 x i1> %evec
@@ -1290,11 +1290,11 @@ define <vscale x 2 x i8> @vfptosi_nxv2f64_nxv2i8(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptosi_nxv2f64_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
@@ -1304,11 +1304,11 @@ define <vscale x 2 x i8> @vfptoui_nxv2f64_nxv2i8(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptoui_nxv2f64_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %evec
@@ -1318,9 +1318,9 @@ define <vscale x 2 x i16> @vfptosi_nxv2f64_nxv2i16(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptosi_nxv2f64_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -1330,9 +1330,9 @@ define <vscale x 2 x i16> @vfptoui_nxv2f64_nxv2i16(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptoui_nxv2f64_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
@@ -1342,8 +1342,8 @@ define <vscale x 2 x i32> @vfptosi_nxv2f64_nxv2i32(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptosi_nxv2f64_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = fptosi <vscale x 2 x double> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -1353,8 +1353,8 @@ define <vscale x 2 x i32> @vfptoui_nxv2f64_nxv2i32(<vscale x 2 x double> %va) {
; CHECK-LABEL: vfptoui_nxv2f64_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = fptoui <vscale x 2 x double> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
@@ -1384,9 +1384,9 @@ define <vscale x 4 x i1> @vfptosi_nxv4f64_nxv4i1(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptosi_nxv4f64_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vand.vi v26, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
@@ -1396,9 +1396,9 @@ define <vscale x 4 x i1> @vfptoui_nxv4f64_nxv4i1(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptoui_nxv4f64_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vand.vi v26, v26, 1
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vand.vi v8, v12, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i1>
ret <vscale x 4 x i1> %evec
@@ -1408,11 +1408,11 @@ define <vscale x 4 x i8> @vfptosi_nxv4f64_nxv4i8(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptosi_nxv4f64_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
@@ -1422,11 +1422,11 @@ define <vscale x 4 x i8> @vfptoui_nxv4f64_nxv4i8(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptoui_nxv4f64_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %evec
@@ -1436,9 +1436,9 @@ define <vscale x 4 x i16> @vfptosi_nxv4f64_nxv4i16(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptosi_nxv4f64_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -1448,9 +1448,9 @@ define <vscale x 4 x i16> @vfptoui_nxv4f64_nxv4i16(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptoui_nxv4f64_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
@@ -1460,8 +1460,8 @@ define <vscale x 4 x i32> @vfptosi_nxv4f64_nxv4i32(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptosi_nxv4f64_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = fptosi <vscale x 4 x double> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -1471,8 +1471,8 @@ define <vscale x 4 x i32> @vfptoui_nxv4f64_nxv4i32(<vscale x 4 x double> %va) {
; CHECK-LABEL: vfptoui_nxv4f64_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = fptoui <vscale x 4 x double> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
@@ -1502,9 +1502,9 @@ define <vscale x 8 x i1> @vfptosi_nxv8f64_nxv8i1(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptosi_nxv8f64_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vand.vi v28, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vand.vi v8, v16, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
@@ -1514,9 +1514,9 @@ define <vscale x 8 x i1> @vfptoui_nxv8f64_nxv8i1(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptoui_nxv8f64_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vand.vi v28, v28, 1
-; CHECK-NEXT: vmsne.vi v0, v28, 0
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vand.vi v8, v16, 1
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i1>
ret <vscale x 8 x i1> %evec
@@ -1526,11 +1526,11 @@ define <vscale x 8 x i8> @vfptosi_nxv8f64_nxv8i8(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptosi_nxv8f64_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v28, 0
+; CHECK-NEXT: vnsrl.wi v10, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
@@ -1540,11 +1540,11 @@ define <vscale x 8 x i8> @vfptoui_nxv8f64_nxv8i8(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptoui_nxv8f64_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v28, 0
+; CHECK-NEXT: vnsrl.wi v10, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %evec
@@ -1554,9 +1554,9 @@ define <vscale x 8 x i16> @vfptosi_nxv8f64_nxv8i16(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptosi_nxv8f64_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -1566,9 +1566,9 @@ define <vscale x 8 x i16> @vfptoui_nxv8f64_nxv8i16(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptoui_nxv8f64_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
@@ -1578,8 +1578,8 @@ define <vscale x 8 x i32> @vfptosi_nxv8f64_nxv8i32(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptosi_nxv8f64_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = fptosi <vscale x 8 x double> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
@@ -1589,8 +1589,8 @@ define <vscale x 8 x i32> @vfptoui_nxv8f64_nxv8i32(<vscale x 8 x double> %va) {
; CHECK-LABEL: vfptoui_nxv8f64_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = fptoui <vscale x 8 x double> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
index 0ac7d519e33bc..ccbb7c3d46cd5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
@@ -9,15 +9,15 @@ define <vscale x 1 x half> @vfptrunc_nxv1f32_nxv1f16(<vscale x 1 x float> %va) {
; RV32-LABEL: vfptrunc_nxv1f32_nxv1f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfncvt.f.f.w v9, v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv1f32_nxv1f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfncvt.f.f.w v9, v8
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%evec = fptrunc <vscale x 1 x float> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -28,15 +28,15 @@ define <vscale x 2 x half> @vfptrunc_nxv2f32_nxv2f16(<vscale x 2 x float> %va) {
; RV32-LABEL: vfptrunc_nxv2f32_nxv2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfncvt.f.f.w v9, v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv2f32_nxv2f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfncvt.f.f.w v9, v8
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%evec = fptrunc <vscale x 2 x float> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -47,15 +47,15 @@ define <vscale x 4 x half> @vfptrunc_nxv4f32_nxv4f16(<vscale x 4 x float> %va) {
; RV32-LABEL: vfptrunc_nxv4f32_nxv4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfncvt.f.f.w v10, v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv4f32_nxv4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfncvt.f.f.w v10, v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%evec = fptrunc <vscale x 4 x float> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -66,15 +66,15 @@ define <vscale x 8 x half> @vfptrunc_nxv8f32_nxv8f16(<vscale x 8 x float> %va) {
; RV32-LABEL: vfptrunc_nxv8f32_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v26, v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vfncvt.f.f.w v12, v8
+; RV32-NEXT: vmv2r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv8f32_nxv8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v26, v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vfncvt.f.f.w v12, v8
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%evec = fptrunc <vscale x 8 x float> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -85,15 +85,15 @@ define <vscale x 16 x half> @vfptrunc_nxv16f32_nxv16f16(<vscale x 16 x float> %v
; RV32-LABEL: vfptrunc_nxv16f32_nxv16f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v28, v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vfncvt.f.f.w v16, v8
+; RV32-NEXT: vmv4r.v v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv16f32_nxv16f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v28, v8
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vfncvt.f.f.w v16, v8
+; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: ret
%evec = fptrunc <vscale x 16 x float> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -104,17 +104,17 @@ define <vscale x 1 x half> @vfptrunc_nxv1f64_nxv1f16(<vscale x 1 x double> %va)
; RV32-LABEL: vfptrunc_nxv1f64_nxv1f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV32-NEXT: vfncvt.rod.f.f.w v25, v8
+; RV32-NEXT: vfncvt.rod.f.f.w v9, v8
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v8, v25
+; RV32-NEXT: vfncvt.f.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv1f64_nxv1f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV64-NEXT: vfncvt.rod.f.f.w v25, v8
+; RV64-NEXT: vfncvt.rod.f.f.w v9, v8
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v8, v25
+; RV64-NEXT: vfncvt.f.f.w v8, v9
; RV64-NEXT: ret
%evec = fptrunc <vscale x 1 x double> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -125,15 +125,15 @@ define <vscale x 1 x float> @vfptrunc_nxv1f64_nxv1f32(<vscale x 1 x double> %va)
; RV32-LABEL: vfptrunc_nxv1f64_nxv1f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfncvt.f.f.w v9, v8
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv1f64_nxv1f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfncvt.f.f.w v9, v8
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%evec = fptrunc <vscale x 1 x double> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -144,17 +144,17 @@ define <vscale x 2 x half> @vfptrunc_nxv2f64_nxv2f16(<vscale x 2 x double> %va)
; RV32-LABEL: vfptrunc_nxv2f64_nxv2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vfncvt.rod.f.f.w v25, v8
+; RV32-NEXT: vfncvt.rod.f.f.w v10, v8
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v8, v25
+; RV32-NEXT: vfncvt.f.f.w v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv2f64_nxv2f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vfncvt.rod.f.f.w v25, v8
+; RV64-NEXT: vfncvt.rod.f.f.w v10, v8
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v8, v25
+; RV64-NEXT: vfncvt.f.f.w v8, v10
; RV64-NEXT: ret
%evec = fptrunc <vscale x 2 x double> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -165,15 +165,15 @@ define <vscale x 2 x float> @vfptrunc_nxv2f64_nxv2f32(<vscale x 2 x double> %va)
; RV32-LABEL: vfptrunc_nxv2f64_nxv2f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v25, v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vfncvt.f.f.w v10, v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv2f64_nxv2f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v25, v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vfncvt.f.f.w v10, v8
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%evec = fptrunc <vscale x 2 x double> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -184,17 +184,17 @@ define <vscale x 4 x half> @vfptrunc_nxv4f64_nxv4f16(<vscale x 4 x double> %va)
; RV32-LABEL: vfptrunc_nxv4f64_nxv4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV32-NEXT: vfncvt.rod.f.f.w v26, v8
+; RV32-NEXT: vfncvt.rod.f.f.w v12, v8
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v8, v26
+; RV32-NEXT: vfncvt.f.f.w v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv4f64_nxv4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV64-NEXT: vfncvt.rod.f.f.w v26, v8
+; RV64-NEXT: vfncvt.rod.f.f.w v12, v8
; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v8, v26
+; RV64-NEXT: vfncvt.f.f.w v8, v12
; RV64-NEXT: ret
%evec = fptrunc <vscale x 4 x double> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -205,15 +205,15 @@ define <vscale x 4 x float> @vfptrunc_nxv4f64_nxv4f32(<vscale x 4 x double> %va)
; RV32-LABEL: vfptrunc_nxv4f64_nxv4f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v26, v8
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vfncvt.f.f.w v12, v8
+; RV32-NEXT: vmv2r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv4f64_nxv4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v26, v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vfncvt.f.f.w v12, v8
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%evec = fptrunc <vscale x 4 x double> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -224,17 +224,17 @@ define <vscale x 8 x half> @vfptrunc_nxv8f64_nxv8f16(<vscale x 8 x double> %va)
; RV32-LABEL: vfptrunc_nxv8f64_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; RV32-NEXT: vfncvt.rod.f.f.w v28, v8
+; RV32-NEXT: vfncvt.rod.f.f.w v16, v8
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v8, v28
+; RV32-NEXT: vfncvt.f.f.w v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv8f64_nxv8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; RV64-NEXT: vfncvt.rod.f.f.w v28, v8
+; RV64-NEXT: vfncvt.rod.f.f.w v16, v8
; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v8, v28
+; RV64-NEXT: vfncvt.f.f.w v8, v16
; RV64-NEXT: ret
%evec = fptrunc <vscale x 8 x double> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -245,15 +245,15 @@ define <vscale x 8 x float> @vfptrunc_nxv8f64_nxv8f32(<vscale x 8 x double> %va)
; RV32-LABEL: vfptrunc_nxv8f64_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; RV32-NEXT: vfncvt.f.f.w v28, v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vfncvt.f.f.w v16, v8
+; RV32-NEXT: vmv4r.v v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: vfptrunc_nxv8f64_nxv8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; RV64-NEXT: vfncvt.f.f.w v28, v8
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vfncvt.f.f.w v16, v8
+; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: ret
%evec = fptrunc <vscale x 8 x double> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
index 8aa3875768c8b..22d0a1adeb750 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
@@ -10,9 +10,9 @@ define <vscale x 1 x half> @vfrdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
; CHECK-LABEL: vfrdiv_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -24,9 +24,9 @@ define <vscale x 1 x half> @vfrdiv_vf_nxv1f16_unmasked(<vscale x 1 x half> %va,
; CHECK-LABEL: vfrdiv_vf_nxv1f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8
+; CHECK-NEXT: vfdiv.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -42,9 +42,9 @@ define <vscale x 2 x half> @vfrdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b,
; CHECK-LABEL: vfrdiv_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -56,9 +56,9 @@ define <vscale x 2 x half> @vfrdiv_vf_nxv2f16_unmasked(<vscale x 2 x half> %va,
; CHECK-LABEL: vfrdiv_vf_nxv2f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8
+; CHECK-NEXT: vfdiv.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -74,9 +74,9 @@ define <vscale x 4 x half> @vfrdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b,
; CHECK-LABEL: vfrdiv_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -88,9 +88,9 @@ define <vscale x 4 x half> @vfrdiv_vf_nxv4f16_unmasked(<vscale x 4 x half> %va,
; CHECK-LABEL: vfrdiv_vf_nxv4f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8
+; CHECK-NEXT: vfdiv.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -106,9 +106,9 @@ define <vscale x 8 x half> @vfrdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
; CHECK-LABEL: vfrdiv_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -120,9 +120,9 @@ define <vscale x 8 x half> @vfrdiv_vf_nxv8f16_unmasked(<vscale x 8 x half> %va,
; CHECK-LABEL: vfrdiv_vf_nxv8f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8
+; CHECK-NEXT: vfdiv.vv v8, v10, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -138,9 +138,9 @@ define <vscale x 16 x half> @vfrdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %
; CHECK-LABEL: vfrdiv_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -152,9 +152,9 @@ define <vscale x 16 x half> @vfrdiv_vf_nxv16f16_unmasked(<vscale x 16 x half> %v
; CHECK-LABEL: vfrdiv_vf_nxv16f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8
+; CHECK-NEXT: vfdiv.vv v8, v12, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -202,9 +202,9 @@ define <vscale x 1 x float> @vfrdiv_vf_nxv1f32(<vscale x 1 x float> %va, float %
; CHECK-LABEL: vfrdiv_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -216,9 +216,9 @@ define <vscale x 1 x float> @vfrdiv_vf_nxv1f32_unmasked(<vscale x 1 x float> %va
; CHECK-LABEL: vfrdiv_vf_nxv1f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8
+; CHECK-NEXT: vfdiv.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -234,9 +234,9 @@ define <vscale x 2 x float> @vfrdiv_vf_nxv2f32(<vscale x 2 x float> %va, float %
; CHECK-LABEL: vfrdiv_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -248,9 +248,9 @@ define <vscale x 2 x float> @vfrdiv_vf_nxv2f32_unmasked(<vscale x 2 x float> %va
; CHECK-LABEL: vfrdiv_vf_nxv2f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8
+; CHECK-NEXT: vfdiv.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -266,9 +266,9 @@ define <vscale x 4 x float> @vfrdiv_vf_nxv4f32(<vscale x 4 x float> %va, float %
; CHECK-LABEL: vfrdiv_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -280,9 +280,9 @@ define <vscale x 4 x float> @vfrdiv_vf_nxv4f32_unmasked(<vscale x 4 x float> %va
; CHECK-LABEL: vfrdiv_vf_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8
+; CHECK-NEXT: vfdiv.vv v8, v10, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -298,9 +298,9 @@ define <vscale x 8 x float> @vfrdiv_vf_nxv8f32(<vscale x 8 x float> %va, float %
; CHECK-LABEL: vfrdiv_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -312,9 +312,9 @@ define <vscale x 8 x float> @vfrdiv_vf_nxv8f32_unmasked(<vscale x 8 x float> %va
; CHECK-LABEL: vfrdiv_vf_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8
+; CHECK-NEXT: vfdiv.vv v8, v12, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -362,9 +362,9 @@ define <vscale x 1 x double> @vfrdiv_vf_nxv1f64(<vscale x 1 x double> %va, doubl
; CHECK-LABEL: vfrdiv_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -376,9 +376,9 @@ define <vscale x 1 x double> @vfrdiv_vf_nxv1f64_unmasked(<vscale x 1 x double> %
; CHECK-LABEL: vfrdiv_vf_nxv1f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v25, v8
+; CHECK-NEXT: vfdiv.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -394,9 +394,9 @@ define <vscale x 2 x double> @vfrdiv_vf_nxv2f64(<vscale x 2 x double> %va, doubl
; CHECK-LABEL: vfrdiv_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -408,9 +408,9 @@ define <vscale x 2 x double> @vfrdiv_vf_nxv2f64_unmasked(<vscale x 2 x double> %
; CHECK-LABEL: vfrdiv_vf_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v26, v8
+; CHECK-NEXT: vfdiv.vv v8, v10, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -426,9 +426,9 @@ define <vscale x 4 x double> @vfrdiv_vf_nxv4f64(<vscale x 4 x double> %va, doubl
; CHECK-LABEL: vfrdiv_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
@@ -440,9 +440,9 @@ define <vscale x 4 x double> @vfrdiv_vf_nxv4f64_unmasked(<vscale x 4 x double> %
; CHECK-LABEL: vfrdiv_vf_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfdiv.vv v8, v28, v8
+; CHECK-NEXT: vfdiv.vv v8, v12, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
index 13f5cd7766334..fdffa513d0e63 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
@@ -10,9 +10,9 @@ define <vscale x 1 x half> @vfrsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
; CHECK-LABEL: vfrsub_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -24,9 +24,9 @@ define <vscale x 1 x half> @vfrsub_vf_nxv1f16_unmasked(<vscale x 1 x half> %va,
; CHECK-LABEL: vfrsub_vf_nxv1f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -42,9 +42,9 @@ define <vscale x 2 x half> @vfrsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b,
; CHECK-LABEL: vfrsub_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -56,9 +56,9 @@ define <vscale x 2 x half> @vfrsub_vf_nxv2f16_unmasked(<vscale x 2 x half> %va,
; CHECK-LABEL: vfrsub_vf_nxv2f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -74,9 +74,9 @@ define <vscale x 4 x half> @vfrsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b,
; CHECK-LABEL: vfrsub_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -88,9 +88,9 @@ define <vscale x 4 x half> @vfrsub_vf_nxv4f16_unmasked(<vscale x 4 x half> %va,
; CHECK-LABEL: vfrsub_vf_nxv4f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -106,9 +106,9 @@ define <vscale x 8 x half> @vfrsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
; CHECK-LABEL: vfrsub_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -120,9 +120,9 @@ define <vscale x 8 x half> @vfrsub_vf_nxv8f16_unmasked(<vscale x 8 x half> %va,
; CHECK-LABEL: vfrsub_vf_nxv8f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8
+; CHECK-NEXT: vfsub.vv v8, v10, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -138,9 +138,9 @@ define <vscale x 16 x half> @vfrsub_vf_nxv16f16(<vscale x 16 x half> %va, half %
; CHECK-LABEL: vfrsub_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -152,9 +152,9 @@ define <vscale x 16 x half> @vfrsub_vf_nxv16f16_unmasked(<vscale x 16 x half> %v
; CHECK-LABEL: vfrsub_vf_nxv16f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8
+; CHECK-NEXT: vfsub.vv v8, v12, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -202,9 +202,9 @@ define <vscale x 1 x float> @vfrsub_vf_nxv1f32(<vscale x 1 x float> %va, float %
; CHECK-LABEL: vfrsub_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -216,9 +216,9 @@ define <vscale x 1 x float> @vfrsub_vf_nxv1f32_unmasked(<vscale x 1 x float> %va
; CHECK-LABEL: vfrsub_vf_nxv1f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -234,9 +234,9 @@ define <vscale x 2 x float> @vfrsub_vf_nxv2f32(<vscale x 2 x float> %va, float %
; CHECK-LABEL: vfrsub_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -248,9 +248,9 @@ define <vscale x 2 x float> @vfrsub_vf_nxv2f32_unmasked(<vscale x 2 x float> %va
; CHECK-LABEL: vfrsub_vf_nxv2f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -266,9 +266,9 @@ define <vscale x 4 x float> @vfrsub_vf_nxv4f32(<vscale x 4 x float> %va, float %
; CHECK-LABEL: vfrsub_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -280,9 +280,9 @@ define <vscale x 4 x float> @vfrsub_vf_nxv4f32_unmasked(<vscale x 4 x float> %va
; CHECK-LABEL: vfrsub_vf_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8
+; CHECK-NEXT: vfsub.vv v8, v10, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -298,9 +298,9 @@ define <vscale x 8 x float> @vfrsub_vf_nxv8f32(<vscale x 8 x float> %va, float %
; CHECK-LABEL: vfrsub_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -312,9 +312,9 @@ define <vscale x 8 x float> @vfrsub_vf_nxv8f32_unmasked(<vscale x 8 x float> %va
; CHECK-LABEL: vfrsub_vf_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8
+; CHECK-NEXT: vfsub.vv v8, v12, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -362,9 +362,9 @@ define <vscale x 1 x double> @vfrsub_vf_nxv1f64(<vscale x 1 x double> %va, doubl
; CHECK-LABEL: vfrsub_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -376,9 +376,9 @@ define <vscale x 1 x double> @vfrsub_vf_nxv1f64_unmasked(<vscale x 1 x double> %
; CHECK-LABEL: vfrsub_vf_nxv1f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v8, v9, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -394,9 +394,9 @@ define <vscale x 2 x double> @vfrsub_vf_nxv2f64(<vscale x 2 x double> %va, doubl
; CHECK-LABEL: vfrsub_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -408,9 +408,9 @@ define <vscale x 2 x double> @vfrsub_vf_nxv2f64_unmasked(<vscale x 2 x double> %
; CHECK-LABEL: vfrsub_vf_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v26, v8
+; CHECK-NEXT: vfsub.vv v8, v10, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -426,9 +426,9 @@ define <vscale x 4 x double> @vfrsub_vf_nxv4f64(<vscale x 4 x double> %va, doubl
; CHECK-LABEL: vfrsub_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t
+; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
@@ -440,9 +440,9 @@ define <vscale x 4 x double> @vfrsub_vf_nxv4f64_unmasked(<vscale x 4 x double> %
; CHECK-LABEL: vfrsub_vf_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v28, v8
+; CHECK-NEXT: vfsub.vv v8, v12, v8
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
index f34ad4c0298ac..9973aafeed5af 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
@@ -11,8 +11,8 @@ define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
@@ -59,8 +59,8 @@ define <vscale x 2 x half> @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
@@ -107,8 +107,8 @@ define <vscale x 4 x half> @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
@@ -155,8 +155,8 @@ define <vscale x 8 x half> @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfslide1up.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
@@ -203,8 +203,8 @@ define <vscale x 16 x half> @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfslide1up.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
@@ -299,8 +299,8 @@ define <vscale x 1 x float> @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
@@ -347,8 +347,8 @@ define <vscale x 2 x float> @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
@@ -395,8 +395,8 @@ define <vscale x 4 x float> @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfslide1up.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
@@ -443,8 +443,8 @@ define <vscale x 8 x float> @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfslide1up.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
@@ -542,8 +542,8 @@ define <vscale x 1 x double> @intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64(<vscal
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -598,8 +598,8 @@ define <vscale x 2 x double> @intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64(<vscal
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfslide1up.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -654,8 +654,8 @@ define <vscale x 4 x double> @intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64(<vscal
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfslide1up.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
index 6d6f8ff50b98f..c2df95c35536e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
@@ -11,8 +11,8 @@ define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
@@ -59,8 +59,8 @@ define <vscale x 2 x half> @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
@@ -107,8 +107,8 @@ define <vscale x 4 x half> @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
@@ -155,8 +155,8 @@ define <vscale x 8 x half> @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfslide1up.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
@@ -203,8 +203,8 @@ define <vscale x 16 x half> @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfslide1up.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
@@ -299,8 +299,8 @@ define <vscale x 1 x float> @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
@@ -347,8 +347,8 @@ define <vscale x 2 x float> @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
@@ -395,8 +395,8 @@ define <vscale x 4 x float> @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfslide1up.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
@@ -443,8 +443,8 @@ define <vscale x 8 x float> @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfslide1up.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
@@ -539,8 +539,8 @@ define <vscale x 1 x double> @intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vfslide1up.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfslide1up.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64(
@@ -587,8 +587,8 @@ define <vscale x 2 x double> @intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vfslide1up.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfslide1up.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64(
@@ -635,8 +635,8 @@ define <vscale x 4 x double> @intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vfslide1up.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfslide1up.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
index 131ae96ad708d..a5bff96d636ef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
@@ -32,9 +32,9 @@ define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <
; CHECK-LABEL: vfsub_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -46,9 +46,9 @@ define <vscale x 1 x half> @vfsub_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h
; CHECK-LABEL: vfsub_vf_nxv1f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25
+; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
@@ -86,9 +86,9 @@ define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b, <
; CHECK-LABEL: vfsub_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -100,9 +100,9 @@ define <vscale x 2 x half> @vfsub_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h
; CHECK-LABEL: vfsub_vf_nxv2f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25
+; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
@@ -140,9 +140,9 @@ define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b, <
; CHECK-LABEL: vfsub_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -154,9 +154,9 @@ define <vscale x 4 x half> @vfsub_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h
; CHECK-LABEL: vfsub_vf_nxv4f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25
+; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
@@ -194,9 +194,9 @@ define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <
; CHECK-LABEL: vfsub_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -208,9 +208,9 @@ define <vscale x 8 x half> @vfsub_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h
; CHECK-LABEL: vfsub_vf_nxv8f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26
+; CHECK-NEXT: vfsub.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
@@ -248,9 +248,9 @@ define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b
; CHECK-LABEL: vfsub_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -262,9 +262,9 @@ define <vscale x 16 x half> @vfsub_vf_nxv16f16_unmasked(<vscale x 16 x half> %va
; CHECK-LABEL: vfsub_vf_nxv16f16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28
+; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
@@ -356,9 +356,9 @@ define <vscale x 1 x float> @vfsub_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK-LABEL: vfsub_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -370,9 +370,9 @@ define <vscale x 1 x float> @vfsub_vf_nxv1f32_unmasked(<vscale x 1 x float> %va,
; CHECK-LABEL: vfsub_vf_nxv1f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25
+; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
@@ -410,9 +410,9 @@ define <vscale x 2 x float> @vfsub_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK-LABEL: vfsub_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -424,9 +424,9 @@ define <vscale x 2 x float> @vfsub_vf_nxv2f32_unmasked(<vscale x 2 x float> %va,
; CHECK-LABEL: vfsub_vf_nxv2f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25
+; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
@@ -464,9 +464,9 @@ define <vscale x 4 x float> @vfsub_vf_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-LABEL: vfsub_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -478,9 +478,9 @@ define <vscale x 4 x float> @vfsub_vf_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-LABEL: vfsub_vf_nxv4f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26
+; CHECK-NEXT: vfsub.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
@@ -518,9 +518,9 @@ define <vscale x 8 x float> @vfsub_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-LABEL: vfsub_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -532,9 +532,9 @@ define <vscale x 8 x float> @vfsub_vf_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-LABEL: vfsub_vf_nxv8f32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28
+; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
@@ -626,9 +626,9 @@ define <vscale x 1 x double> @vfsub_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK-LABEL: vfsub_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -640,9 +640,9 @@ define <vscale x 1 x double> @vfsub_vf_nxv1f64_unmasked(<vscale x 1 x double> %v
; CHECK-LABEL: vfsub_vf_nxv1f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v25
+; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
@@ -680,9 +680,9 @@ define <vscale x 2 x double> @vfsub_vf_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-LABEL: vfsub_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -694,9 +694,9 @@ define <vscale x 2 x double> @vfsub_vf_nxv2f64_unmasked(<vscale x 2 x double> %v
; CHECK-LABEL: vfsub_vf_nxv2f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfmv.v.f v26, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v26
+; CHECK-NEXT: vfsub.vv v8, v8, v10
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
@@ -734,9 +734,9 @@ define <vscale x 4 x double> @vfsub_vf_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-LABEL: vfsub_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t
+; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
@@ -748,9 +748,9 @@ define <vscale x 4 x double> @vfsub_vf_nxv4f64_unmasked(<vscale x 4 x double> %v
; CHECK-LABEL: vfsub_vf_nxv4f64_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfmv.v.f v28, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vfsub.vv v8, v8, v28
+; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
index bddbfb8f99c06..148959bd0c6d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16(
@@ -56,8 +56,8 @@ define <vscale x 2 x float> @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16(
@@ -102,8 +102,8 @@ define <vscale x 4 x float> @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16(
@@ -148,8 +148,8 @@ define <vscale x 8 x float> @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16(
@@ -240,8 +240,8 @@ define <vscale x 1 x double> @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32(<vscal
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32(
@@ -286,8 +286,8 @@ define <vscale x 2 x double> @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32(<vscal
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32(
@@ -332,8 +332,8 @@ define <vscale x 4 x double> @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32(<vscal
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32(
@@ -425,8 +425,8 @@ define <vscale x 1 x float> @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfwadd.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16(
@@ -473,8 +473,8 @@ define <vscale x 2 x float> @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16(
@@ -521,8 +521,8 @@ define <vscale x 4 x float> @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfwadd.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16(
@@ -569,8 +569,8 @@ define <vscale x 8 x float> @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfwadd.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16(
@@ -665,8 +665,8 @@ define <vscale x 1 x double> @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32(
@@ -713,8 +713,8 @@ define <vscale x 2 x double> @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfwadd.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32(
@@ -761,8 +761,8 @@ define <vscale x 4 x double> @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfwadd.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
index b810e11ac2572..d3d79942db091 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16(
@@ -56,8 +56,8 @@ define <vscale x 2 x float> @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16(
@@ -102,8 +102,8 @@ define <vscale x 4 x float> @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16(
@@ -148,8 +148,8 @@ define <vscale x 8 x float> @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16(<vscale
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16(
@@ -240,8 +240,8 @@ define <vscale x 1 x double> @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32(<vscal
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32(
@@ -286,8 +286,8 @@ define <vscale x 2 x double> @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32(<vscal
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32(
@@ -332,8 +332,8 @@ define <vscale x 4 x double> @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32(<vscal
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32(
@@ -425,8 +425,8 @@ define <vscale x 1 x float> @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfwadd.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16(
@@ -473,8 +473,8 @@ define <vscale x 2 x float> @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16(
@@ -521,8 +521,8 @@ define <vscale x 4 x float> @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfwadd.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16(
@@ -569,8 +569,8 @@ define <vscale x 8 x float> @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfwadd.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16(
@@ -665,8 +665,8 @@ define <vscale x 1 x double> @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfwadd.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32(
@@ -713,8 +713,8 @@ define <vscale x 2 x double> @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfwadd.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32(
@@ -761,8 +761,8 @@ define <vscale x 4 x double> @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfwadd.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
index be5b58847d223..ef02214f79221 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
@@ -212,9 +212,9 @@ declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
@@ -393,9 +393,9 @@ declare <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
@@ -1150,8 +1150,8 @@ define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16(
@@ -1166,8 +1166,8 @@ define <vscale x 2 x float> @intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16(
@@ -1182,8 +1182,8 @@ define <vscale x 4 x float> @intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16(
@@ -1198,8 +1198,8 @@ define <vscale x 8 x float> @intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16(
@@ -1214,8 +1214,8 @@ define <vscale x 1 x double> @intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f3
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32(
@@ -1230,8 +1230,8 @@ define <vscale x 2 x double> @intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f3
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32(
@@ -1246,8 +1246,8 @@ define <vscale x 4 x double> @intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f3
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
index df929cf7c5089..439989e68e270 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
@@ -212,9 +212,9 @@ declare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
@@ -393,9 +393,9 @@ declare <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
@@ -1150,8 +1150,8 @@ define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16(
@@ -1166,8 +1166,8 @@ define <vscale x 2 x float> @intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16(
@@ -1182,8 +1182,8 @@ define <vscale x 4 x float> @intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16(
@@ -1198,8 +1198,8 @@ define <vscale x 8 x float> @intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16(
@@ -1214,8 +1214,8 @@ define <vscale x 1 x double> @intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f3
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32(
@@ -1230,8 +1230,8 @@ define <vscale x 2 x double> @intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f3
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32(
@@ -1246,8 +1246,8 @@ define <vscale x 4 x double> @intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f3
; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
index e585b8e2fe6ba..813e352dea626 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x float> @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x float> @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x float> @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16(<vscale x 8
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x double> @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x double> @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x double> @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
index ce99c3a173f01..48e052c1e1d39 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x float> @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x float> @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x float> @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16(<vscale x 8
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x double> @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x double> @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x double> @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
index 6d54fbfd2b324..9617152391059 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8(
@@ -261,8 +261,8 @@ define <vscale x 1 x float> @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16(
@@ -303,8 +303,8 @@ define <vscale x 2 x float> @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16(
@@ -345,8 +345,8 @@ define <vscale x 4 x float> @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16(
@@ -387,8 +387,8 @@ define <vscale x 8 x float> @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16(<vscale x 8
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16(
@@ -471,8 +471,8 @@ define <vscale x 1 x double> @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32(
@@ -513,8 +513,8 @@ define <vscale x 2 x double> @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32(
@@ -555,8 +555,8 @@ define <vscale x 4 x double> @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
index f9a8c8ae920fe..e1279189e2228 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8(
@@ -261,8 +261,8 @@ define <vscale x 1 x float> @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16(
@@ -303,8 +303,8 @@ define <vscale x 2 x float> @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16(
@@ -345,8 +345,8 @@ define <vscale x 4 x float> @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16(
@@ -387,8 +387,8 @@ define <vscale x 8 x float> @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16(<vscale x 8
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16(
@@ -471,8 +471,8 @@ define <vscale x 1 x double> @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32(
@@ -513,8 +513,8 @@ define <vscale x 2 x double> @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32(
@@ -555,8 +555,8 @@ define <vscale x 4 x double> @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
index bd6271bec8612..9147750fcc50a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8(
@@ -261,8 +261,8 @@ define <vscale x 1 x float> @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16(
@@ -303,8 +303,8 @@ define <vscale x 2 x float> @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16(
@@ -345,8 +345,8 @@ define <vscale x 4 x float> @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16(
@@ -387,8 +387,8 @@ define <vscale x 8 x float> @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16(<vscale x 8
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16(
@@ -471,8 +471,8 @@ define <vscale x 1 x double> @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32(
@@ -513,8 +513,8 @@ define <vscale x 2 x double> @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32(
@@ -555,8 +555,8 @@ define <vscale x 4 x double> @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
index 88eee09e88790..e0a3ff909ef79 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x half> @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x half> @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x half> @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8(
@@ -135,8 +135,8 @@ define <vscale x 8 x half> @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8(
@@ -177,8 +177,8 @@ define <vscale x 16 x half> @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8(
@@ -261,8 +261,8 @@ define <vscale x 1 x float> @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16(<vscale x 1
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16(
@@ -303,8 +303,8 @@ define <vscale x 2 x float> @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16(<vscale x 2
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16(
@@ -345,8 +345,8 @@ define <vscale x 4 x float> @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16(<vscale x 4
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16(
@@ -387,8 +387,8 @@ define <vscale x 8 x float> @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16(<vscale x 8
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16(
@@ -471,8 +471,8 @@ define <vscale x 1 x double> @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32(
@@ -513,8 +513,8 @@ define <vscale x 2 x double> @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32(
@@ -555,8 +555,8 @@ define <vscale x 4 x double> @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
index 79ecafc642bea..7dfd8968633e8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
index f7faf81d1b941..30b8a19463e77 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
index c7d2f2d3c4dba..6b0e27d477e93 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
index 000faf2356380..6cef7abd1404b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
index 7cdf8afcec975..9e1f9c0ed8ea4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
index 046db374ec12b..b25556da757df 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.x.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.x.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
index d655219faa436..69169adb5135c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll
index b930e85cd04eb..69b5d60e3183d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i32> @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16(
@@ -51,8 +51,8 @@ define <vscale x 2 x i32> @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16(
@@ -93,8 +93,8 @@ define <vscale x 4 x i32> @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16(
@@ -135,8 +135,8 @@ define <vscale x 8 x i32> @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16(
@@ -219,8 +219,8 @@ define <vscale x 1 x i64> @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32(
@@ -261,8 +261,8 @@ define <vscale x 2 x i64> @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32(
@@ -303,8 +303,8 @@ define <vscale x 4 x i64> @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.xu.f.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.xu.f.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
index 75bce7633dea7..cc496b80a4620 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x float> @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16(
@@ -56,8 +56,8 @@ define <vscale x 2 x float> @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16(
@@ -102,8 +102,8 @@ define <vscale x 4 x float> @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16(
@@ -148,8 +148,8 @@ define <vscale x 8 x float> @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16(
@@ -240,8 +240,8 @@ define <vscale x 1 x double> @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32(<vscal
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32(
@@ -286,8 +286,8 @@ define <vscale x 2 x double> @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32(<vscal
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32(
@@ -332,8 +332,8 @@ define <vscale x 4 x double> @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32(<vscal
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32(
@@ -425,8 +425,8 @@ define <vscale x 1 x float> @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfwmul.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16(
@@ -473,8 +473,8 @@ define <vscale x 2 x float> @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16(
@@ -521,8 +521,8 @@ define <vscale x 4 x float> @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfwmul.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16(
@@ -569,8 +569,8 @@ define <vscale x 8 x float> @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfwmul.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16(
@@ -665,8 +665,8 @@ define <vscale x 1 x double> @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32(
@@ -713,8 +713,8 @@ define <vscale x 2 x double> @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfwmul.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32(
@@ -761,8 +761,8 @@ define <vscale x 4 x double> @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfwmul.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
index d7a3c0b7873a7..301b6174f6677 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x float> @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16(
@@ -56,8 +56,8 @@ define <vscale x 2 x float> @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16(
@@ -102,8 +102,8 @@ define <vscale x 4 x float> @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16(
@@ -148,8 +148,8 @@ define <vscale x 8 x float> @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16(<vscale
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16(
@@ -240,8 +240,8 @@ define <vscale x 1 x double> @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32(<vscal
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32(
@@ -286,8 +286,8 @@ define <vscale x 2 x double> @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32(<vscal
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32(
@@ -332,8 +332,8 @@ define <vscale x 4 x double> @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32(<vscal
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32(
@@ -425,8 +425,8 @@ define <vscale x 1 x float> @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfwmul.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16(
@@ -473,8 +473,8 @@ define <vscale x 2 x float> @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16(
@@ -521,8 +521,8 @@ define <vscale x 4 x float> @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfwmul.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16(
@@ -569,8 +569,8 @@ define <vscale x 8 x float> @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfwmul.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16(
@@ -665,8 +665,8 @@ define <vscale x 1 x double> @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfwmul.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwmul.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32(
@@ -713,8 +713,8 @@ define <vscale x 2 x double> @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfwmul.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwmul.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32(
@@ -761,8 +761,8 @@ define <vscale x 4 x double> @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfwmul.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwmul.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
index 73eafee0fbd43..a1850c0083235 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16(
@@ -56,8 +56,8 @@ define <vscale x 2 x float> @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16(
@@ -102,8 +102,8 @@ define <vscale x 4 x float> @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16(
@@ -148,8 +148,8 @@ define <vscale x 8 x float> @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16(
@@ -240,8 +240,8 @@ define <vscale x 1 x double> @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32(<vscal
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32(
@@ -286,8 +286,8 @@ define <vscale x 2 x double> @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32(<vscal
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32(
@@ -332,8 +332,8 @@ define <vscale x 4 x double> @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32(<vscal
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32(
@@ -425,8 +425,8 @@ define <vscale x 1 x float> @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfwsub.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16(
@@ -473,8 +473,8 @@ define <vscale x 2 x float> @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16(
@@ -521,8 +521,8 @@ define <vscale x 4 x float> @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfwsub.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16(
@@ -569,8 +569,8 @@ define <vscale x 8 x float> @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfwsub.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16(
@@ -665,8 +665,8 @@ define <vscale x 1 x double> @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32(
@@ -713,8 +713,8 @@ define <vscale x 2 x double> @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfwsub.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32(
@@ -761,8 +761,8 @@ define <vscale x 4 x double> @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfwsub.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
index 80a2edda326aa..7659757f732f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16(
@@ -56,8 +56,8 @@ define <vscale x 2 x float> @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16(
@@ -102,8 +102,8 @@ define <vscale x 4 x float> @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16(
@@ -148,8 +148,8 @@ define <vscale x 8 x float> @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16(<vscale
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16(
@@ -240,8 +240,8 @@ define <vscale x 1 x double> @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32(<vscal
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32(
@@ -286,8 +286,8 @@ define <vscale x 2 x double> @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32(<vscal
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32(
@@ -332,8 +332,8 @@ define <vscale x 4 x double> @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32(<vscal
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32(
@@ -425,8 +425,8 @@ define <vscale x 1 x float> @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vfwsub.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16(
@@ -473,8 +473,8 @@ define <vscale x 2 x float> @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16(
@@ -521,8 +521,8 @@ define <vscale x 4 x float> @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vfwsub.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16(
@@ -569,8 +569,8 @@ define <vscale x 8 x float> @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vfwsub.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16(
@@ -665,8 +665,8 @@ define <vscale x 1 x double> @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vfwsub.vf v25, v8, ft0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.vf v9, v8, ft0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32(
@@ -713,8 +713,8 @@ define <vscale x 2 x double> @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vfwsub.vf v26, v8, ft0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.vf v10, v8, ft0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32(
@@ -761,8 +761,8 @@ define <vscale x 4 x double> @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vfwsub.vf v28, v8, ft0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.vf v12, v8, ft0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
index ab5f16b13f763..d645f5729f367 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
@@ -212,9 +212,9 @@ declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
@@ -393,9 +393,9 @@ declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
@@ -1150,8 +1150,8 @@ define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(
@@ -1166,8 +1166,8 @@ define <vscale x 2 x float> @intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16(
@@ -1182,8 +1182,8 @@ define <vscale x 4 x float> @intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16(
@@ -1198,8 +1198,8 @@ define <vscale x 8 x float> @intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16(
@@ -1214,8 +1214,8 @@ define <vscale x 1 x double> @intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f3
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32(
@@ -1230,8 +1230,8 @@ define <vscale x 2 x double> @intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f3
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32(
@@ -1246,8 +1246,8 @@ define <vscale x 4 x double> @intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f3
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
index 901330cf51922..e9b4e577cea33 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
@@ -212,9 +212,9 @@ declare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
@@ -393,9 +393,9 @@ declare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
@@ -1150,8 +1150,8 @@ define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vfwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(
@@ -1166,8 +1166,8 @@ define <vscale x 2 x float> @intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vfwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16(
@@ -1182,8 +1182,8 @@ define <vscale x 4 x float> @intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vfwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16(
@@ -1198,8 +1198,8 @@ define <vscale x 8 x float> @intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vfwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16(
@@ -1214,8 +1214,8 @@ define <vscale x 1 x double> @intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f3
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32(
@@ -1230,8 +1230,8 @@ define <vscale x 2 x double> @intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f3
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vfwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32(
@@ -1246,8 +1246,8 @@ define <vscale x 4 x double> @intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f3
; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vfwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
index 0163c71071587..19dfb3532a3d8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
@@ -8,9 +8,9 @@ define <vscale x 1 x half> @vsitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv1i1_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -20,9 +20,9 @@ define <vscale x 1 x half> @vuitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv1i1_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -32,9 +32,9 @@ define <vscale x 1 x float> @vsitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv1i1_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -44,9 +44,9 @@ define <vscale x 1 x float> @vuitofp_nxv1i1_nxv1f32(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv1i1_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -56,9 +56,9 @@ define <vscale x 1 x double> @vsitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv1i1_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -68,9 +68,9 @@ define <vscale x 1 x double> @vuitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv1i1_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -80,9 +80,9 @@ define <vscale x 2 x half> @vsitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv2i1_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -92,9 +92,9 @@ define <vscale x 2 x half> @vuitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv2i1_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -104,9 +104,9 @@ define <vscale x 2 x float> @vsitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv2i1_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -116,9 +116,9 @@ define <vscale x 2 x float> @vuitofp_nxv2i1_nxv2f32(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv2i1_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -128,9 +128,9 @@ define <vscale x 2 x double> @vsitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv2i1_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v26
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -140,9 +140,9 @@ define <vscale x 2 x double> @vuitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv2i1_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v26
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -152,9 +152,9 @@ define <vscale x 4 x half> @vsitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv4i1_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -164,9 +164,9 @@ define <vscale x 4 x half> @vuitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv4i1_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -176,9 +176,9 @@ define <vscale x 4 x float> @vsitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv4i1_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v26
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -188,9 +188,9 @@ define <vscale x 4 x float> @vuitofp_nxv4i1_nxv4f32(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv4i1_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v26
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -200,9 +200,9 @@ define <vscale x 4 x double> @vsitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv4i1_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v28
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -212,9 +212,9 @@ define <vscale x 4 x double> @vuitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv4i1_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v28
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -224,9 +224,9 @@ define <vscale x 8 x half> @vsitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv8i1_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v26
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -236,9 +236,9 @@ define <vscale x 8 x half> @vuitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv8i1_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v26
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -248,9 +248,9 @@ define <vscale x 8 x float> @vsitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv8i1_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v28
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -260,9 +260,9 @@ define <vscale x 8 x float> @vuitofp_nxv8i1_nxv8f32(<vscale x 8 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv8i1_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v28
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -296,9 +296,9 @@ define <vscale x 16 x half> @vsitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
; CHECK-LABEL: vsitofp_nxv16i1_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, -1, v0
-; CHECK-NEXT: vfcvt.f.x.v v8, v28
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret
%evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -308,9 +308,9 @@ define <vscale x 16 x half> @vuitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
; CHECK-LABEL: vuitofp_nxv16i1_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmerge.vim v28, v28, 1, v0
-; CHECK-NEXT: vfcvt.f.xu.v v8, v28
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret
%evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -368,8 +368,8 @@ define <vscale x 1 x half> @vsitofp_nxv1i8_nxv1f16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv1i8_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i8> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -379,8 +379,8 @@ define <vscale x 1 x half> @vuitofp_nxv1i8_nxv1f16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv1i8_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i8> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -390,8 +390,8 @@ define <vscale x 1 x float> @vsitofp_nxv1i8_nxv1f32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv1i8_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i8> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -401,8 +401,8 @@ define <vscale x 1 x float> @vuitofp_nxv1i8_nxv1f32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv1i8_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i8> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -412,8 +412,8 @@ define <vscale x 1 x double> @vsitofp_nxv1i8_nxv1f64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv1i8_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf8 v25, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vsext.vf8 v9, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i8> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -423,8 +423,8 @@ define <vscale x 1 x double> @vuitofp_nxv1i8_nxv1f64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv1i8_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf8 v25, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vzext.vf8 v9, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i8> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -434,8 +434,8 @@ define <vscale x 2 x half> @vsitofp_nxv2i8_nxv2f16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv2i8_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i8> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -445,8 +445,8 @@ define <vscale x 2 x half> @vuitofp_nxv2i8_nxv2f16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv2i8_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i8> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -456,8 +456,8 @@ define <vscale x 2 x float> @vsitofp_nxv2i8_nxv2f32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv2i8_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i8> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -467,8 +467,8 @@ define <vscale x 2 x float> @vuitofp_nxv2i8_nxv2f32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv2i8_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i8> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -478,8 +478,8 @@ define <vscale x 2 x double> @vsitofp_nxv2i8_nxv2f64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv2i8_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf8 v26, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v26
+; CHECK-NEXT: vsext.vf8 v10, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i8> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -489,8 +489,8 @@ define <vscale x 2 x double> @vuitofp_nxv2i8_nxv2f64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv2i8_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf8 v26, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v26
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i8> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -500,8 +500,8 @@ define <vscale x 4 x half> @vsitofp_nxv4i8_nxv4f16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv4i8_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i8> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -511,8 +511,8 @@ define <vscale x 4 x half> @vuitofp_nxv4i8_nxv4f16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv4i8_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i8> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -522,8 +522,8 @@ define <vscale x 4 x float> @vsitofp_nxv4i8_nxv4f32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv4i8_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i8> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -533,8 +533,8 @@ define <vscale x 4 x float> @vuitofp_nxv4i8_nxv4f32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv4i8_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i8> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -544,8 +544,8 @@ define <vscale x 4 x double> @vsitofp_nxv4i8_nxv4f64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv4i8_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v28
+; CHECK-NEXT: vsext.vf8 v12, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i8> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -555,8 +555,8 @@ define <vscale x 4 x double> @vuitofp_nxv4i8_nxv4f64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv4i8_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v28
+; CHECK-NEXT: vzext.vf8 v12, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i8> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -566,8 +566,8 @@ define <vscale x 8 x half> @vsitofp_nxv8i8_nxv8f16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv8i8_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i8> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -577,8 +577,8 @@ define <vscale x 8 x half> @vuitofp_nxv8i8_nxv8f16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv8i8_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i8> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -588,8 +588,8 @@ define <vscale x 8 x float> @vsitofp_nxv8i8_nxv8f32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv8i8_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i8> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -599,8 +599,8 @@ define <vscale x 8 x float> @vuitofp_nxv8i8_nxv8f32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv8i8_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i8> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -632,8 +632,8 @@ define <vscale x 16 x half> @vsitofp_nxv16i8_nxv16f16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsitofp_nxv16i8_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 16 x i8> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -643,8 +643,8 @@ define <vscale x 16 x half> @vuitofp_nxv16i8_nxv16f16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vuitofp_nxv16i8_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 16 x i8> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -718,8 +718,8 @@ define <vscale x 1 x float> @vsitofp_nxv1i16_nxv1f32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsitofp_nxv1i16_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i16> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -729,8 +729,8 @@ define <vscale x 1 x float> @vuitofp_nxv1i16_nxv1f32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vuitofp_nxv1i16_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i16> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -740,8 +740,8 @@ define <vscale x 1 x double> @vsitofp_nxv1i16_nxv1f64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsitofp_nxv1i16_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i16> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -751,8 +751,8 @@ define <vscale x 1 x double> @vuitofp_nxv1i16_nxv1f64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vuitofp_nxv1i16_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i16> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -782,8 +782,8 @@ define <vscale x 2 x float> @vsitofp_nxv2i16_nxv2f32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsitofp_nxv2i16_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i16> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -793,8 +793,8 @@ define <vscale x 2 x float> @vuitofp_nxv2i16_nxv2f32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vuitofp_nxv2i16_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i16> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -804,8 +804,8 @@ define <vscale x 2 x double> @vsitofp_nxv2i16_nxv2f64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsitofp_nxv2i16_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i16> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -815,8 +815,8 @@ define <vscale x 2 x double> @vuitofp_nxv2i16_nxv2f64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vuitofp_nxv2i16_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i16> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -846,8 +846,8 @@ define <vscale x 4 x float> @vsitofp_nxv4i16_nxv4f32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsitofp_nxv4i16_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i16> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -857,8 +857,8 @@ define <vscale x 4 x float> @vuitofp_nxv4i16_nxv4f32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vuitofp_nxv4i16_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i16> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -868,8 +868,8 @@ define <vscale x 4 x double> @vsitofp_nxv4i16_nxv4f64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsitofp_nxv4i16_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vfcvt.f.x.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vfcvt.f.x.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i16> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -879,8 +879,8 @@ define <vscale x 4 x double> @vuitofp_nxv4i16_nxv4f64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vuitofp_nxv4i16_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vfcvt.f.xu.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vfcvt.f.xu.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i16> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -910,8 +910,8 @@ define <vscale x 8 x float> @vsitofp_nxv8i16_nxv8f32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsitofp_nxv8i16_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i16> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -921,8 +921,8 @@ define <vscale x 8 x float> @vuitofp_nxv8i16_nxv8f32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vuitofp_nxv8i16_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i16> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -1016,8 +1016,8 @@ define <vscale x 1 x half> @vsitofp_nxv1i32_nxv1f16(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vsitofp_nxv1i32_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i32> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -1027,8 +1027,8 @@ define <vscale x 1 x half> @vuitofp_nxv1i32_nxv1f16(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vuitofp_nxv1i32_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i32> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -1058,8 +1058,8 @@ define <vscale x 1 x double> @vsitofp_nxv1i32_nxv1f64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vsitofp_nxv1i32_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.x.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i32> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -1069,8 +1069,8 @@ define <vscale x 1 x double> @vuitofp_nxv1i32_nxv1f64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vuitofp_nxv1i32_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i32> %va to <vscale x 1 x double>
ret <vscale x 1 x double> %evec
@@ -1080,8 +1080,8 @@ define <vscale x 2 x half> @vsitofp_nxv2i32_nxv2f16(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vsitofp_nxv2i32_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i32> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -1091,8 +1091,8 @@ define <vscale x 2 x half> @vuitofp_nxv2i32_nxv2f16(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vuitofp_nxv2i32_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i32> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -1122,8 +1122,8 @@ define <vscale x 2 x double> @vsitofp_nxv2i32_nxv2f64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vsitofp_nxv2i32_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.x.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i32> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -1133,8 +1133,8 @@ define <vscale x 2 x double> @vuitofp_nxv2i32_nxv2f64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vuitofp_nxv2i32_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i32> %va to <vscale x 2 x double>
ret <vscale x 2 x double> %evec
@@ -1144,8 +1144,8 @@ define <vscale x 4 x half> @vsitofp_nxv4i32_nxv4f16(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vsitofp_nxv4i32_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i32> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -1155,8 +1155,8 @@ define <vscale x 4 x half> @vuitofp_nxv4i32_nxv4f16(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vuitofp_nxv4i32_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i32> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -1186,8 +1186,8 @@ define <vscale x 4 x double> @vsitofp_nxv4i32_nxv4f64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vsitofp_nxv4i32_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.x.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.x.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i32> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -1197,8 +1197,8 @@ define <vscale x 4 x double> @vuitofp_nxv4i32_nxv4f64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vuitofp_nxv4i32_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfwcvt.f.xu.v v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i32> %va to <vscale x 4 x double>
ret <vscale x 4 x double> %evec
@@ -1208,8 +1208,8 @@ define <vscale x 8 x half> @vsitofp_nxv8i32_nxv8f16(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vsitofp_nxv8i32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.x.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i32> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -1219,8 +1219,8 @@ define <vscale x 8 x half> @vuitofp_nxv8i32_nxv8f16(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vuitofp_nxv8i32_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.xu.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i32> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -1272,8 +1272,8 @@ define <vscale x 16 x half> @vsitofp_nxv16i32_nxv16f16(<vscale x 16 x i32> %va)
; CHECK-LABEL: vsitofp_nxv16i32_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.x.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = sitofp <vscale x 16 x i32> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -1283,8 +1283,8 @@ define <vscale x 16 x half> @vuitofp_nxv16i32_nxv16f16(<vscale x 16 x i32> %va)
; CHECK-LABEL: vuitofp_nxv16i32_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.xu.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = uitofp <vscale x 16 x i32> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
@@ -1314,9 +1314,9 @@ define <vscale x 1 x half> @vsitofp_nxv1i64_nxv1f16(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv1i64_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i64> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -1326,9 +1326,9 @@ define <vscale x 1 x half> @vuitofp_nxv1i64_nxv1f16(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv1i64_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i64> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
@@ -1338,8 +1338,8 @@ define <vscale x 1 x float> @vsitofp_nxv1i64_nxv1f32(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv1i64_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i64> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -1349,8 +1349,8 @@ define <vscale x 1 x float> @vuitofp_nxv1i64_nxv1f32(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv1i64_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i64> %va to <vscale x 1 x float>
ret <vscale x 1 x float> %evec
@@ -1380,9 +1380,9 @@ define <vscale x 2 x half> @vsitofp_nxv2i64_nxv2f16(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv2i64_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
+; CHECK-NEXT: vfncvt.f.x.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i64> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -1392,9 +1392,9 @@ define <vscale x 2 x half> @vuitofp_nxv2i64_nxv2f16(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv2i64_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
+; CHECK-NEXT: vfncvt.f.xu.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v25
+; CHECK-NEXT: vfncvt.f.f.w v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i64> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
@@ -1404,8 +1404,8 @@ define <vscale x 2 x float> @vsitofp_nxv2i64_nxv2f32(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv2i64_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.x.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i64> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -1415,8 +1415,8 @@ define <vscale x 2 x float> @vuitofp_nxv2i64_nxv2f32(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv2i64_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i64> %va to <vscale x 2 x float>
ret <vscale x 2 x float> %evec
@@ -1446,9 +1446,9 @@ define <vscale x 4 x half> @vsitofp_nxv4i64_nxv4f16(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv4i64_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v8
+; CHECK-NEXT: vfncvt.f.x.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i64> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -1458,9 +1458,9 @@ define <vscale x 4 x half> @vuitofp_nxv4i64_nxv4f16(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv4i64_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v8
+; CHECK-NEXT: vfncvt.f.xu.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v26
+; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i64> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
@@ -1470,8 +1470,8 @@ define <vscale x 4 x float> @vsitofp_nxv4i64_nxv4f32(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv4i64_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.x.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i64> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -1481,8 +1481,8 @@ define <vscale x 4 x float> @vuitofp_nxv4i64_nxv4f32(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv4i64_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vfncvt.f.xu.w v12, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i64> %va to <vscale x 4 x float>
ret <vscale x 4 x float> %evec
@@ -1512,9 +1512,9 @@ define <vscale x 8 x half> @vsitofp_nxv8i64_nxv8f16(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv8i64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v28, v8
+; CHECK-NEXT: vfncvt.f.x.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v8, v16
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i64> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -1524,9 +1524,9 @@ define <vscale x 8 x half> @vuitofp_nxv8i64_nxv8f16(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv8i64_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v28, v8
+; CHECK-NEXT: vfncvt.f.xu.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vfncvt.f.f.w v8, v28
+; CHECK-NEXT: vfncvt.f.f.w v8, v16
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i64> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
@@ -1536,8 +1536,8 @@ define <vscale x 8 x float> @vsitofp_nxv8i64_nxv8f32(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vsitofp_nxv8i64_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.x.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.x.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i64> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
@@ -1547,8 +1547,8 @@ define <vscale x 8 x float> @vuitofp_nxv8i64_nxv8f32(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vuitofp_nxv8i64_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vfncvt.f.xu.w v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vfncvt.f.xu.w v16, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i64> %va to <vscale x 8 x float>
ret <vscale x 8 x float> %evec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
index c041fa5806ef2..27a32d8095d00 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
@@ -1888,7 +1888,7 @@ define void @intrinsic_vleff_dead_value(<vscale x 1 x double>* %0, i32 %1, i32*
; CHECK-LABEL: intrinsic_vleff_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vle64ff.v v25, (a0)
+; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret
@@ -1926,7 +1926,7 @@ define void @intrinsic_vleff_dead_all(<vscale x 1 x double>* %0, i32 %1, i32* %2
; CHECK-LABEL: intrinsic_vleff_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vle64ff.v v25, (a0)
+; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call { <vscale x 1 x double>, i32 } @llvm.riscv.vleff.nxv1f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
index a7099b82dee01..b76cb4b8c92e0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
@@ -1888,7 +1888,7 @@ define void @intrinsic_vleff_dead_value(<vscale x 1 x double>* %0, i64 %1, i64*
; CHECK-LABEL: intrinsic_vleff_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vle64ff.v v25, (a0)
+; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret
@@ -1926,7 +1926,7 @@ define void @intrinsic_vleff_dead_all(<vscale x 1 x double>* %0, i64 %1) nounwin
; CHECK-LABEL: intrinsic_vleff_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vle64ff.v v25, (a0)
+; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
index 2a49fc1f09325..3ac1d59e7b8a2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64(
@@ -194,8 +194,8 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
@@ -240,8 +240,8 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64(
@@ -286,8 +286,8 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64(
@@ -332,8 +332,8 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64(
@@ -378,8 +378,8 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
@@ -424,8 +424,8 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64(
@@ -470,8 +470,8 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
@@ -516,8 +516,8 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64(
@@ -742,8 +742,8 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
@@ -788,8 +788,8 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64(
@@ -834,8 +834,8 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64(
@@ -880,8 +880,8 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64(
@@ -926,8 +926,8 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
@@ -972,8 +972,8 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64(
@@ -1018,8 +1018,8 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64(
@@ -1064,8 +1064,8 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64(
@@ -1290,8 +1290,8 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
@@ -1336,8 +1336,8 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
@@ -1382,8 +1382,8 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
@@ -1428,8 +1428,8 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
@@ -1474,8 +1474,8 @@ define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
@@ -1520,8 +1520,8 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
@@ -1566,8 +1566,8 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
@@ -1612,8 +1612,8 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
@@ -1658,8 +1658,8 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
@@ -1704,8 +1704,8 @@ define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscal
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
@@ -1975,8 +1975,8 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
@@ -2021,8 +2021,8 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
@@ -2067,8 +2067,8 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
@@ -2159,8 +2159,8 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
@@ -2205,8 +2205,8 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
@@ -2251,8 +2251,8 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
@@ -2297,8 +2297,8 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
@@ -2343,8 +2343,8 @@ define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
@@ -2614,8 +2614,8 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
@@ -2660,8 +2660,8 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
@@ -2706,8 +2706,8 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
@@ -2798,8 +2798,8 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
@@ -2844,8 +2844,8 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
@@ -2890,8 +2890,8 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
@@ -2936,8 +2936,8 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
@@ -2982,8 +2982,8 @@ define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
@@ -3028,8 +3028,8 @@ define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
@@ -3344,8 +3344,8 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
@@ -3390,8 +3390,8 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
@@ -3436,8 +3436,8 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
@@ -3482,8 +3482,8 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
@@ -3574,8 +3574,8 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
@@ -3620,8 +3620,8 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
@@ -3666,8 +3666,8 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
@@ -4028,8 +4028,8 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
@@ -4074,8 +4074,8 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
@@ -4120,8 +4120,8 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
@@ -4166,8 +4166,8 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
@@ -4258,8 +4258,8 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
@@ -4304,8 +4304,8 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
@@ -4350,8 +4350,8 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
@@ -4757,8 +4757,8 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
@@ -4803,8 +4803,8 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
@@ -4849,8 +4849,8 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
@@ -4895,8 +4895,8 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
@@ -4941,8 +4941,8 @@ define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
@@ -5033,8 +5033,8 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
@@ -5079,8 +5079,8 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
@@ -5125,8 +5125,8 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
@@ -5171,8 +5171,8 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
@@ -5263,8 +5263,8 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
@@ -5309,8 +5309,8 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
@@ -5355,8 +5355,8 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
@@ -5447,8 +5447,8 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
@@ -5493,8 +5493,8 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
@@ -5539,8 +5539,8 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
@@ -5585,8 +5585,8 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
@@ -5631,8 +5631,8 @@ define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscal
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
@@ -5723,8 +5723,8 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
@@ -5769,8 +5769,8 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
@@ -5815,8 +5815,8 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
@@ -5861,8 +5861,8 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
@@ -5953,8 +5953,8 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
@@ -5999,8 +5999,8 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
@@ -6045,8 +6045,8 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
index fb9db003dc5e6..47e7393c3f1ca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64(
@@ -194,8 +194,8 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
@@ -240,8 +240,8 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64(
@@ -286,8 +286,8 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64(
@@ -332,8 +332,8 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64(
@@ -378,8 +378,8 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
@@ -424,8 +424,8 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64(
@@ -470,8 +470,8 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
@@ -516,8 +516,8 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64(
@@ -742,8 +742,8 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
@@ -788,8 +788,8 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64(
@@ -834,8 +834,8 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64(
@@ -880,8 +880,8 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64(
@@ -926,8 +926,8 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
@@ -972,8 +972,8 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64(
@@ -1018,8 +1018,8 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64(
@@ -1064,8 +1064,8 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64(
@@ -1290,8 +1290,8 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
@@ -1336,8 +1336,8 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
@@ -1382,8 +1382,8 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
@@ -1428,8 +1428,8 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
@@ -1474,8 +1474,8 @@ define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
@@ -1520,8 +1520,8 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
@@ -1566,8 +1566,8 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
@@ -1612,8 +1612,8 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
@@ -1658,8 +1658,8 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
@@ -1704,8 +1704,8 @@ define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscal
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
@@ -1975,8 +1975,8 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
@@ -2021,8 +2021,8 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
@@ -2067,8 +2067,8 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
@@ -2159,8 +2159,8 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
@@ -2205,8 +2205,8 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
@@ -2251,8 +2251,8 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
@@ -2297,8 +2297,8 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
@@ -2343,8 +2343,8 @@ define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vsca
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
@@ -2614,8 +2614,8 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
@@ -2660,8 +2660,8 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
@@ -2706,8 +2706,8 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
@@ -2798,8 +2798,8 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
@@ -2844,8 +2844,8 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
@@ -2890,8 +2890,8 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
@@ -2936,8 +2936,8 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
@@ -2982,8 +2982,8 @@ define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
@@ -3028,8 +3028,8 @@ define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
@@ -3344,8 +3344,8 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
@@ -3390,8 +3390,8 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
@@ -3436,8 +3436,8 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
@@ -3482,8 +3482,8 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
@@ -3574,8 +3574,8 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
@@ -3620,8 +3620,8 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
@@ -3666,8 +3666,8 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
@@ -4028,8 +4028,8 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
@@ -4074,8 +4074,8 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
@@ -4120,8 +4120,8 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
@@ -4166,8 +4166,8 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
@@ -4258,8 +4258,8 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
@@ -4304,8 +4304,8 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
@@ -4350,8 +4350,8 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
@@ -4757,8 +4757,8 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
@@ -4803,8 +4803,8 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
@@ -4849,8 +4849,8 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
@@ -4895,8 +4895,8 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
@@ -4941,8 +4941,8 @@ define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
@@ -5033,8 +5033,8 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
@@ -5079,8 +5079,8 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
@@ -5125,8 +5125,8 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
@@ -5171,8 +5171,8 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
@@ -5263,8 +5263,8 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
@@ -5309,8 +5309,8 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
@@ -5355,8 +5355,8 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
@@ -5447,8 +5447,8 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
@@ -5493,8 +5493,8 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
@@ -5539,8 +5539,8 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
@@ -5585,8 +5585,8 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
@@ -5631,8 +5631,8 @@ define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscal
; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
@@ -5723,8 +5723,8 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
@@ -5769,8 +5769,8 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
@@ -5815,8 +5815,8 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
@@ -5861,8 +5861,8 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
@@ -5953,8 +5953,8 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vloxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vloxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
@@ -5999,8 +5999,8 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vloxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vloxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
@@ -6045,8 +6045,8 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale
; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vloxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vloxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
index 5a06573d78dc5..0fb8242084ac5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64(
@@ -194,8 +194,8 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
@@ -240,8 +240,8 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64(
@@ -286,8 +286,8 @@ define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64(
@@ -332,8 +332,8 @@ define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64(
@@ -378,8 +378,8 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
@@ -424,8 +424,8 @@ define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64(
@@ -470,8 +470,8 @@ define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
@@ -516,8 +516,8 @@ define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64(
@@ -742,8 +742,8 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
@@ -788,8 +788,8 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64(
@@ -834,8 +834,8 @@ define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64(
@@ -880,8 +880,8 @@ define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64(
@@ -926,8 +926,8 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
@@ -972,8 +972,8 @@ define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64(
@@ -1018,8 +1018,8 @@ define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64(
@@ -1064,8 +1064,8 @@ define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64(
@@ -1290,8 +1290,8 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
@@ -1336,8 +1336,8 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
@@ -1382,8 +1382,8 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
@@ -1428,8 +1428,8 @@ define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
@@ -1474,8 +1474,8 @@ define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
@@ -1520,8 +1520,8 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
@@ -1566,8 +1566,8 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
@@ -1612,8 +1612,8 @@ define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
@@ -1658,8 +1658,8 @@ define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
@@ -1704,8 +1704,8 @@ define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscal
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
@@ -1975,8 +1975,8 @@ define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
@@ -2021,8 +2021,8 @@ define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
@@ -2067,8 +2067,8 @@ define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
@@ -2159,8 +2159,8 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
@@ -2205,8 +2205,8 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
@@ -2251,8 +2251,8 @@ define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
@@ -2297,8 +2297,8 @@ define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
@@ -2343,8 +2343,8 @@ define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
@@ -2614,8 +2614,8 @@ define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
@@ -2660,8 +2660,8 @@ define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
@@ -2706,8 +2706,8 @@ define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
@@ -2798,8 +2798,8 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
@@ -2844,8 +2844,8 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
@@ -2890,8 +2890,8 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
@@ -2936,8 +2936,8 @@ define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
@@ -2982,8 +2982,8 @@ define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
@@ -3028,8 +3028,8 @@ define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
@@ -3344,8 +3344,8 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
@@ -3390,8 +3390,8 @@ define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
@@ -3436,8 +3436,8 @@ define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
@@ -3482,8 +3482,8 @@ define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
@@ -3574,8 +3574,8 @@ define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
@@ -3620,8 +3620,8 @@ define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
@@ -3666,8 +3666,8 @@ define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
@@ -4028,8 +4028,8 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
@@ -4074,8 +4074,8 @@ define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
@@ -4120,8 +4120,8 @@ define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
@@ -4166,8 +4166,8 @@ define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
@@ -4258,8 +4258,8 @@ define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
@@ -4304,8 +4304,8 @@ define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
@@ -4350,8 +4350,8 @@ define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
@@ -4757,8 +4757,8 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
@@ -4803,8 +4803,8 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
@@ -4849,8 +4849,8 @@ define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
@@ -4895,8 +4895,8 @@ define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
@@ -4941,8 +4941,8 @@ define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
@@ -5033,8 +5033,8 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
@@ -5079,8 +5079,8 @@ define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
@@ -5125,8 +5125,8 @@ define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
@@ -5171,8 +5171,8 @@ define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
@@ -5263,8 +5263,8 @@ define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
@@ -5309,8 +5309,8 @@ define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
@@ -5355,8 +5355,8 @@ define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
@@ -5447,8 +5447,8 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
@@ -5493,8 +5493,8 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
@@ -5539,8 +5539,8 @@ define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
@@ -5585,8 +5585,8 @@ define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
@@ -5631,8 +5631,8 @@ define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscal
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
@@ -5723,8 +5723,8 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
@@ -5769,8 +5769,8 @@ define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
@@ -5815,8 +5815,8 @@ define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
@@ -5861,8 +5861,8 @@ define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
@@ -5953,8 +5953,8 @@ define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
@@ -5999,8 +5999,8 @@ define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
@@ -6045,8 +6045,8 @@ define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
index 0ec37535be5c8..a04272f3d1a01 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64(
@@ -194,8 +194,8 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
@@ -240,8 +240,8 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64(
@@ -286,8 +286,8 @@ define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64(
@@ -332,8 +332,8 @@ define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64(
@@ -378,8 +378,8 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
@@ -424,8 +424,8 @@ define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64(
@@ -470,8 +470,8 @@ define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
@@ -516,8 +516,8 @@ define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64(
@@ -742,8 +742,8 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
@@ -788,8 +788,8 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64(
@@ -834,8 +834,8 @@ define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64(
@@ -880,8 +880,8 @@ define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64(
@@ -926,8 +926,8 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
@@ -972,8 +972,8 @@ define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei64.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei64.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64(
@@ -1018,8 +1018,8 @@ define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei64.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei64.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64(
@@ -1064,8 +1064,8 @@ define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei64.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei64.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64(
@@ -1290,8 +1290,8 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
@@ -1336,8 +1336,8 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
@@ -1382,8 +1382,8 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
@@ -1428,8 +1428,8 @@ define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
@@ -1474,8 +1474,8 @@ define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
@@ -1520,8 +1520,8 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
@@ -1566,8 +1566,8 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
@@ -1612,8 +1612,8 @@ define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
@@ -1658,8 +1658,8 @@ define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
@@ -1704,8 +1704,8 @@ define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscal
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
@@ -1975,8 +1975,8 @@ define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
@@ -2021,8 +2021,8 @@ define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
@@ -2067,8 +2067,8 @@ define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
@@ -2159,8 +2159,8 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
@@ -2205,8 +2205,8 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
@@ -2251,8 +2251,8 @@ define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
@@ -2297,8 +2297,8 @@ define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
@@ -2343,8 +2343,8 @@ define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vsca
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
@@ -2614,8 +2614,8 @@ define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei32.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei32.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
@@ -2660,8 +2660,8 @@ define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei32.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei32.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
@@ -2706,8 +2706,8 @@ define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei32.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei32.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
@@ -2798,8 +2798,8 @@ define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
@@ -2844,8 +2844,8 @@ define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
@@ -2890,8 +2890,8 @@ define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
@@ -2936,8 +2936,8 @@ define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
@@ -2982,8 +2982,8 @@ define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
@@ -3028,8 +3028,8 @@ define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v16, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
@@ -3344,8 +3344,8 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
@@ -3390,8 +3390,8 @@ define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
@@ -3436,8 +3436,8 @@ define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
@@ -3482,8 +3482,8 @@ define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
@@ -3574,8 +3574,8 @@ define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
@@ -3620,8 +3620,8 @@ define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
@@ -3666,8 +3666,8 @@ define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
@@ -4028,8 +4028,8 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
@@ -4074,8 +4074,8 @@ define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
@@ -4120,8 +4120,8 @@ define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
@@ -4166,8 +4166,8 @@ define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
@@ -4258,8 +4258,8 @@ define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei16.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei16.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
@@ -4304,8 +4304,8 @@ define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei16.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei16.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
@@ -4350,8 +4350,8 @@ define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei16.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
@@ -4757,8 +4757,8 @@ define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
@@ -4803,8 +4803,8 @@ define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
@@ -4849,8 +4849,8 @@ define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
@@ -4895,8 +4895,8 @@ define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
@@ -4941,8 +4941,8 @@ define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
@@ -5033,8 +5033,8 @@ define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
@@ -5079,8 +5079,8 @@ define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
@@ -5125,8 +5125,8 @@ define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
@@ -5171,8 +5171,8 @@ define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
@@ -5263,8 +5263,8 @@ define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
@@ -5309,8 +5309,8 @@ define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
@@ -5355,8 +5355,8 @@ define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
@@ -5447,8 +5447,8 @@ define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
@@ -5493,8 +5493,8 @@ define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
@@ -5539,8 +5539,8 @@ define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
@@ -5585,8 +5585,8 @@ define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
@@ -5631,8 +5631,8 @@ define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscal
; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
@@ -5723,8 +5723,8 @@ define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
@@ -5769,8 +5769,8 @@ define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
@@ -5815,8 +5815,8 @@ define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
@@ -5861,8 +5861,8 @@ define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
@@ -5953,8 +5953,8 @@ define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vluxei8.v v25, (a0), v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vluxei8.v v9, (a0), v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
@@ -5999,8 +5999,8 @@ define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vluxei8.v v26, (a0), v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vluxei8.v v10, (a0), v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
@@ -6045,8 +6045,8 @@ define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale
; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vluxei8.v v28, (a0), v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vluxei8.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
index dc70f83d8a536..0ecbc734de624 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
@@ -1533,9 +1533,9 @@ define <vscale x 1 x i64> @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vmacc.vv v8, v25, v9
+; CHECK-NEXT: vmacc.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1563,9 +1563,9 @@ define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vmacc.vv v8, v25, v9, v0.t
+; CHECK-NEXT: vmacc.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1593,9 +1593,9 @@ define <vscale x 2 x i64> @intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vmacc.vv v8, v26, v10
+; CHECK-NEXT: vmacc.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1623,9 +1623,9 @@ define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vmacc.vv v8, v26, v10, v0.t
+; CHECK-NEXT: vmacc.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1653,9 +1653,9 @@ define <vscale x 4 x i64> @intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vmacc.vv v8, v28, v12
+; CHECK-NEXT: vmacc.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,9 +1683,9 @@ define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vmacc.vv v8, v28, v12, v0.t
+; CHECK-NEXT: vmacc.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
index 0bb2d5709b558..b9d8ac8e3841c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
@@ -814,8 +814,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64(<vscale x 1 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmadc.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmadc.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -840,8 +840,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64(<vscale x 2 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmadc.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmadc.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -866,8 +866,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64(<vscale x 4 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmadc.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmadc.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
index ef4b984e679db..7a3edab3a2630 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
@@ -11,8 +11,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8(
@@ -34,8 +34,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8(
@@ -57,8 +57,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8(
@@ -80,8 +80,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8(
@@ -103,8 +103,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8(
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8(
@@ -126,8 +126,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8(
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8(
@@ -149,8 +149,8 @@ define <vscale x 64 x i1> @intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8(
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8(
@@ -172,8 +172,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16(
@@ -195,8 +195,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16(
@@ -218,8 +218,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16(
@@ -241,8 +241,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16(
@@ -264,8 +264,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i1
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16(
@@ -287,8 +287,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i1
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16(
@@ -310,8 +310,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32(
@@ -333,8 +333,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32(
@@ -356,8 +356,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32(
@@ -379,8 +379,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32(
@@ -402,8 +402,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i3
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32(
@@ -425,8 +425,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.nxv1i64(
@@ -448,8 +448,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.nxv2i64(
@@ -471,8 +471,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.nxv4i64(
@@ -494,8 +494,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.nxv8i64(
@@ -517,8 +517,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8(
@@ -540,8 +540,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8(
@@ -563,8 +563,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.i8(
@@ -586,8 +586,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.i8(
@@ -609,8 +609,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.i8(
@@ -632,8 +632,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.i8(
@@ -655,8 +655,8 @@ define <vscale x 64 x i1> @intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.i8(
@@ -678,8 +678,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.i16(
@@ -701,8 +701,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.i16(
@@ -724,8 +724,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.i16(
@@ -747,8 +747,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.i16(
@@ -770,8 +770,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.i16(
@@ -793,8 +793,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.i16(
@@ -816,8 +816,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.i32(
@@ -839,8 +839,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.i32(
@@ -862,8 +862,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32(
@@ -885,8 +885,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.i32(
@@ -908,8 +908,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.i32(
@@ -935,9 +935,9 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64(<vscal
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmadc.vvm v25, v8, v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmadc.vvm v9, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -964,9 +964,9 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64(<vscal
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmadc.vvm v25, v8, v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmadc.vvm v10, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -993,9 +993,9 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64(<vscal
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmadc.vvm v25, v8, v28, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmadc.vvm v12, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1022,9 +1022,9 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64(<vscal
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v24, (a0), zero
+; CHECK-NEXT: vmadc.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1041,8 +1041,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8(
@@ -1058,8 +1058,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8(
@@ -1075,8 +1075,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.i8(
@@ -1092,8 +1092,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.i8(
@@ -1109,8 +1109,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.i8(
@@ -1126,8 +1126,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.i8(
@@ -1143,8 +1143,8 @@ define <vscale x 64 x i1> @intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.i8(
@@ -1160,8 +1160,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.i16(
@@ -1177,8 +1177,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.i16(
@@ -1194,8 +1194,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.i16(
@@ -1211,8 +1211,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.i16(
@@ -1228,8 +1228,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.i16(
@@ -1245,8 +1245,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.i16(
@@ -1262,8 +1262,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.i32(
@@ -1279,8 +1279,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.i32(
@@ -1296,8 +1296,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32(
@@ -1313,8 +1313,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.i32(
@@ -1330,8 +1330,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.i32(
@@ -1347,8 +1347,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64(
@@ -1364,8 +1364,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64(
@@ -1381,8 +1381,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64(
@@ -1398,8 +1398,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
index b1aa8103c950f..a29588d107d93 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
@@ -11,8 +11,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8(
@@ -34,8 +34,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8(
@@ -57,8 +57,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8(
@@ -80,8 +80,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8(<vsc
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8(
@@ -103,8 +103,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8(
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8(
@@ -126,8 +126,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8(
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8(
@@ -149,8 +149,8 @@ define <vscale x 64 x i1> @intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8(
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8(
@@ -172,8 +172,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16(
@@ -195,8 +195,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16(
@@ -218,8 +218,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16(
@@ -241,8 +241,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16(
@@ -264,8 +264,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i1
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16(
@@ -287,8 +287,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i1
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16(
@@ -310,8 +310,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32(
@@ -333,8 +333,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32(
@@ -356,8 +356,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32(
@@ -379,8 +379,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32(
@@ -402,8 +402,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i3
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32(
@@ -425,8 +425,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.nxv1i64(
@@ -448,8 +448,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.nxv2i64(
@@ -471,8 +471,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.nxv4i64(
@@ -494,8 +494,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64(<v
; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.nxv8i64(
@@ -517,8 +517,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8(
@@ -540,8 +540,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8(
@@ -563,8 +563,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.i8(
@@ -586,8 +586,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.i8(
@@ -609,8 +609,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.i8(
@@ -632,8 +632,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.i8(
@@ -655,8 +655,8 @@ define <vscale x 64 x i1> @intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.i8(
@@ -678,8 +678,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.i16(
@@ -701,8 +701,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.i16(
@@ -724,8 +724,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.i16(
@@ -747,8 +747,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.i16(
@@ -770,8 +770,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.i16(
@@ -793,8 +793,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.i16(
@@ -816,8 +816,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.i32(
@@ -839,8 +839,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.i32(
@@ -862,8 +862,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32(
@@ -885,8 +885,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.i32(
@@ -908,8 +908,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.i32(
@@ -931,8 +931,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64(
@@ -954,8 +954,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64(
@@ -977,8 +977,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64(
@@ -1000,8 +1000,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64(
@@ -1017,8 +1017,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8(
@@ -1034,8 +1034,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8(
@@ -1051,8 +1051,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.i8(
@@ -1068,8 +1068,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i8.i8(
@@ -1085,8 +1085,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i8.i8(
@@ -1102,8 +1102,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i8.i8(
@@ -1119,8 +1119,8 @@ define <vscale x 64 x i1> @intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8(<vsca
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmadc.carry.in.nxv64i8.i8(
@@ -1136,8 +1136,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i16.i16(
@@ -1153,8 +1153,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i16.i16(
@@ -1170,8 +1170,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i16.i16(
@@ -1187,8 +1187,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i16.i16(
@@ -1204,8 +1204,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i16.i16(
@@ -1221,8 +1221,8 @@ define <vscale x 32 x i1> @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmadc.carry.in.nxv32i16.i16(
@@ -1238,8 +1238,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i32.i32(
@@ -1255,8 +1255,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i32.i32(
@@ -1272,8 +1272,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32(
@@ -1289,8 +1289,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i32.i32(
@@ -1306,8 +1306,8 @@ define <vscale x 16 x i1> @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32(<vs
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmadc.carry.in.nxv16i32.i32(
@@ -1323,8 +1323,8 @@ define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v9, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64(
@@ -1340,8 +1340,8 @@ define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v10, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64(
@@ -1357,8 +1357,8 @@ define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v12, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64(
@@ -1374,8 +1374,8 @@ define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64(<vscal
; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmadc.vim v25, v8, 9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmadc.vim v16, v8, 9, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
index b972e55f2c253..8deb23a234760 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
@@ -1533,9 +1533,9 @@ define <vscale x 1 x i64> @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vmadd.vv v8, v25, v9
+; CHECK-NEXT: vmadd.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1563,9 +1563,9 @@ define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vmadd.vv v8, v25, v9, v0.t
+; CHECK-NEXT: vmadd.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1593,9 +1593,9 @@ define <vscale x 2 x i64> @intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vmadd.vv v8, v26, v10
+; CHECK-NEXT: vmadd.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1623,9 +1623,9 @@ define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vmadd.vv v8, v26, v10, v0.t
+; CHECK-NEXT: vmadd.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1653,9 +1653,9 @@ define <vscale x 4 x i64> @intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vmadd.vv v8, v28, v12
+; CHECK-NEXT: vmadd.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,9 +1683,9 @@ define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vmadd.vv v8, v28, v12, v0.t
+; CHECK-NEXT: vmadd.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
index 73a20142e5358..b8b5c38605ffa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
@@ -462,8 +462,8 @@ define <vscale x 1 x i64> @vmadd_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vmadd.vv v8, v25, v9
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmadd.vv v8, v10, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -499,8 +499,8 @@ define <vscale x 2 x i64> @vmadd_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vmacc.vv v8, v10, v26
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmacc.vv v8, v10, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -536,8 +536,8 @@ define <vscale x 4 x i64> @vmadd_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vmadd.vv v8, v28, v12
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmadd.vv v8, v16, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
index 7f0df02b138e6..6ca00ef5f2784 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vmax_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmax.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vmax_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmax.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmax.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vmax_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmax.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmax.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
index 3bedc8151deec..1b523efaf40a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
@@ -705,8 +705,8 @@ define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmax.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -750,8 +750,8 @@ define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmax.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -795,8 +795,8 @@ define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmax.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
index 1b67d501e27f2..3a187f5369323 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmaxu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmaxu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmaxu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmaxu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmaxu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmaxu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmaxu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmaxu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
index 97625371778fc..ba55434a24d6e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
@@ -705,8 +705,8 @@ define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmaxu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -750,8 +750,8 @@ define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmaxu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmaxu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -795,8 +795,8 @@ define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmaxu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmaxu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
index 5e5743466739a..f0e0328907136 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
@@ -895,8 +895,8 @@ define <vscale x 1 x i64> @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64(<vscale x 1
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -923,8 +923,8 @@ define <vscale x 2 x i64> @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64(<vscale x 2
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -951,8 +951,8 @@ define <vscale x 4 x i64> @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64(<vscale x 4
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
index 17e6963bd36a6..3ff4ffa7bcf0c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
@@ -1105,11 +1105,11 @@ define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1162,11 +1162,11 @@ define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1219,11 +1219,11 @@ define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
index 4e41827b0cf74..7d4b0376ca435 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfeq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
@@ -1097,12 +1097,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
@@ -1146,12 +1146,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
@@ -1195,12 +1195,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
index af62253486687..33a61ba4584f7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
@@ -1105,11 +1105,11 @@ define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1162,11 +1162,11 @@ define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1219,11 +1219,11 @@ define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
index 30a8fcdaf3b4b..29b0f001818aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
@@ -1097,12 +1097,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
@@ -1146,12 +1146,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
@@ -1195,12 +1195,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
index a606f4434afee..5e6d3aeb1580a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
@@ -1105,11 +1105,11 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1162,11 +1162,11 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1219,11 +1219,11 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
index f1e0442253370..4f109c5706416 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
@@ -1097,12 +1097,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
@@ -1146,12 +1146,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
@@ -1195,12 +1195,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
index 941bb73e82642..eac282bdf05c9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
@@ -1105,11 +1105,11 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1162,11 +1162,11 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1219,11 +1219,11 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
index 8246b9c8cc47b..94a40203cfed2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
@@ -1097,12 +1097,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
@@ -1146,12 +1146,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
@@ -1195,12 +1195,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
index 1c32ffa468951..c944d632f7929 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
@@ -1105,11 +1105,11 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1162,11 +1162,11 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1219,11 +1219,11 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
index e03cd16851c48..2db18bb32862a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmflt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
@@ -1097,12 +1097,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
@@ -1146,12 +1146,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
@@ -1195,12 +1195,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
index fbb7973ae1a74..efabe7512c8b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
@@ -1105,11 +1105,11 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1162,11 +1162,11 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1219,11 +1219,11 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
index c61dc9099fe0c..45f5b765a8ed1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 1
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
@@ -292,11 +292,11 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
@@ -344,11 +344,11 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
@@ -396,11 +396,11 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
@@ -448,11 +448,11 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
@@ -500,11 +500,11 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
@@ -552,11 +552,11 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
@@ -604,11 +604,11 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmfne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
@@ -656,12 +656,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
@@ -705,12 +705,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
@@ -754,12 +754,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
@@ -803,12 +803,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
@@ -852,12 +852,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
@@ -901,12 +901,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
@@ -950,12 +950,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
@@ -999,12 +999,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
@@ -1048,12 +1048,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
@@ -1097,12 +1097,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
@@ -1146,12 +1146,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
@@ -1195,12 +1195,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
index ef5426949edd5..992c67262ff41 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vmin_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmin.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmin.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmin.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vmin_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmin.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmin.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmin.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vmin_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmin.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmin.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmin.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
index 389a77115e627..43dff739d41ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
@@ -705,8 +705,8 @@ define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmin.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmin.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -750,8 +750,8 @@ define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmin.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmin.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -795,8 +795,8 @@ define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmin.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmin.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
index 4ad1709a50821..7da939e7b99c0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vminu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vminu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vminu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vminu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vminu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vminu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vminu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vminu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vminu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vminu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vminu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vminu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
index c5ca761907ef6..ca8cec7ce66a3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
@@ -705,8 +705,8 @@ define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vminu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vminu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -750,8 +750,8 @@ define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vminu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vminu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -795,8 +795,8 @@ define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vminu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vminu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
index a341a2cd50a5b..1ca8c1f0fe2bd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
@@ -814,8 +814,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64(<vscale x 1 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsbc.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsbc.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -840,8 +840,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64(<vscale x 2 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsbc.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsbc.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -866,8 +866,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64(<vscale x 4 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsbc.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsbc.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
index 4b1c899834539..a9902849e3e32 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
@@ -11,8 +11,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8(
@@ -34,8 +34,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8(
@@ -57,8 +57,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8(
@@ -80,8 +80,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i8.nxv8i8(
@@ -103,8 +103,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i8.nxv16i8(
@@ -126,8 +126,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i8.nxv32i8(
@@ -149,8 +149,8 @@ define <vscale x 64 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbc.borrow.in.nxv64i8.nxv64i8(
@@ -172,8 +172,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i16.nxv1i16(
@@ -195,8 +195,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i16.nxv2i16(
@@ -218,8 +218,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i16.nxv4i16(
@@ -241,8 +241,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i16.nxv8i16(
@@ -264,8 +264,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i16.nxv16i16(
@@ -287,8 +287,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i16.nxv32i16(
@@ -310,8 +310,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i32.nxv1i32(
@@ -333,8 +333,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i32.nxv2i32(
@@ -356,8 +356,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i32.nxv4i32(
@@ -379,8 +379,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i32.nxv8i32(
@@ -402,8 +402,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i32.nxv16i32(
@@ -425,8 +425,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i64.nxv1i64(
@@ -448,8 +448,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i64.nxv2i64(
@@ -471,8 +471,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i64.nxv4i64(
@@ -494,8 +494,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i64.nxv8i64(
@@ -517,8 +517,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8(
@@ -540,8 +540,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8(
@@ -563,8 +563,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.i8(
@@ -586,8 +586,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i8.i8(
@@ -609,8 +609,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8(<vsc
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i8.i8(
@@ -632,8 +632,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8(<vsc
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i8.i8(
@@ -655,8 +655,8 @@ define <vscale x 64 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8(<vsc
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbc.borrow.in.nxv64i8.i8(
@@ -678,8 +678,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i16.i16(
@@ -701,8 +701,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i16.i16(
@@ -724,8 +724,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i16.i16(
@@ -747,8 +747,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i16.i16(
@@ -770,8 +770,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16(<v
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i16.i16(
@@ -793,8 +793,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16(<v
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i16.i16(
@@ -816,8 +816,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i32.i32(
@@ -839,8 +839,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i32.i32(
@@ -862,8 +862,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i32.i32(
@@ -885,8 +885,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i32.i32(
@@ -908,8 +908,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32(<v
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i32.i32(
@@ -935,9 +935,9 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64(<vsca
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsbc.vvm v25, v8, v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsbc.vvm v9, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -964,9 +964,9 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64(<vsca
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsbc.vvm v25, v8, v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsbc.vvm v10, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -993,9 +993,9 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64(<vsca
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsbc.vvm v25, v8, v28, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmsbc.vvm v12, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1022,9 +1022,9 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64(<vsca
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v24, (a0), zero
+; CHECK-NEXT: vmsbc.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
index ee63343f9e4bf..e95cd217393cd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
@@ -11,8 +11,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8(
@@ -34,8 +34,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8(
@@ -57,8 +57,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8(
@@ -80,8 +80,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8(<vs
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i8.nxv8i8(
@@ -103,8 +103,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i8.nxv16i8(
@@ -126,8 +126,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i8.nxv32i8(
@@ -149,8 +149,8 @@ define <vscale x 64 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbc.borrow.in.nxv64i8.nxv64i8(
@@ -172,8 +172,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i16.nxv1i16(
@@ -195,8 +195,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i16.nxv2i16(
@@ -218,8 +218,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i16.nxv4i16(
@@ -241,8 +241,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i16.nxv8i16(
@@ -264,8 +264,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i16.nxv16i16(
@@ -287,8 +287,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i16.nxv32i16(
@@ -310,8 +310,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i32.nxv1i32(
@@ -333,8 +333,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i32.nxv2i32(
@@ -356,8 +356,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i32.nxv4i32(
@@ -379,8 +379,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i32.nxv8i32(
@@ -402,8 +402,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i32.nxv16i32(
@@ -425,8 +425,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i64.nxv1i64(
@@ -448,8 +448,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i64.nxv2i64(
@@ -471,8 +471,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i64.nxv4i64(
@@ -494,8 +494,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64(<
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i64.nxv8i64(
@@ -517,8 +517,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8(
@@ -540,8 +540,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8(
@@ -563,8 +563,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.i8(
@@ -586,8 +586,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i8.i8(
@@ -609,8 +609,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8(<vsc
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i8.i8(
@@ -632,8 +632,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8(<vsc
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i8.i8(
@@ -655,8 +655,8 @@ define <vscale x 64 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8(<vsc
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbc.borrow.in.nxv64i8.i8(
@@ -678,8 +678,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i16.i16(
@@ -701,8 +701,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i16.i16(
@@ -724,8 +724,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i16.i16(
@@ -747,8 +747,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i16.i16(
@@ -770,8 +770,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16(<v
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i16.i16(
@@ -793,8 +793,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16(<v
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.borrow.in.nxv32i16.i16(
@@ -816,8 +816,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i32.i32(
@@ -839,8 +839,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i32.i32(
@@ -862,8 +862,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i32.i32(
@@ -885,8 +885,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i32.i32(
@@ -908,8 +908,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32(<v
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.borrow.in.nxv16i32.i32(
@@ -931,8 +931,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v9, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i64.i64(
@@ -954,8 +954,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v10, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i64.i64(
@@ -977,8 +977,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v12, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i64.i64(
@@ -1000,8 +1000,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64(<vsca
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbc.vxm v16, v8, a0, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
index 5861898efed5b..ea87ba36f7435 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
@@ -28,11 +28,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
@@ -51,8 +51,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
@@ -70,11 +70,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
@@ -112,11 +112,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
@@ -135,8 +135,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
@@ -154,11 +154,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
@@ -177,8 +177,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
@@ -196,11 +196,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
@@ -219,8 +219,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
@@ -238,11 +238,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
@@ -261,8 +261,8 @@ define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
@@ -280,11 +280,11 @@ declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
index e8916bfbe2de3..a00ae90722569 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
@@ -28,11 +28,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
@@ -51,8 +51,8 @@ define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
@@ -70,11 +70,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
@@ -112,11 +112,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
@@ -135,8 +135,8 @@ define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
@@ -154,11 +154,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
@@ -177,8 +177,8 @@ define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
@@ -196,11 +196,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
@@ -219,8 +219,8 @@ define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
@@ -238,11 +238,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
@@ -261,8 +261,8 @@ define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsbf.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
@@ -280,11 +280,11 @@ declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsbf.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
index 40ff8d96022e4..db3b68f43674e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmseq.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmseq.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vv v10, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmseq.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmseq.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vv v11, v8, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmseq.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmseq.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vv v25, v8, v28, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vv v13, v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
index b418d9bba0741..38f2c69df1bd0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmseq.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
index 67ee7c3a338e0..983111ad6aafc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
@@ -946,8 +946,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
@@ -968,11 +968,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
@@ -994,8 +994,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
@@ -1016,11 +1016,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
@@ -1042,8 +1042,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
@@ -1064,11 +1064,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
@@ -1090,8 +1090,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
@@ -1112,11 +1112,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
@@ -1138,8 +1138,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i8_i8(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
@@ -1160,11 +1160,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
@@ -1186,8 +1186,8 @@ define <vscale x 32 x i1> @intrinsic_vmsge_vx_nxv32i8_i8(<vscale x 32 x i8> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
@@ -1208,11 +1208,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
@@ -1234,8 +1234,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i16_i16(<vscale x 1 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
@@ -1256,11 +1256,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
@@ -1282,8 +1282,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i16_i16(<vscale x 2 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
@@ -1304,11 +1304,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
@@ -1330,8 +1330,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i16_i16(<vscale x 4 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
@@ -1352,11 +1352,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
@@ -1378,8 +1378,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i16_i16(<vscale x 8 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
@@ -1400,11 +1400,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
@@ -1426,8 +1426,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i16_i16(<vscale x 16 x i16> %
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
@@ -1448,11 +1448,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
@@ -1474,8 +1474,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i32_i32(<vscale x 1 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
@@ -1496,11 +1496,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
@@ -1522,8 +1522,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i32_i32(<vscale x 2 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
@@ -1544,11 +1544,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
@@ -1570,8 +1570,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i32_i32(<vscale x 4 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
@@ -1592,11 +1592,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
@@ -1618,8 +1618,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i32_i32(<vscale x 8 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
@@ -1640,11 +1640,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
@@ -1670,8 +1670,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v25, v8
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1698,11 +1698,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vv v10, v11, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1729,8 +1729,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v26, v8
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1757,11 +1757,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vv v11, v12, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1788,8 +1788,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v28, v8
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1816,11 +1816,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vv v25, v28, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vv v13, v16, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1852,11 +1852,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
@@ -1887,11 +1887,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
@@ -1922,11 +1922,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
@@ -1957,11 +1957,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
@@ -1992,11 +1992,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
@@ -2027,11 +2027,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
@@ -2062,11 +2062,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
@@ -2097,11 +2097,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -1, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
@@ -2132,11 +2132,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
@@ -2167,11 +2167,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
@@ -2202,11 +2202,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
@@ -2237,11 +2237,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
@@ -2272,11 +2272,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
@@ -2307,11 +2307,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
@@ -2342,11 +2342,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
@@ -2377,11 +2377,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
@@ -2412,11 +2412,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
@@ -2447,11 +2447,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
@@ -2469,8 +2469,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
@@ -2487,8 +2487,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
@@ -2505,8 +2505,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
@@ -2523,8 +2523,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
@@ -2541,8 +2541,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
@@ -2559,8 +2559,8 @@ define <vscale x 32 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
@@ -2577,8 +2577,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
@@ -2595,8 +2595,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
@@ -2613,8 +2613,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
@@ -2631,8 +2631,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
@@ -2649,8 +2649,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
@@ -2667,8 +2667,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
@@ -2685,8 +2685,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
@@ -2703,8 +2703,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
@@ -2721,8 +2721,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
@@ -2743,8 +2743,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v25, v8, v0.t
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -2766,10 +2766,10 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmsle.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -2791,10 +2791,10 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vmsle.vv v25, v28, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v12, v0
+; CHECK-NEXT: vmsle.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
index e411543612b9e..6df0024db836d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
@@ -946,8 +946,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
@@ -968,11 +968,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
@@ -994,8 +994,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
@@ -1016,11 +1016,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
@@ -1042,8 +1042,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
@@ -1064,11 +1064,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
@@ -1090,8 +1090,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
@@ -1112,11 +1112,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
@@ -1138,8 +1138,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i8_i8(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
@@ -1160,11 +1160,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
@@ -1186,8 +1186,8 @@ define <vscale x 32 x i1> @intrinsic_vmsge_vx_nxv32i8_i8(<vscale x 32 x i8> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
@@ -1208,11 +1208,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
@@ -1234,8 +1234,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i16_i16(<vscale x 1 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
@@ -1256,11 +1256,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
@@ -1282,8 +1282,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i16_i16(<vscale x 2 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
@@ -1304,11 +1304,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
@@ -1330,8 +1330,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i16_i16(<vscale x 4 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
@@ -1352,11 +1352,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
@@ -1378,8 +1378,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i16_i16(<vscale x 8 x i16> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
@@ -1400,11 +1400,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
@@ -1426,8 +1426,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i16_i16(<vscale x 16 x i16> %
; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
@@ -1448,11 +1448,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
@@ -1474,8 +1474,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i32_i32(<vscale x 1 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
@@ -1496,11 +1496,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
@@ -1522,8 +1522,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i32_i32(<vscale x 2 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
@@ -1544,11 +1544,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
@@ -1570,8 +1570,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i32_i32(<vscale x 4 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
@@ -1592,11 +1592,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
@@ -1618,8 +1618,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i32_i32(<vscale x 8 x i32> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
@@ -1640,11 +1640,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
@@ -1666,8 +1666,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(
@@ -1688,11 +1688,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(
@@ -1736,11 +1736,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
@@ -1762,8 +1762,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(
@@ -1784,11 +1784,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
@@ -1819,11 +1819,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
@@ -1854,11 +1854,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
@@ -1889,11 +1889,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
@@ -1924,11 +1924,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
@@ -1959,11 +1959,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
@@ -1994,11 +1994,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
@@ -2029,11 +2029,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
@@ -2064,11 +2064,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, -1, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
@@ -2099,11 +2099,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
@@ -2134,11 +2134,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
@@ -2169,11 +2169,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
@@ -2204,11 +2204,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
@@ -2239,11 +2239,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
@@ -2274,11 +2274,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
@@ -2309,11 +2309,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
@@ -2344,11 +2344,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
@@ -2379,11 +2379,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, -16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, -16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
@@ -2414,11 +2414,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, -14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, -14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
@@ -2436,8 +2436,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
@@ -2454,8 +2454,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
@@ -2472,8 +2472,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
@@ -2490,8 +2490,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
@@ -2508,8 +2508,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
@@ -2526,8 +2526,8 @@ define <vscale x 32 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
@@ -2544,8 +2544,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
@@ -2562,8 +2562,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
@@ -2580,8 +2580,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
@@ -2598,8 +2598,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
@@ -2616,8 +2616,8 @@ define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16(<vscal
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
@@ -2634,8 +2634,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
@@ -2652,8 +2652,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
@@ -2670,8 +2670,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
@@ -2688,8 +2688,8 @@ define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
@@ -2706,8 +2706,8 @@ define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
@@ -2724,8 +2724,8 @@ define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
@@ -2742,8 +2742,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmslt.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmslt.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
index 4b62178aaefbe..72d2c044539cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
@@ -946,8 +946,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
@@ -968,11 +968,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
@@ -994,8 +994,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
@@ -1016,11 +1016,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
@@ -1042,8 +1042,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
@@ -1064,11 +1064,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
@@ -1090,8 +1090,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
@@ -1112,11 +1112,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
@@ -1138,8 +1138,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i8_i8(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
@@ -1160,11 +1160,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
@@ -1186,8 +1186,8 @@ define <vscale x 32 x i1> @intrinsic_vmsgeu_vx_nxv32i8_i8(<vscale x 32 x i8> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
@@ -1208,11 +1208,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
@@ -1234,8 +1234,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i16_i16(<vscale x 1 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
@@ -1256,11 +1256,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
@@ -1282,8 +1282,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i16_i16(<vscale x 2 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
@@ -1304,11 +1304,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -1330,8 +1330,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i16_i16(<vscale x 4 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
@@ -1352,11 +1352,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
@@ -1378,8 +1378,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i16_i16(<vscale x 8 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
@@ -1400,11 +1400,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
@@ -1426,8 +1426,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i16_i16(<vscale x 16 x i16>
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
@@ -1448,11 +1448,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
@@ -1474,8 +1474,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i32_i32(<vscale x 1 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
@@ -1496,11 +1496,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
@@ -1522,8 +1522,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i32_i32(<vscale x 2 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
@@ -1544,11 +1544,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
@@ -1570,8 +1570,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i32_i32(<vscale x 4 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
@@ -1592,11 +1592,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
@@ -1618,8 +1618,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i32_i32(<vscale x 8 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
@@ -1640,11 +1640,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
@@ -1670,8 +1670,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v25, v8
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1698,11 +1698,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vv v10, v11, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1729,8 +1729,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v26, v8
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1757,11 +1757,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vv v11, v12, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1788,8 +1788,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v28, v8
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1816,11 +1816,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vv v25, v28, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vv v13, v16, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1852,11 +1852,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
@@ -1887,11 +1887,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
@@ -1922,11 +1922,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
@@ -1957,11 +1957,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
@@ -1992,11 +1992,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
@@ -2027,11 +2027,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
@@ -2062,11 +2062,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
@@ -2097,11 +2097,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vv v10, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -2132,11 +2132,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
@@ -2167,11 +2167,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
@@ -2202,11 +2202,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
@@ -2237,11 +2237,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
@@ -2272,11 +2272,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
@@ -2307,11 +2307,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
@@ -2342,11 +2342,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
@@ -2377,11 +2377,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
@@ -2412,11 +2412,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, -16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
@@ -2447,11 +2447,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, -14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
@@ -2469,8 +2469,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
@@ -2487,8 +2487,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
@@ -2505,8 +2505,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
@@ -2523,8 +2523,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
@@ -2541,8 +2541,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
@@ -2559,8 +2559,8 @@ define <vscale x 32 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
@@ -2577,8 +2577,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
@@ -2595,8 +2595,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -2613,8 +2613,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
@@ -2631,8 +2631,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
@@ -2649,8 +2649,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
@@ -2667,8 +2667,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
@@ -2685,8 +2685,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
@@ -2703,8 +2703,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
@@ -2721,8 +2721,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
@@ -2743,8 +2743,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v25, v8, v0.t
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsleu.vv v0, v9, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -2766,10 +2766,10 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmsleu.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -2791,10 +2791,10 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vmsleu.vv v25, v28, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v12, v0
+; CHECK-NEXT: vmsleu.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
index ff4daa3c147c0..0999549724f0e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
@@ -946,8 +946,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
@@ -968,11 +968,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
@@ -994,8 +994,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
@@ -1016,11 +1016,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
@@ -1042,8 +1042,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
@@ -1064,11 +1064,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
@@ -1090,8 +1090,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
@@ -1112,11 +1112,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
@@ -1138,8 +1138,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i8_i8(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
@@ -1160,11 +1160,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
@@ -1186,8 +1186,8 @@ define <vscale x 32 x i1> @intrinsic_vmsgeu_vx_nxv32i8_i8(<vscale x 32 x i8> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
@@ -1208,11 +1208,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
@@ -1234,8 +1234,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i16_i16(<vscale x 1 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
@@ -1256,11 +1256,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
@@ -1282,8 +1282,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i16_i16(<vscale x 2 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
@@ -1304,11 +1304,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -1330,8 +1330,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i16_i16(<vscale x 4 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
@@ -1352,11 +1352,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
@@ -1378,8 +1378,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i16_i16(<vscale x 8 x i16> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
@@ -1400,11 +1400,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
@@ -1426,8 +1426,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i16_i16(<vscale x 16 x i16>
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
@@ -1448,11 +1448,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
@@ -1474,8 +1474,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i32_i32(<vscale x 1 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
@@ -1496,11 +1496,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
@@ -1522,8 +1522,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i32_i32(<vscale x 2 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
@@ -1544,11 +1544,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
@@ -1570,8 +1570,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i32_i32(<vscale x 4 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
@@ -1592,11 +1592,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
@@ -1618,8 +1618,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i32_i32(<vscale x 8 x i32> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
@@ -1640,11 +1640,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
@@ -1666,8 +1666,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(
@@ -1688,11 +1688,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v9
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v10, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(
@@ -1736,11 +1736,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v10
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
@@ -1762,8 +1762,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmnand.mm v0, v25, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmnand.mm v0, v12, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(
@@ -1784,11 +1784,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmxor.mm v0, v25, v12
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
@@ -1819,11 +1819,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
@@ -1854,11 +1854,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
@@ -1889,11 +1889,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
@@ -1924,11 +1924,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
@@ -1959,11 +1959,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
@@ -1994,11 +1994,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
@@ -2029,11 +2029,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
@@ -2064,11 +2064,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmseq.vv v10, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -2099,11 +2099,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
@@ -2134,11 +2134,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
@@ -2169,11 +2169,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
@@ -2204,11 +2204,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
@@ -2239,11 +2239,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
@@ -2274,11 +2274,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
@@ -2309,11 +2309,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
@@ -2344,11 +2344,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
@@ -2379,11 +2379,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, -16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
@@ -2414,11 +2414,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, -14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
@@ -2436,8 +2436,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
@@ -2454,8 +2454,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
@@ -2472,8 +2472,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
@@ -2490,8 +2490,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8(<vscale x
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
@@ -2508,8 +2508,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
@@ -2526,8 +2526,8 @@ define <vscale x 32 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
@@ -2544,8 +2544,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
@@ -2562,8 +2562,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -2580,8 +2580,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
@@ -2598,8 +2598,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
@@ -2616,8 +2616,8 @@ define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16(<vsca
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
@@ -2634,8 +2634,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
@@ -2652,8 +2652,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
@@ -2670,8 +2670,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
@@ -2688,8 +2688,8 @@ define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
@@ -2706,8 +2706,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v8, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
@@ -2724,8 +2724,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
@@ -2742,8 +2742,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmsltu.vx v25, v8, a0
-; CHECK-NEXT: vmandnot.mm v0, v0, v25
+; CHECK-NEXT: vmsltu.vx v12, v8, a0
+; CHECK-NEXT: vmandnot.mm v0, v0, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
index 1687a6b34563f..7c4556d5493ea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v25, v8
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmslt.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vv v10, v11, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v26, v8
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmslt.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vv v11, v12, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v28, v8
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmslt.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vv v25, v28, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vv v13, v16, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
index b0a992aeb093f..6fc625c8eed6a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
index 3b3edb04916d5..00c19c1cf1879 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v25, v8
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsltu.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vv v10, v11, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v26, v8
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsltu.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vv v11, v12, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v28, v8
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsltu.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vv v25, v28, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vv v13, v16, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
index b0898d6eaa656..c3f1890c4a349 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v9, v8
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v10, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v10, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v12, v8
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v12, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
index ccae7ce26129f..729a40cc6b87f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
@@ -28,11 +28,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
@@ -51,8 +51,8 @@ define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
@@ -70,11 +70,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
@@ -112,11 +112,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
@@ -135,8 +135,8 @@ define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
@@ -154,11 +154,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
@@ -177,8 +177,8 @@ define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
@@ -196,11 +196,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
@@ -219,8 +219,8 @@ define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
@@ -238,11 +238,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
@@ -261,8 +261,8 @@ define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
@@ -280,11 +280,11 @@ declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
index 64f446a9d53cc..af2238ec1f246 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
@@ -28,11 +28,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
@@ -51,8 +51,8 @@ define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
@@ -70,11 +70,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
@@ -112,11 +112,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
@@ -135,8 +135,8 @@ define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
@@ -154,11 +154,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
@@ -177,8 +177,8 @@ define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
@@ -196,11 +196,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
@@ -219,8 +219,8 @@ define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
@@ -238,11 +238,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
@@ -261,8 +261,8 @@ define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsif.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
@@ -280,11 +280,11 @@ declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsif.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsif.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
index 44484b0050cc7..38ee92455a3be 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsle.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vv v10, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsle.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vv v11, v8, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsle.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsle.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vv v25, v8, v28, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vv v13, v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
index be1e77de78d4d..0f8db99807e12 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsle.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsle.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
index 6ba9aa1da3d17..31a4f3f63e9ec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsleu.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vv v10, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsleu.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vv v11, v8, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsleu.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsleu.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vv v25, v8, v28, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vv v13, v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
index 10016dd411030..311caf94415c4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsleu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsleu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
index cfe08d9816816..21cc5b9fbd6df 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmslt.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vv v10, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmslt.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vv v11, v8, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmslt.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmslt.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vv v25, v8, v28, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vv v13, v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -1, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
index 1053315954316..65e657fad254a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmslt.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmslt.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, -1, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsle.vi v25, v8, 14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v10, v8, 14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsle.vi v25, v8, -16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v11, v8, -16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsle.vi v25, v8, -14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsle.vi v13, v8, -14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
index 0ea23255f0e58..8ff7727efe307 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsltu.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vv v10, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsltu.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vv v11, v8, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsltu.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsltu.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vv v25, v8, v28, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vv v13, v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vv v10, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, -16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, -14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
index f3d934a409fb1..3ed8e9572e348 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsltu.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsltu.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -15, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -13, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, -7, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, -5, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, -3, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vv v10, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 2, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 4, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, 10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, 12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v10, v8, 14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v11, v8, -16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsleu.vi v13, v8, -14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
index 316c750e2b2fc..a7ffa3ab58540 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
@@ -1655,8 +1655,8 @@ define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i64_i64(<vscale x 1 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmsne.vv v0, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmsne.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,11 +1683,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v11, (a0), zero
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vv v10, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1714,8 +1714,8 @@ define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i64_i64(<vscale x 2 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmsne.vv v0, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmsne.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1742,11 +1742,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vv v11, v8, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1773,8 +1773,8 @@ define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i64_i64(<vscale x 4 x i64> %0,
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmsne.vv v0, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmsne.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1801,11 +1801,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vlse64.v v16, (a0), zero
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vv v25, v8, v28, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vv v13, v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1837,11 +1837,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
@@ -1872,11 +1872,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
@@ -1907,11 +1907,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
@@ -1942,11 +1942,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
@@ -1977,11 +1977,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
@@ -2012,11 +2012,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
@@ -2047,11 +2047,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
@@ -2082,11 +2082,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
@@ -2117,11 +2117,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
@@ -2152,11 +2152,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
@@ -2187,11 +2187,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
@@ -2222,11 +2222,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
@@ -2257,11 +2257,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
@@ -2292,11 +2292,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
@@ -2327,11 +2327,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
@@ -2362,11 +2362,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
@@ -2397,11 +2397,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
@@ -2432,11 +2432,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
index a6ec285e1092e..c8143026ea353 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
@@ -32,11 +32,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
@@ -84,11 +84,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
@@ -136,11 +136,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
@@ -188,11 +188,11 @@ define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
@@ -240,11 +240,11 @@ define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
@@ -292,11 +292,11 @@ define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
@@ -344,11 +344,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
@@ -396,11 +396,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
@@ -448,11 +448,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
@@ -500,11 +500,11 @@ define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
@@ -552,11 +552,11 @@ define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 1
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
@@ -604,11 +604,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
@@ -656,11 +656,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
@@ -708,11 +708,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
@@ -760,11 +760,11 @@ define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
@@ -812,11 +812,11 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v8, v8, v9
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
@@ -864,11 +864,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v14, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
@@ -916,11 +916,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmsne.vv v25, v8, v12
-; CHECK-NEXT: vmv1r.v v26, v0
-; CHECK-NEXT: vmv1r.v v0, v25
-; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmsne.vv v20, v8, v12
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
@@ -967,11 +967,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
@@ -1014,11 +1014,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
@@ -1061,11 +1061,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
@@ -1108,11 +1108,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
@@ -1155,11 +1155,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
@@ -1202,11 +1202,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
@@ -1249,11 +1249,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
@@ -1296,11 +1296,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
@@ -1343,11 +1343,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
@@ -1390,11 +1390,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
@@ -1437,11 +1437,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
@@ -1484,11 +1484,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
@@ -1531,11 +1531,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
@@ -1578,11 +1578,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
@@ -1625,11 +1625,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
@@ -1672,11 +1672,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
@@ -1719,11 +1719,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
@@ -1766,11 +1766,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
@@ -1801,11 +1801,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
@@ -1836,11 +1836,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
@@ -1871,11 +1871,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
@@ -1906,11 +1906,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
@@ -1941,11 +1941,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
@@ -1976,11 +1976,11 @@ entry:
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
@@ -2011,11 +2011,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
@@ -2046,11 +2046,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
@@ -2081,11 +2081,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
@@ -2116,11 +2116,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
@@ -2151,11 +2151,11 @@ entry:
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
@@ -2186,11 +2186,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
@@ -2221,11 +2221,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
@@ -2256,11 +2256,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
@@ -2291,11 +2291,11 @@ entry:
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
@@ -2326,11 +2326,11 @@ entry:
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
@@ -2361,11 +2361,11 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
@@ -2396,11 +2396,11 @@ entry:
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
index 9dac52abb2366..e4c1d4253bf4b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
@@ -28,11 +28,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
@@ -51,8 +51,8 @@ define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
@@ -70,11 +70,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
@@ -112,11 +112,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
@@ -135,8 +135,8 @@ define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
@@ -154,11 +154,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
@@ -177,8 +177,8 @@ define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
@@ -196,11 +196,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
@@ -219,8 +219,8 @@ define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
@@ -238,11 +238,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
@@ -261,8 +261,8 @@ define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i32
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
@@ -280,11 +280,11 @@ declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
index 90f04745735c2..c68110dbb66bf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
@@ -28,11 +28,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
@@ -51,8 +51,8 @@ define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
@@ -70,11 +70,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
@@ -93,8 +93,8 @@ define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
@@ -112,11 +112,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
@@ -135,8 +135,8 @@ define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1)
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
@@ -154,11 +154,11 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
@@ -177,8 +177,8 @@ define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
@@ -196,11 +196,11 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
@@ -219,8 +219,8 @@ define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
@@ -238,11 +238,11 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
@@ -261,8 +261,8 @@ define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i64
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsof.m v25, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v8, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
@@ -280,11 +280,11 @@ declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsof.m v25, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmsof.m v10, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
index 8b3023e1627ed..02564ccc1777a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
index c2ac91c7651cc..cbef358319d60 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
@@ -650,8 +650,8 @@ define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -716,8 +716,8 @@ define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -782,8 +782,8 @@ define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
index 0e52651c1ebd3..bcf43854f94e6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
@@ -1001,9 +1001,9 @@ define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v25, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1027,9 +1027,9 @@ define <vscale x 1 x i64> @vmul_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v25
+; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1079,9 +1079,9 @@ define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v26, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1105,9 +1105,9 @@ define <vscale x 2 x i64> @vmul_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v26
+; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1157,9 +1157,9 @@ define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v28, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1183,9 +1183,9 @@ define <vscale x 4 x i64> @vmul_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmul.vv v8, v8, v28
+; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
index 9080748139d08..a9efb2b91566e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmulh.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmulh.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmulh.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
index 32ccf4b008dc0..178926a05463b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
@@ -8,13 +8,13 @@ define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 42
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: addi a1, zero, -85
-; CHECK-NEXT: vmacc.vx v25, a1, v8
-; CHECK-NEXT: vsll.vi v26, v25, 7
-; CHECK-NEXT: vsrl.vi v25, v25, 1
-; CHECK-NEXT: vor.vv v25, v25, v26
-; CHECK-NEXT: vmsleu.vx v0, v25, a0
+; CHECK-NEXT: vmacc.vx v9, a1, v8
+; CHECK-NEXT: vsll.vi v8, v9, 7
+; CHECK-NEXT: vsrl.vi v9, v9, 1
+; CHECK-NEXT: vor.vv v8, v9, v8
+; CHECK-NEXT: vmsleu.vx v0, v8, a0
; CHECK-NEXT: ret
%head_six = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat_six = shufflevector <vscale x 4 x i8> %head_six, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
index 791f80f044203..a9b03186ba0a2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64(<vscale x 1
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmulhsu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64(<vscale x 2
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmulhsu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64(<vscale x 4
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmulhsu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
index 1f20f05d25e37..512b3ce5c885e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmulhu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmulhu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
index 12ebdcba8e3d8..fa001c38ef796 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
@@ -245,10 +245,10 @@ define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(<vscale x 1 x i64> %0, i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vid.v v26
-; CHECK-NEXT: vmseq.vi v0, v26, 0
-; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vmseq.vi v0, v10, 0
+; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -266,10 +266,10 @@ define <vscale x 2 x i64> @intrinsic_vmv.s.x_x_nxv2i64(<vscale x 2 x i64> %0, i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vid.v v28
-; CHECK-NEXT: vmseq.vi v0, v28, 0
-; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vid.v v12
+; CHECK-NEXT: vmseq.vi v0, v12, 0
+; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -287,10 +287,10 @@ define <vscale x 4 x i64> @intrinsic_vmv.s.x_x_nxv4i64(<vscale x 4 x i64> %0, i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vid.v v12
-; CHECK-NEXT: vmseq.vi v0, v12, 0
-; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vid.v v16
+; CHECK-NEXT: vmseq.vi v0, v16, 0
+; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
index e738752df9a26..0e2c7a77431fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
@@ -242,8 +242,8 @@ define i64 @intrinsic_vmv.x.s_s_nxv1i64(<vscale x 1 x i64> %0) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v8, a0
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v9, v8, a0
+; CHECK-NEXT: vmv.x.s a1, v9
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
@@ -258,8 +258,8 @@ define i64 @intrinsic_vmv.x.s_s_nxv2i64(<vscale x 2 x i64> %0) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; CHECK-NEXT: vsrl.vx v26, v8, a0
-; CHECK-NEXT: vmv.x.s a1, v26
+; CHECK-NEXT: vsrl.vx v10, v8, a0
+; CHECK-NEXT: vmv.x.s a1, v10
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
@@ -274,8 +274,8 @@ define i64 @intrinsic_vmv.x.s_s_nxv4i64(<vscale x 4 x i64> %0) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
-; CHECK-NEXT: vsrl.vx v28, v8, a0
-; CHECK-NEXT: vmv.x.s a1, v28
+; CHECK-NEXT: vsrl.vx v12, v8, a0
+; CHECK-NEXT: vmv.x.s a1, v12
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
index 26a91827a0bc9..e57b98f1dd5ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclip.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclip.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8(<vscale
; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclip.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclip.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclip.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16(<vsca
; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclip.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclip.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclip.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclip.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnclip_vx_nxv8i8_nxv8i16(<vscale x 8 x i16>
; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnclip_vx_nxv16i8_nxv16i16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnclip.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnclip_vx_nxv32i8_nxv32i16(<vscale x 32 x i
; CHECK-LABEL: intrinsic_vnclip_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnclip.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnclip_vx_nxv4i16_nxv4i32(<vscale x 4 x i32
; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnclip_vx_nxv8i16_nxv8i32(<vscale x 8 x i32
; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnclip.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnclip_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnclip.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnclip_vx_nxv2i32_nxv2i64(<vscale x 2 x i64
; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnclip_vx_nxv4i32_nxv4i64(<vscale x 4 x i64
; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnclip.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnclip_vx_nxv8i32_nxv8i64(<vscale x 8 x i64
; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnclip.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclip.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8(<vscale x 32
; CHECK-LABEL: intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclip.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclip.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16(<vscale x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclip.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclip.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclip.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
index 2d2b8dd499b38..21497e0cc7644 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclip.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclip.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8(<vscale
; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclip.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclip.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclip.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16(<vsca
; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclip.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclip.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclip.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclip.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnclip_vx_nxv8i8_nxv8i16(<vscale x 8 x i16>
; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnclip_vx_nxv16i8_nxv16i16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnclip.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnclip_vx_nxv32i8_nxv32i16(<vscale x 32 x i
; CHECK-LABEL: intrinsic_vnclip_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnclip.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnclip_vx_nxv4i16_nxv4i32(<vscale x 4 x i32
; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnclip_vx_nxv8i16_nxv8i32(<vscale x 8 x i32
; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnclip.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnclip_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnclip.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnclip_vx_nxv2i32_nxv2i64(<vscale x 2 x i64
; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnclip.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnclip_vx_nxv4i32_nxv4i64(<vscale x 4 x i64
; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnclip.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnclip_vx_nxv8i32_nxv8i64(<vscale x 8 x i64
; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnclip.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i1
; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclip.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8(<vscale x 32
; CHECK-LABEL: intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclip.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclip.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16(<vscale x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclip.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclip.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclip.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclip.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclip.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclip.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclip.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
index f839089ffac3b..42f4ecf3e4fcf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclipu.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclipu.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclipu.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16(<vsc
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclipu.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclipu.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclipu.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnclipu_vx_nxv8i8_nxv8i16(<vscale x 8 x i16>
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnclipu_vx_nxv16i8_nxv16i16(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnclipu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnclipu_vx_nxv32i8_nxv32i16(<vscale x 32 x
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnclipu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnclipu_vx_nxv4i16_nxv4i32(<vscale x 4 x i3
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnclipu_vx_nxv8i16_nxv8i32(<vscale x 8 x i3
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnclipu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnclipu_vx_nxv16i16_nxv16i32(<vscale x 16
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnclipu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnclipu_vx_nxv2i32_nxv2i64(<vscale x 2 x i6
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnclipu_vx_nxv4i32_nxv4i64(<vscale x 4 x i6
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnclipu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnclipu_vx_nxv8i32_nxv8i64(<vscale x 8 x i6
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnclipu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclipu.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8(<vscale x 32
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclipu.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16(<vscale x 4
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16(<vscale x 8
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclipu.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16(<vscale x
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclipu.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclipu.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32(<vscale x 8
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclipu.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
index 6d85bce2c20e0..e8e28e5482bdf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclipu.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclipu.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclipu.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16(<vsc
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclipu.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclipu.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclipu.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclipu.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnclipu_vx_nxv8i8_nxv8i16(<vscale x 8 x i16>
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnclipu_vx_nxv16i8_nxv16i16(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnclipu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnclipu_vx_nxv32i8_nxv32i16(<vscale x 32 x
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnclipu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnclipu_vx_nxv4i16_nxv4i32(<vscale x 4 x i3
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnclipu_vx_nxv8i16_nxv8i32(<vscale x 8 x i3
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnclipu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnclipu_vx_nxv16i16_nxv16i32(<vscale x 16
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnclipu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnclipu_vx_nxv2i32_nxv2i64(<vscale x 2 x i6
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnclipu.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnclipu_vx_nxv4i32_nxv4i64(<vscale x 4 x i6
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnclipu.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnclipu_vx_nxv8i32_nxv8i64(<vscale x 8 x i6
; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnclipu.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnclipu.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8(<vscale x 32
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnclipu.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16(<vscale x 4
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16(<vscale x 8
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnclipu.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16(<vscale x
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnclipu.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnclipu.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnclipu.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnclipu.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnclipu.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32(<vscale x 8
; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnclipu.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnclipu.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
index 13217aec64f0b..5ba99c50dc74f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
@@ -1533,9 +1533,9 @@ define <vscale x 1 x i64> @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64(<vscale x 1
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vnmsac.vv v8, v25, v9
+; CHECK-NEXT: vnmsac.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1563,9 +1563,9 @@ define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vnmsac.vv v8, v25, v9, v0.t
+; CHECK-NEXT: vnmsac.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1593,9 +1593,9 @@ define <vscale x 2 x i64> @intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64(<vscale x 2
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vnmsac.vv v8, v26, v10
+; CHECK-NEXT: vnmsac.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1623,9 +1623,9 @@ define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vnmsac.vv v8, v26, v10, v0.t
+; CHECK-NEXT: vnmsac.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1653,9 +1653,9 @@ define <vscale x 4 x i64> @intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64(<vscale x 4
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vnmsac.vv v8, v28, v12
+; CHECK-NEXT: vnmsac.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,9 +1683,9 @@ define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vnmsac.vv v8, v28, v12, v0.t
+; CHECK-NEXT: vnmsac.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
index 7f30d180681f4..372ba28bd459b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
@@ -1533,9 +1533,9 @@ define <vscale x 1 x i64> @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64(<vscale x 1
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vnmsub.vv v8, v25, v9
+; CHECK-NEXT: vnmsub.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1563,9 +1563,9 @@ define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
-; CHECK-NEXT: vnmsub.vv v8, v25, v9, v0.t
+; CHECK-NEXT: vnmsub.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1593,9 +1593,9 @@ define <vscale x 2 x i64> @intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64(<vscale x 2
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vnmsub.vv v8, v26, v10
+; CHECK-NEXT: vnmsub.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1623,9 +1623,9 @@ define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
-; CHECK-NEXT: vnmsub.vv v8, v26, v10, v0.t
+; CHECK-NEXT: vnmsub.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1653,9 +1653,9 @@ define <vscale x 4 x i64> @intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64(<vscale x 4
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vnmsub.vv v8, v28, v12
+; CHECK-NEXT: vnmsub.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1683,9 +1683,9 @@ define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
-; CHECK-NEXT: vnmsub.vv v8, v28, v12, v0.t
+; CHECK-NEXT: vnmsub.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
index d981c9569b79e..075c0a35f05b7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
@@ -462,8 +462,8 @@ define <vscale x 1 x i64> @vnmsub_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vnmsub.vv v8, v25, v9
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vnmsub.vv v8, v10, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -499,8 +499,8 @@ define <vscale x 2 x i64> @vnmsub_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vnmsac.vv v8, v10, v26
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vnmsac.vv v8, v10, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -536,8 +536,8 @@ define <vscale x 4 x i64> @vnmsub_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vnmsub.vv v8, v28, v12
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vnmsub.vv v8, v16, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
index e47d74669b95b..560f4510038cf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsra.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsra.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsra.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsra.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsra.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16(<vscal
; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsra.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnsra_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %
; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnsra_vx_nxv16i8_nxv16i16(<vscale x 16 x i1
; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnsra_vx_nxv32i8_nxv32i16(<vscale x 32 x i1
; CHECK-LABEL: intrinsic_vnsra_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnsra_vx_nxv4i16_nxv4i32(<vscale x 4 x i32>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnsra_vx_nxv8i16_nxv8i32(<vscale x 8 x i32>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnsra_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnsra_vx_nxv2i32_nxv2i64(<vscale x 2 x i64>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnsra_vx_nxv4i32_nxv4i64(<vscale x 4 x i64>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnsra_vx_nxv8i32_nxv8i64(<vscale x 8 x i64>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16
; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsra.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsra.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsra.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16(<vscale x 1
; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsra.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
index 5cacd53ad1c95..fc1f3f0e8ba12 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsra.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsra.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsra.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsra.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsra.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16(<vscal
; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsra.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnsra_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %
; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnsra_vx_nxv16i8_nxv16i16(<vscale x 16 x i1
; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnsra_vx_nxv32i8_nxv32i16(<vscale x 32 x i1
; CHECK-LABEL: intrinsic_vnsra_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnsra_vx_nxv4i16_nxv4i32(<vscale x 4 x i32>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnsra_vx_nxv8i16_nxv8i32(<vscale x 8 x i32>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnsra_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnsra_vx_nxv2i32_nxv2i64(<vscale x 2 x i64>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnsra_vx_nxv4i32_nxv4i64(<vscale x 4 x i64>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnsra_vx_nxv8i32_nxv8i64(<vscale x 8 x i64>
; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16
; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsra.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsra.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsra.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16(<vscale x 1
; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsra.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsra.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsra.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsra.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsra.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsra.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsra.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
index b3384d5b0999b..2c0330fd2b0f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsrl.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16(<vscal
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnsrl_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnsrl_vx_nxv16i8_nxv16i16(<vscale x 16 x i1
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnsrl_vx_nxv32i8_nxv32i16(<vscale x 32 x i1
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnsrl_vx_nxv4i16_nxv4i32(<vscale x 4 x i32>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnsrl_vx_nxv8i16_nxv8i32(<vscale x 8 x i32>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnsrl_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnsrl_vx_nxv2i32_nxv2i64(<vscale x 2 x i64>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnsrl_vx_nxv4i32_nxv4i64(<vscale x 4 x i64>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnsrl_vx_nxv8i32_nxv8i64(<vscale x 8 x i64>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16(<vscale x 1
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
index e1982f72da336..5e453c045e07a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
@@ -145,8 +145,8 @@ define <vscale x 8 x i8> @intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8(
@@ -191,8 +191,8 @@ define <vscale x 16 x i8> @intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8(
@@ -237,8 +237,8 @@ define <vscale x 32 x i8> @intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsrl.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.nxv32i8(
@@ -373,8 +373,8 @@ define <vscale x 4 x i16> @intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16(
@@ -419,8 +419,8 @@ define <vscale x 8 x i16> @intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.nxv8i16(
@@ -465,8 +465,8 @@ define <vscale x 16 x i16> @intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16(<vscal
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.nxv16i16(
@@ -556,8 +556,8 @@ define <vscale x 2 x i32> @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v11
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32(
@@ -602,8 +602,8 @@ define <vscale x 4 x i32> @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v14
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32(
@@ -648,8 +648,8 @@ define <vscale x 8 x i32> @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v20
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32(
@@ -829,8 +829,8 @@ define <vscale x 8 x i8> @intrinsic_vnsrl_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
@@ -875,8 +875,8 @@ define <vscale x 16 x i8> @intrinsic_vnsrl_vx_nxv16i8_nxv16i16(<vscale x 16 x i1
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
@@ -921,8 +921,8 @@ define <vscale x 32 x i8> @intrinsic_vnsrl_vx_nxv32i8_nxv32i16(<vscale x 32 x i1
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
@@ -1057,8 +1057,8 @@ define <vscale x 4 x i16> @intrinsic_vnsrl_vx_nxv4i16_nxv4i32(<vscale x 4 x i32>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
@@ -1103,8 +1103,8 @@ define <vscale x 8 x i16> @intrinsic_vnsrl_vx_nxv8i16_nxv8i32(<vscale x 8 x i32>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
@@ -1149,8 +1149,8 @@ define <vscale x 16 x i16> @intrinsic_vnsrl_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
@@ -1240,8 +1240,8 @@ define <vscale x 2 x i32> @intrinsic_vnsrl_vx_nxv2i32_nxv2i64(<vscale x 2 x i64>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(
@@ -1286,8 +1286,8 @@ define <vscale x 4 x i32> @intrinsic_vnsrl_vx_nxv4i32_nxv4i64(<vscale x 4 x i64>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(
@@ -1332,8 +1332,8 @@ define <vscale x 8 x i32> @intrinsic_vnsrl_vx_nxv8i32_nxv8i64(<vscale x 8 x i64>
; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(
@@ -1469,8 +1469,8 @@ define <vscale x 8 x i8> @intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
@@ -1502,8 +1502,8 @@ define <vscale x 16 x i8> @intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
@@ -1535,8 +1535,8 @@ define <vscale x 32 x i8> @intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
@@ -1632,8 +1632,8 @@ define <vscale x 4 x i16> @intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
@@ -1665,8 +1665,8 @@ define <vscale x 8 x i16> @intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
@@ -1698,8 +1698,8 @@ define <vscale x 16 x i16> @intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16(<vscale x 1
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
@@ -1763,8 +1763,8 @@ define <vscale x 2 x i32> @intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(
@@ -1796,8 +1796,8 @@ define <vscale x 4 x i32> @intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(
@@ -1829,8 +1829,8 @@ define <vscale x 8 x i32> @intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
index ec2705d0eb7de..2550b308ca039 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vor.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vor.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vor.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vor.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vor.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vor.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i6
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vor.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vor.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vor.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
index 7c670dd2341cd..de465855d7e6d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
@@ -892,8 +892,8 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vor.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -948,8 +948,8 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vor.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -1004,8 +1004,8 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vor.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
index 4a6cc0cf8a07d..5c08d547204d8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
@@ -1495,9 +1495,9 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscal
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v25, v0.t
+; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1521,9 +1521,9 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v25
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1599,9 +1599,9 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscal
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v26, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1625,9 +1625,9 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v26
+; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1703,9 +1703,9 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscal
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v28, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1729,9 +1729,9 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vor.vv v8, v8, v28
+; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index d383790954c12..64295ffc31f55 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -10,15 +10,15 @@ define <vscale x 1 x i8> @vpgather_nxv1i8(<vscale x 1 x i8*> %ptrs, <vscale x 1
; RV32-LABEL: vpgather_nxv1i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.gather.nxv1i8.nxv1p0i8(<vscale x 1 x i8*> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v
@@ -30,15 +30,15 @@ define <vscale x 2 x i8> @vpgather_nxv2i8(<vscale x 2 x i8*> %ptrs, <vscale x 2
; RV32-LABEL: vpgather_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v
@@ -48,17 +48,17 @@ define <vscale x 2 x i16> @vpgather_nxv2i8_sextload_nxv2i16(<vscale x 2 x i8*> %
; RV32-LABEL: vpgather_nxv2i8_sextload_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32-NEXT: vsext.vf2 v8, v25
+; RV32-NEXT: vsext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8_sextload_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64-NEXT: vsext.vf2 v8, v25
+; RV64-NEXT: vsext.vf2 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>
@@ -69,17 +69,17 @@ define <vscale x 2 x i16> @vpgather_nxv2i8_zextload_nxv2i16(<vscale x 2 x i8*> %
; RV32-LABEL: vpgather_nxv2i8_zextload_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32-NEXT: vzext.vf2 v8, v25
+; RV32-NEXT: vzext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8_zextload_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64-NEXT: vzext.vf2 v8, v25
+; RV64-NEXT: vzext.vf2 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = zext <vscale x 2 x i8> %v to <vscale x 2 x i16>
@@ -90,17 +90,17 @@ define <vscale x 2 x i32> @vpgather_nxv2i8_sextload_nxv2i32(<vscale x 2 x i8*> %
; RV32-LABEL: vpgather_nxv2i8_sextload_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vsext.vf4 v8, v25
+; RV32-NEXT: vsext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8_sextload_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vsext.vf4 v8, v25
+; RV64-NEXT: vsext.vf4 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = sext <vscale x 2 x i8> %v to <vscale x 2 x i32>
@@ -111,17 +111,17 @@ define <vscale x 2 x i32> @vpgather_nxv2i8_zextload_nxv2i32(<vscale x 2 x i8*> %
; RV32-LABEL: vpgather_nxv2i8_zextload_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vzext.vf4 v8, v25
+; RV32-NEXT: vzext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8_zextload_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vzext.vf4 v8, v25
+; RV64-NEXT: vzext.vf4 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = zext <vscale x 2 x i8> %v to <vscale x 2 x i32>
@@ -132,17 +132,17 @@ define <vscale x 2 x i64> @vpgather_nxv2i8_sextload_nxv2i64(<vscale x 2 x i8*> %
; RV32-LABEL: vpgather_nxv2i8_sextload_nxv2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vsext.vf8 v8, v25
+; RV32-NEXT: vsext.vf8 v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8_sextload_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT: vsext.vf8 v8, v25
+; RV64-NEXT: vsext.vf8 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = sext <vscale x 2 x i8> %v to <vscale x 2 x i64>
@@ -153,17 +153,17 @@ define <vscale x 2 x i64> @vpgather_nxv2i8_zextload_nxv2i64(<vscale x 2 x i8*> %
; RV32-LABEL: vpgather_nxv2i8_zextload_nxv2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vzext.vf8 v8, v25
+; RV32-NEXT: vzext.vf8 v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i8_zextload_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT: vzext.vf8 v8, v25
+; RV64-NEXT: vzext.vf8 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.gather.nxv2i8.nxv2p0i8(<vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = zext <vscale x 2 x i8> %v to <vscale x 2 x i64>
@@ -176,15 +176,15 @@ define <vscale x 4 x i8> @vpgather_nxv4i8(<vscale x 4 x i8*> %ptrs, <vscale x 4
; RV32-LABEL: vpgather_nxv4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv4i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.gather.nxv4i8.nxv4p0i8(<vscale x 4 x i8*> %ptrs, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v
@@ -194,15 +194,15 @@ define <vscale x 4 x i8> @vpgather_truemask_nxv4i8(<vscale x 4 x i8*> %ptrs, i32
; RV32-LABEL: vpgather_truemask_nxv4i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_nxv4i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -216,15 +216,15 @@ define <vscale x 8 x i8> @vpgather_nxv8i8(<vscale x 8 x i8*> %ptrs, <vscale x 8
; RV32-LABEL: vpgather_nxv8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv8i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v16, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v16
; RV64-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.gather.nxv8i8.nxv8p0i8(<vscale x 8 x i8*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v
@@ -234,9 +234,9 @@ define <vscale x 8 x i8> @vpgather_baseidx_nxv8i8(i8* %base, <vscale x 8 x i8> %
; RV32-LABEL: vpgather_baseidx_nxv8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
+; RV32-NEXT: vsext.vf4 v12, v8
; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i8:
@@ -257,15 +257,15 @@ define <vscale x 1 x i16> @vpgather_nxv1i16(<vscale x 1 x i16*> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv1i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0i16(<vscale x 1 x i16*> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v
@@ -277,15 +277,15 @@ define <vscale x 2 x i16> @vpgather_nxv2i16(<vscale x 2 x i16*> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0i16(<vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v
@@ -295,17 +295,17 @@ define <vscale x 2 x i32> @vpgather_nxv2i16_sextload_nxv2i32(<vscale x 2 x i16*>
; RV32-LABEL: vpgather_nxv2i16_sextload_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vsext.vf2 v8, v25
+; RV32-NEXT: vsext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i16_sextload_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vsext.vf2 v8, v25
+; RV64-NEXT: vsext.vf2 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0i16(<vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = sext <vscale x 2 x i16> %v to <vscale x 2 x i32>
@@ -316,17 +316,17 @@ define <vscale x 2 x i32> @vpgather_nxv2i16_zextload_nxv2i32(<vscale x 2 x i16*>
; RV32-LABEL: vpgather_nxv2i16_zextload_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV32-NEXT: vzext.vf2 v8, v25
+; RV32-NEXT: vzext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i16_zextload_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64-NEXT: vzext.vf2 v8, v25
+; RV64-NEXT: vzext.vf2 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0i16(<vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = zext <vscale x 2 x i16> %v to <vscale x 2 x i32>
@@ -337,17 +337,17 @@ define <vscale x 2 x i64> @vpgather_nxv2i16_sextload_nxv2i64(<vscale x 2 x i16*>
; RV32-LABEL: vpgather_nxv2i16_sextload_nxv2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vsext.vf4 v8, v25
+; RV32-NEXT: vsext.vf4 v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i16_sextload_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT: vsext.vf4 v8, v25
+; RV64-NEXT: vsext.vf4 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0i16(<vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = sext <vscale x 2 x i16> %v to <vscale x 2 x i64>
@@ -358,17 +358,17 @@ define <vscale x 2 x i64> @vpgather_nxv2i16_zextload_nxv2i64(<vscale x 2 x i16*>
; RV32-LABEL: vpgather_nxv2i16_zextload_nxv2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vzext.vf4 v8, v25
+; RV32-NEXT: vzext.vf4 v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i16_zextload_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT: vzext.vf4 v8, v25
+; RV64-NEXT: vzext.vf4 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.gather.nxv2i16.nxv2p0i16(<vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = zext <vscale x 2 x i16> %v to <vscale x 2 x i64>
@@ -381,15 +381,15 @@ define <vscale x 4 x i16> @vpgather_nxv4i16(<vscale x 4 x i16*> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv4i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.gather.nxv4i16.nxv4p0i16(<vscale x 4 x i16*> %ptrs, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v
@@ -399,15 +399,15 @@ define <vscale x 4 x i16> @vpgather_truemask_nxv4i16(<vscale x 4 x i16*> %ptrs,
; RV32-LABEL: vpgather_truemask_nxv4i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_nxv4i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -421,15 +421,15 @@ define <vscale x 8 x i16> @vpgather_nxv8i16(<vscale x 8 x i16*> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t
+; RV32-NEXT: vmv2r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv8i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v16, (zero), v8, v0.t
+; RV64-NEXT: vmv2r.v v8, v16
; RV64-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.gather.nxv8i16.nxv8p0i16(<vscale x 8 x i16*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v
@@ -439,10 +439,10 @@ define <vscale x 8 x i16> @vpgather_baseidx_nxv8i8_nxv8i16(i16* %base, <vscale x
; RV32-LABEL: vpgather_baseidx_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i8_nxv8i16:
@@ -462,10 +462,10 @@ define <vscale x 8 x i16> @vpgather_baseidx_sext_nxv8i8_nxv8i16(i16* %base, <vsc
; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i16:
@@ -486,10 +486,10 @@ define <vscale x 8 x i16> @vpgather_baseidx_zext_nxv8i8_nxv8i16(i16* %base, <vsc
; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
@@ -510,10 +510,10 @@ define <vscale x 8 x i16> @vpgather_baseidx_nxv8i16(i16* %base, <vscale x 8 x i1
; RV32-LABEL: vpgather_baseidx_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i16:
@@ -541,8 +541,8 @@ define <vscale x 1 x i32> @vpgather_nxv1i32(<vscale x 1 x i32*> %ptrs, <vscale x
; RV64-LABEL: vpgather_nxv1i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.gather.nxv1i32.nxv1p0i32(<vscale x 1 x i32*> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v
@@ -560,8 +560,8 @@ define <vscale x 2 x i32> @vpgather_nxv2i32(<vscale x 2 x i32*> %ptrs, <vscale x
; RV64-LABEL: vpgather_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.gather.nxv2i32.nxv2p0i32(<vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v
@@ -571,17 +571,17 @@ define <vscale x 2 x i64> @vpgather_nxv2i32_sextload_nxv2i64(<vscale x 2 x i32*>
; RV32-LABEL: vpgather_nxv2i32_sextload_nxv2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vsext.vf2 v8, v25
+; RV32-NEXT: vsext.vf2 v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i32_sextload_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT: vsext.vf2 v8, v25
+; RV64-NEXT: vsext.vf2 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.gather.nxv2i32.nxv2p0i32(<vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -592,17 +592,17 @@ define <vscale x 2 x i64> @vpgather_nxv2i32_zextload_nxv2i64(<vscale x 2 x i32*>
; RV32-LABEL: vpgather_nxv2i32_zextload_nxv2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vzext.vf2 v8, v25
+; RV32-NEXT: vzext.vf2 v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i32_zextload_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV64-NEXT: vzext.vf2 v8, v25
+; RV64-NEXT: vzext.vf2 v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.gather.nxv2i32.nxv2p0i32(<vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
%ev = zext <vscale x 2 x i32> %v to <vscale x 2 x i64>
@@ -621,8 +621,8 @@ define <vscale x 4 x i32> @vpgather_nxv4i32(<vscale x 4 x i32*> %ptrs, <vscale x
; RV64-LABEL: vpgather_nxv4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %ptrs, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v
@@ -638,8 +638,8 @@ define <vscale x 4 x i32> @vpgather_truemask_nxv4i32(<vscale x 4 x i32*> %ptrs,
; RV64-LABEL: vpgather_truemask_nxv4i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -659,8 +659,8 @@ define <vscale x 8 x i32> @vpgather_nxv8i32(<vscale x 8 x i32*> %ptrs, <vscale x
; RV64-LABEL: vpgather_nxv8i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; RV64-NEXT: vluxei64.v v28, (zero), v8, v0.t
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vluxei64.v v16, (zero), v8, v0.t
+; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.gather.nxv8i32.nxv8p0i32(<vscale x 8 x i32*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v
@@ -670,10 +670,10 @@ define <vscale x 8 x i32> @vpgather_baseidx_nxv8i8_nxv8i32(i32* %base, <vscale x
; RV32-LABEL: vpgather_baseidx_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i8_nxv8i32:
@@ -693,10 +693,10 @@ define <vscale x 8 x i32> @vpgather_baseidx_sext_nxv8i8_nxv8i32(i32* %base, <vsc
; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8i32:
@@ -717,10 +717,10 @@ define <vscale x 8 x i32> @vpgather_baseidx_zext_nxv8i8_nxv8i32(i32* %base, <vsc
; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
@@ -741,10 +741,10 @@ define <vscale x 8 x i32> @vpgather_baseidx_nxv8i16_nxv8i32(i32* %base, <vscale
; RV32-LABEL: vpgather_baseidx_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i16_nxv8i32:
@@ -764,10 +764,10 @@ define <vscale x 8 x i32> @vpgather_baseidx_sext_nxv8i16_nxv8i32(i32* %base, <vs
; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8i32:
@@ -788,10 +788,10 @@ define <vscale x 8 x i32> @vpgather_baseidx_zext_nxv8i16_nxv8i32(i32* %base, <vs
; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
@@ -812,9 +812,9 @@ define <vscale x 8 x i32> @vpgather_baseidx_nxv8i32(i32* %base, <vscale x 8 x i3
; RV32-LABEL: vpgather_baseidx_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 2
+; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i32:
@@ -836,8 +836,8 @@ define <vscale x 1 x i64> @vpgather_nxv1i64(<vscale x 1 x i64*> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv1i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1i64:
@@ -855,8 +855,8 @@ define <vscale x 2 x i64> @vpgather_nxv2i64(<vscale x 2 x i64*> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2i64:
@@ -874,8 +874,8 @@ define <vscale x 4 x i64> @vpgather_nxv4i64(<vscale x 4 x i64*> %ptrs, <vscale x
; RV32-LABEL: vpgather_nxv4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8, v0.t
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv4i64:
@@ -891,8 +891,8 @@ define <vscale x 4 x i64> @vpgather_truemask_nxv4i64(<vscale x 4 x i64*> %ptrs,
; RV32-LABEL: vpgather_truemask_nxv4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_nxv4i64:
@@ -929,10 +929,10 @@ define <vscale x 8 x i64> @vpgather_baseidx_nxv8i8_nxv8i64(i64* %base, <vscale x
; RV32-LABEL: vpgather_baseidx_nxv8i8_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v16, v12, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i8_nxv8i64:
@@ -982,10 +982,10 @@ define <vscale x 8 x i64> @vpgather_baseidx_nxv8i16_nxv8i64(i64* %base, <vscale
; RV32-LABEL: vpgather_baseidx_nxv8i16_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v16, v12, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i16_nxv8i64:
@@ -1035,9 +1035,9 @@ define <vscale x 8 x i64> @vpgather_baseidx_nxv8i32_nxv8i64(i64* %base, <vscale
; RV32-LABEL: vpgather_baseidx_nxv8i32_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 3
+; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i32_nxv8i64:
@@ -1102,15 +1102,15 @@ define <vscale x 1 x half> @vpgather_nxv1f16(<vscale x 1 x half*> %ptrs, <vscale
; RV32-LABEL: vpgather_nxv1f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.gather.nxv1f16.nxv1p0f16(<vscale x 1 x half*> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -1122,15 +1122,15 @@ define <vscale x 2 x half> @vpgather_nxv2f16(<vscale x 2 x half*> %ptrs, <vscale
; RV32-LABEL: vpgather_nxv2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.gather.nxv2f16.nxv2p0f16(<vscale x 2 x half*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -1142,15 +1142,15 @@ define <vscale x 4 x half> @vpgather_nxv4f16(<vscale x 4 x half*> %ptrs, <vscale
; RV32-LABEL: vpgather_nxv4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%v = call <vscale x 4 x half> @llvm.vp.gather.nxv4f16.nxv4p0f16(<vscale x 4 x half*> %ptrs, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x half> %v
@@ -1160,15 +1160,15 @@ define <vscale x 4 x half> @vpgather_truemask_nxv4f16(<vscale x 4 x half*> %ptrs
; RV32-LABEL: vpgather_truemask_nxv4f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v10, (zero), v8
+; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_nxv4f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv1r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -1182,15 +1182,15 @@ define <vscale x 8 x half> @vpgather_nxv8f16(<vscale x 8 x half*> %ptrs, <vscale
; RV32-LABEL: vpgather_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t
+; RV32-NEXT: vmv2r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv8f16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v16, (zero), v8, v0.t
+; RV64-NEXT: vmv2r.v v8, v16
; RV64-NEXT: ret
%v = call <vscale x 8 x half> @llvm.vp.gather.nxv8f16.nxv8p0f16(<vscale x 8 x half*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x half> %v
@@ -1200,10 +1200,10 @@ define <vscale x 8 x half> @vpgather_baseidx_nxv8i8_nxv8f16(half* %base, <vscale
; RV32-LABEL: vpgather_baseidx_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i8_nxv8f16:
@@ -1223,10 +1223,10 @@ define <vscale x 8 x half> @vpgather_baseidx_sext_nxv8i8_nxv8f16(half* %base, <v
; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f16:
@@ -1247,10 +1247,10 @@ define <vscale x 8 x half> @vpgather_baseidx_zext_nxv8i8_nxv8f16(half* %base, <v
; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
@@ -1271,10 +1271,10 @@ define <vscale x 8 x half> @vpgather_baseidx_nxv8f16(half* %base, <vscale x 8 x
; RV32-LABEL: vpgather_baseidx_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8f16:
@@ -1302,8 +1302,8 @@ define <vscale x 1 x float> @vpgather_nxv1f32(<vscale x 1 x float*> %ptrs, <vsca
; RV64-LABEL: vpgather_nxv1f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
%v = call <vscale x 1 x float> @llvm.vp.gather.nxv1f32.nxv1p0f32(<vscale x 1 x float*> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x float> %v
@@ -1321,8 +1321,8 @@ define <vscale x 2 x float> @vpgather_nxv2f32(<vscale x 2 x float*> %ptrs, <vsca
; RV64-LABEL: vpgather_nxv2f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t
-; RV64-NEXT: vmv1r.v v8, v25
+; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t
+; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret
%v = call <vscale x 2 x float> @llvm.vp.gather.nxv2f32.nxv2p0f32(<vscale x 2 x float*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x float> %v
@@ -1340,8 +1340,8 @@ define <vscale x 4 x float> @vpgather_nxv4f32(<vscale x 4 x float*> %ptrs, <vsca
; RV64-LABEL: vpgather_nxv4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%v = call <vscale x 4 x float> @llvm.vp.gather.nxv4f32.nxv4p0f32(<vscale x 4 x float*> %ptrs, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x float> %v
@@ -1357,8 +1357,8 @@ define <vscale x 4 x float> @vpgather_truemask_nxv4f32(<vscale x 4 x float*> %pt
; RV64-LABEL: vpgather_truemask_nxv4f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; RV64-NEXT: vluxei64.v v26, (zero), v8
-; RV64-NEXT: vmv2r.v v8, v26
+; RV64-NEXT: vluxei64.v v12, (zero), v8
+; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret
%mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
%mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -1378,8 +1378,8 @@ define <vscale x 8 x float> @vpgather_nxv8f32(<vscale x 8 x float*> %ptrs, <vsca
; RV64-LABEL: vpgather_nxv8f32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; RV64-NEXT: vluxei64.v v28, (zero), v8, v0.t
-; RV64-NEXT: vmv4r.v v8, v28
+; RV64-NEXT: vluxei64.v v16, (zero), v8, v0.t
+; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: ret
%v = call <vscale x 8 x float> @llvm.vp.gather.nxv8f32.nxv8p0f32(<vscale x 8 x float*> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x float> %v
@@ -1389,10 +1389,10 @@ define <vscale x 8 x float> @vpgather_baseidx_nxv8i8_nxv8f32(float* %base, <vsca
; RV32-LABEL: vpgather_baseidx_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i8_nxv8f32:
@@ -1412,10 +1412,10 @@ define <vscale x 8 x float> @vpgather_baseidx_sext_nxv8i8_nxv8f32(float* %base,
; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f32:
@@ -1436,10 +1436,10 @@ define <vscale x 8 x float> @vpgather_baseidx_zext_nxv8i8_nxv8f32(float* %base,
; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
@@ -1460,10 +1460,10 @@ define <vscale x 8 x float> @vpgather_baseidx_nxv8i16_nxv8f32(float* %base, <vsc
; RV32-LABEL: vpgather_baseidx_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i16_nxv8f32:
@@ -1483,10 +1483,10 @@ define <vscale x 8 x float> @vpgather_baseidx_sext_nxv8i16_nxv8f32(float* %base,
; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f32:
@@ -1507,10 +1507,10 @@ define <vscale x 8 x float> @vpgather_baseidx_zext_nxv8i16_nxv8f32(float* %base,
; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v8, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
@@ -1531,9 +1531,9 @@ define <vscale x 8 x float> @vpgather_baseidx_nxv8f32(float* %base, <vscale x 8
; RV32-LABEL: vpgather_baseidx_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 2
+; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8f32:
@@ -1555,8 +1555,8 @@ define <vscale x 1 x double> @vpgather_nxv1f64(<vscale x 1 x double*> %ptrs, <vs
; RV32-LABEL: vpgather_nxv1f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t
-; RV32-NEXT: vmv1r.v v8, v25
+; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t
+; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv1f64:
@@ -1574,8 +1574,8 @@ define <vscale x 2 x double> @vpgather_nxv2f64(<vscale x 2 x double*> %ptrs, <vs
; RV32-LABEL: vpgather_nxv2f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t
-; RV32-NEXT: vmv2r.v v8, v26
+; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t
+; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv2f64:
@@ -1593,8 +1593,8 @@ define <vscale x 4 x double> @vpgather_nxv4f64(<vscale x 4 x double*> %ptrs, <vs
; RV32-LABEL: vpgather_nxv4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8, v0.t
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_nxv4f64:
@@ -1610,8 +1610,8 @@ define <vscale x 4 x double> @vpgather_truemask_nxv4f64(<vscale x 4 x double*> %
; RV32-LABEL: vpgather_truemask_nxv4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; RV32-NEXT: vluxei32.v v28, (zero), v8
-; RV32-NEXT: vmv4r.v v8, v28
+; RV32-NEXT: vluxei32.v v12, (zero), v8
+; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_truemask_nxv4f64:
@@ -1648,10 +1648,10 @@ define <vscale x 8 x double> @vpgather_baseidx_nxv8i8_nxv8f64(double* %base, <vs
; RV32-LABEL: vpgather_baseidx_nxv8i8_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v12, v8
+; RV32-NEXT: vsll.vi v16, v12, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i8_nxv8f64:
@@ -1701,10 +1701,10 @@ define <vscale x 8 x double> @vpgather_baseidx_nxv8i16_nxv8f64(double* %base, <v
; RV32-LABEL: vpgather_baseidx_nxv8i16_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v8
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v12, v8
+; RV32-NEXT: vsll.vi v16, v12, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i16_nxv8f64:
@@ -1754,9 +1754,9 @@ define <vscale x 8 x double> @vpgather_baseidx_nxv8i32_nxv8f64(double* %base, <v
; RV32-LABEL: vpgather_baseidx_nxv8i32_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v8, 3
+; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpgather_baseidx_nxv8i32_nxv8f64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll
index 76e2b9ac768cb..9bc48ad59ef06 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll
@@ -27,10 +27,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv1i1(
define i32 @intrinsic_vpopc_mask_m_i32_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vpopc.mask.i32.nxv1i1(
@@ -67,10 +67,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv2i1(
define i32 @intrinsic_vpopc_mask_m_i32_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vpopc.mask.i32.nxv2i1(
@@ -107,10 +107,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv4i1(
define i32 @intrinsic_vpopc_mask_m_i32_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vpopc.mask.i32.nxv4i1(
@@ -147,10 +147,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv8i1(
define i32 @intrinsic_vpopc_mask_m_i32_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vpopc.mask.i32.nxv8i1(
@@ -187,10 +187,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv16i1(
define i32 @intrinsic_vpopc_mask_m_i32_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vpopc.mask.i32.nxv16i1(
@@ -227,10 +227,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv32i1(
define i32 @intrinsic_vpopc_mask_m_i32_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vpopc.mask.i32.nxv32i1(
@@ -267,10 +267,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv64i1(
define i32 @intrinsic_vpopc_mask_m_i32_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vpopc.mask.i32.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll
index a29d7b3660f02..10c72e381fb94 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll
@@ -27,10 +27,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv1i1(
define i64 @intrinsic_vpopc_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv1i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vpopc.mask.i64.nxv1i1(
@@ -67,10 +67,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv2i1(
define i64 @intrinsic_vpopc_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv2i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vpopc.mask.i64.nxv2i1(
@@ -107,10 +107,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv4i1(
define i64 @intrinsic_vpopc_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv4i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vpopc.mask.i64.nxv4i1(
@@ -147,10 +147,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv8i1(
define i64 @intrinsic_vpopc_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv8i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vpopc.mask.i64.nxv8i1(
@@ -187,10 +187,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv16i1(
define i64 @intrinsic_vpopc_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv16i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vpopc.mask.i64.nxv16i1(
@@ -227,10 +227,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv32i1(
define i64 @intrinsic_vpopc_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv32i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vpopc.mask.i64.nxv32i1(
@@ -267,10 +267,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv64i1(
define i64 @intrinsic_vpopc_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv64i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a0, v25, v0.t
+; CHECK-NEXT: vpopc.m a0, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vpopc.mask.i64.nxv64i1(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
index c041c3411281d..c0db7f57a190f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
@@ -44,17 +44,17 @@ define void @vpscatter_nxv2i16_truncstore_nxv2i8(<vscale x 2 x i16> %val, <vscal
; RV32-LABEL: vpscatter_nxv2i16_truncstore_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_nxv2i16_truncstore_nxv2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i16> %val to <vscale x 2 x i8>
call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
@@ -65,21 +65,21 @@ define void @vpscatter_nxv2i32_truncstore_nxv2i8(<vscale x 2 x i32> %val, <vscal
; RV32-LABEL: vpscatter_nxv2i32_truncstore_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_nxv2i32_truncstore_nxv2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i8>
call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
@@ -90,25 +90,25 @@ define void @vpscatter_nxv2i64_truncstore_nxv2i8(<vscale x 2 x i64> %val, <vscal
; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v11, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v11, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v12, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v12, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8>
call void @llvm.vp.scatter.nxv2i8.nxv2p0i8(<vscale x 2 x i8> %tval, <vscale x 2 x i8*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
@@ -173,9 +173,9 @@ define void @vpscatter_baseidx_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale
; RV32-LABEL: vpscatter_baseidx_nxv8i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v9
+; RV32-NEXT: vsext.vf4 v12, v9
; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i8:
@@ -230,17 +230,17 @@ define void @vpscatter_nxv2i32_truncstore_nxv2i16(<vscale x 2 x i32> %val, <vsca
; RV32-LABEL: vpscatter_nxv2i32_truncstore_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_nxv2i32_truncstore_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i32> %val to <vscale x 2 x i16>
call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
@@ -251,21 +251,21 @@ define void @vpscatter_nxv2i64_truncstore_nxv2i16(<vscale x 2 x i64> %val, <vsca
; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v11, v8, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v25, 0
+; RV32-NEXT: vnsrl.wi v8, v11, 0
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
+; RV32-NEXT: vsoxei32.v v8, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v12, v8, 0
; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v25, 0
+; RV64-NEXT: vnsrl.wi v8, v12, 0
; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16>
call void @llvm.vp.scatter.nxv2i16.nxv2p0i16(<vscale x 2 x i16> %tval, <vscale x 2 x i16*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
@@ -330,10 +330,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16* %bas
; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8i16:
@@ -353,10 +353,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16*
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i16:
@@ -377,10 +377,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16*
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
@@ -401,10 +401,10 @@ define void @vpscatter_baseidx_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vsc
; RV32-LABEL: vpscatter_baseidx_nxv8i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i16:
@@ -460,17 +460,17 @@ define void @vpscatter_nxv2i64_truncstore_nxv2i32(<vscale x 2 x i64> %val, <vsca
; RV32-LABEL: vpscatter_nxv2i64_truncstore_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT: vnsrl.wi v25, v8, 0
+; RV32-NEXT: vnsrl.wi v11, v8, 0
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV32-NEXT: vsoxei32.v v25, (zero), v10, v0.t
+; RV32-NEXT: vsoxei32.v v11, (zero), v10, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_nxv2i64_truncstore_nxv2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT: vnsrl.wi v25, v8, 0
+; RV64-NEXT: vnsrl.wi v12, v8, 0
; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; RV64-NEXT: vsoxei64.v v25, (zero), v10, v0.t
+; RV64-NEXT: vsoxei64.v v12, (zero), v10, v0.t
; RV64-NEXT: ret
%tval = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32>
call void @llvm.vp.scatter.nxv2i32.nxv2p0i32(<vscale x 2 x i32> %tval, <vscale x 2 x i32*> %ptrs, <vscale x 2 x i1> %m, i32 %evl)
@@ -535,10 +535,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, i32* %bas
; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8i32:
@@ -558,10 +558,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, i32*
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i32:
@@ -582,10 +582,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, i32*
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
@@ -606,10 +606,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, i32* %ba
; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8i32:
@@ -629,10 +629,10 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, i32
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i32:
@@ -653,10 +653,10 @@ define void @vpscatter_baseidx_zext_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, i32
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
@@ -677,9 +677,9 @@ define void @vpscatter_baseidx_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vsc
; RV32-LABEL: vpscatter_baseidx_nxv8i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v12, 2
+; RV32-NEXT: vsll.vi v12, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i32:
@@ -789,10 +789,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, i64* %bas
; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8i64:
@@ -842,10 +842,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, i64* %ba
; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8i64:
@@ -895,9 +895,9 @@ define void @vpscatter_baseidx_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, i64* %ba
; RV32-LABEL: vpscatter_baseidx_nxv8i32_nxv8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v16, 3
+; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i32_nxv8i64:
@@ -1050,10 +1050,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8f16(<vscale x 8 x half> %val, half* %b
; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8f16:
@@ -1073,10 +1073,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, hal
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f16:
@@ -1097,10 +1097,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, hal
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vzext.vf4 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
@@ -1121,10 +1121,10 @@ define void @vpscatter_baseidx_nxv8f16(<vscale x 8 x half> %val, half* %base, <v
; RV32-LABEL: vpscatter_baseidx_nxv8f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v10
-; RV32-NEXT: vadd.vv v28, v28, v28
+; RV32-NEXT: vsext.vf2 v12, v10
+; RV32-NEXT: vadd.vv v12, v12, v12
; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8f16:
@@ -1234,10 +1234,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8f32(<vscale x 8 x float> %val, float*
; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8f32:
@@ -1257,10 +1257,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f32(<vscale x 8 x float> %val, fl
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f32:
@@ -1281,10 +1281,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8f32(<vscale x 8 x float> %val, fl
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf4 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf4 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
@@ -1305,10 +1305,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8f32(<vscale x 8 x float> %val, float*
; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8f32:
@@ -1328,10 +1328,10 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8f32(<vscale x 8 x float> %val, f
; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vsext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f32:
@@ -1352,10 +1352,10 @@ define void @vpscatter_baseidx_zext_nxv8i16_nxv8f32(<vscale x 8 x float> %val, f
; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vzext.vf2 v28, v12
-; RV32-NEXT: vsll.vi v28, v28, 2
+; RV32-NEXT: vzext.vf2 v16, v12
+; RV32-NEXT: vsll.vi v12, v16, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
@@ -1376,9 +1376,9 @@ define void @vpscatter_baseidx_nxv8f32(<vscale x 8 x float> %val, float* %base,
; RV32-LABEL: vpscatter_baseidx_nxv8f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v12, 2
+; RV32-NEXT: vsll.vi v12, v12, 2
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8f32:
@@ -1488,10 +1488,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8f64(<vscale x 8 x double> %val, double
; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf4 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf4 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8f64:
@@ -1541,10 +1541,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8f64(<vscale x 8 x double> %val, doubl
; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsext.vf2 v28, v16
-; RV32-NEXT: vsll.vi v28, v28, 3
+; RV32-NEXT: vsext.vf2 v20, v16
+; RV32-NEXT: vsll.vi v16, v20, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8f64:
@@ -1594,9 +1594,9 @@ define void @vpscatter_baseidx_nxv8i32_nxv8f64(<vscale x 8 x double> %val, doubl
; RV32-LABEL: vpscatter_baseidx_nxv8i32_nxv8f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu
-; RV32-NEXT: vsll.vi v28, v16, 3
+; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t
+; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vpscatter_baseidx_nxv8i32_nxv8f64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
index 07b224f38f155..5a27b4384c1f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
@@ -12,10 +12,10 @@ define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
@@ -26,10 +26,10 @@ define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
ret half %red
@@ -43,10 +43,10 @@ define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
@@ -57,10 +57,10 @@ define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
ret half %red
@@ -74,9 +74,9 @@ define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
@@ -87,9 +87,9 @@ define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
ret half %red
@@ -103,10 +103,10 @@ define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
@@ -117,10 +117,10 @@ define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red
@@ -134,9 +134,9 @@ define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
@@ -147,9 +147,9 @@ define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red
@@ -163,10 +163,10 @@ define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
@@ -177,10 +177,10 @@ define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
ret float %red
@@ -194,9 +194,9 @@ define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredusum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
@@ -207,9 +207,9 @@ define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfredosum.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red
@@ -223,10 +223,10 @@ define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
@@ -237,10 +237,10 @@ define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
ret double %red
@@ -254,10 +254,10 @@ define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
; CHECK-NEXT: lui a0, %hi(.LCPI16_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI16_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v12, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s ft0, v25
+; CHECK-NEXT: vfredusum.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
@@ -268,10 +268,10 @@ define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
ret double %red
@@ -285,10 +285,10 @@ define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI18_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI18_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
ret half %red
@@ -300,10 +300,10 @@ define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
; CHECK-NEXT: lui a0, %hi(.LCPI19_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI19_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
ret half %red
@@ -315,10 +315,10 @@ define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
; CHECK-NEXT: lui a0, %hi(.LCPI20_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI20_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
ret half %red
@@ -332,10 +332,10 @@ define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI21_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI21_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v)
ret half %red
@@ -349,9 +349,9 @@ define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI22_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI22_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %v)
ret half %red
@@ -367,10 +367,10 @@ define half @vreduce_fmin_nxv64f16(<vscale x 64 x half> %v) {
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v)
ret half %red
@@ -384,10 +384,10 @@ define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI24_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI24_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
ret float %red
@@ -399,10 +399,10 @@ define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI25_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI25_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
ret float %red
@@ -414,10 +414,10 @@ define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI26_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI26_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
ret float %red
@@ -431,9 +431,9 @@ define float @vreduce_fmin_nxv2f32(<vscale x 2 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI27_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI27_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %v)
ret float %red
@@ -447,10 +447,10 @@ define float @vreduce_fmin_nxv4f32(<vscale x 4 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI28_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI28_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
ret float %red
@@ -466,10 +466,10 @@ define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) {
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v)
ret float %red
@@ -483,9 +483,9 @@ define double @vreduce_fmin_nxv1f64(<vscale x 1 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI30_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI30_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
ret double %red
@@ -497,9 +497,9 @@ define double @vreduce_fmin_nxv1f64_nonans(<vscale x 1 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI31_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
ret double %red
@@ -511,9 +511,9 @@ define double @vreduce_fmin_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI32_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI32_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmin.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
ret double %red
@@ -527,10 +527,10 @@ define double @vreduce_fmin_nxv2f64(<vscale x 2 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI33_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI33_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v)
ret double %red
@@ -544,10 +544,10 @@ define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI34_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI34_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v12, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
ret double %red
@@ -563,10 +563,10 @@ define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) {
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfredmin.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmin.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v)
ret double %red
@@ -580,10 +580,10 @@ define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI36_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI36_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
ret half %red
@@ -595,10 +595,10 @@ define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
; CHECK-NEXT: lui a0, %hi(.LCPI37_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI37_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
ret half %red
@@ -610,10 +610,10 @@ define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
; CHECK-NEXT: lui a0, %hi(.LCPI38_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI38_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
ret half %red
@@ -627,10 +627,10 @@ define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI39_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI39_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v)
ret half %red
@@ -644,9 +644,9 @@ define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI40_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI40_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %v)
ret half %red
@@ -662,10 +662,10 @@ define half @vreduce_fmax_nxv64f16(<vscale x 64 x half> %v) {
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v)
ret half %red
@@ -679,10 +679,10 @@ define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI42_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI42_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
ret float %red
@@ -694,10 +694,10 @@ define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI43_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI43_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
ret float %red
@@ -709,10 +709,10 @@ define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI44_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI44_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v9, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
ret float %red
@@ -726,9 +726,9 @@ define float @vreduce_fmax_nxv2f32(<vscale x 2 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI45_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI45_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %v)
ret float %red
@@ -742,10 +742,10 @@ define float @vreduce_fmax_nxv4f32(<vscale x 4 x float> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI46_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
ret float %red
@@ -761,10 +761,10 @@ define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) {
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v)
ret float %red
@@ -778,9 +778,9 @@ define double @vreduce_fmax_nxv1f64(<vscale x 1 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI48_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI48_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
ret double %red
@@ -792,9 +792,9 @@ define double @vreduce_fmax_nxv1f64_nonans(<vscale x 1 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI49_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI49_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
ret double %red
@@ -806,9 +806,9 @@ define double @vreduce_fmax_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI50_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI50_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfmv.v.f v9, ft0
+; CHECK-NEXT: vfredmax.vs v8, v8, v9
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
ret double %red
@@ -822,10 +822,10 @@ define double @vreduce_fmax_nxv2f64(<vscale x 2 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI51_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI51_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v10, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v10
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v)
ret double %red
@@ -839,10 +839,10 @@ define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) {
; CHECK-NEXT: lui a0, %hi(.LCPI52_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI52_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v12, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v12
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
ret double %red
@@ -858,10 +858,10 @@ define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) {
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, ft0
+; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vfredmax.vs v25, v8, v25
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredmax.vs v8, v8, v16
+; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)
ret double %red
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
index 588c97231504d..74861743998c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -10,10 +10,10 @@ define half @vpreduce_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1
; CHECK-LABEL: vpreduce_fadd_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
ret half %r
@@ -23,10 +23,10 @@ define half @vpreduce_ord_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale
; CHECK-LABEL: vpreduce_ord_fadd_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
ret half %r
@@ -38,10 +38,10 @@ define half @vpreduce_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2
; CHECK-LABEL: vpreduce_fadd_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)
ret half %r
@@ -51,10 +51,10 @@ define half @vpreduce_ord_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale
; CHECK-LABEL: vpreduce_ord_fadd_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)
ret half %r
@@ -66,10 +66,10 @@ define half @vpreduce_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4
; CHECK-LABEL: vpreduce_fadd_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)
ret half %r
@@ -79,10 +79,10 @@ define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale
; CHECK-LABEL: vpreduce_ord_fadd_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)
ret half %r
@@ -94,10 +94,10 @@ define float @vpreduce_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x
; CHECK-LABEL: vpreduce_fadd_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)
ret float %r
@@ -107,10 +107,10 @@ define float @vpreduce_ord_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vsca
; CHECK-LABEL: vpreduce_ord_fadd_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)
ret float %r
@@ -122,10 +122,10 @@ define float @vpreduce_fadd_nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x
; CHECK-LABEL: vpreduce_fadd_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 %evl)
ret float %r
@@ -135,10 +135,10 @@ define float @vpreduce_ord_fadd_nxv2f32(float %s, <vscale x 2 x float> %v, <vsca
; CHECK-LABEL: vpreduce_ord_fadd_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 %evl)
ret float %r
@@ -150,10 +150,10 @@ define float @vpreduce_fadd_nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x
; CHECK-LABEL: vpreduce_fadd_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 %evl)
ret float %r
@@ -163,10 +163,10 @@ define float @vpreduce_ord_fadd_nxv4f32(float %s, <vscale x 4 x float> %v, <vsca
; CHECK-LABEL: vpreduce_ord_fadd_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 %evl)
ret float %r
@@ -178,10 +178,10 @@ define double @vpreduce_fadd_nxv1f64(double %s, <vscale x 1 x double> %v, <vscal
; CHECK-LABEL: vpreduce_fadd_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call reassoc double @llvm.vp.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 %evl)
ret double %r
@@ -191,10 +191,10 @@ define double @vpreduce_ord_fadd_nxv1f64(double %s, <vscale x 1 x double> %v, <v
; CHECK-LABEL: vpreduce_ord_fadd_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%r = call double @llvm.vp.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 %evl)
ret double %r
@@ -206,10 +206,10 @@ define double @vpreduce_fadd_nxv2f64(double %s, <vscale x 2 x double> %v, <vscal
; CHECK-LABEL: vpreduce_fadd_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%r = call reassoc double @llvm.vp.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 %evl)
ret double %r
@@ -219,10 +219,10 @@ define double @vpreduce_ord_fadd_nxv2f64(double %s, <vscale x 2 x double> %v, <v
; CHECK-LABEL: vpreduce_ord_fadd_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%r = call double @llvm.vp.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 %evl)
ret double %r
@@ -234,10 +234,10 @@ define double @vpreduce_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscal
; CHECK-LABEL: vpreduce_fadd_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v12, v8, v12, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v12
; CHECK-NEXT: ret
%r = call reassoc double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)
ret double %r
@@ -247,10 +247,10 @@ define double @vpreduce_ord_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <v
; CHECK-LABEL: vpreduce_ord_fadd_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v25, fa0
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v12, v8, v12, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v12
; CHECK-NEXT: ret
%r = call double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)
ret double %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
index db0a336814359..8709adddce5c5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
@@ -7,10 +7,10 @@ define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -22,10 +22,10 @@ define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -38,10 +38,10 @@ define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -53,10 +53,10 @@ define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -69,10 +69,10 @@ define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -84,10 +84,10 @@ define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -99,10 +99,10 @@ define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -114,10 +114,10 @@ define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -129,10 +129,10 @@ define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -144,10 +144,10 @@ define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -160,10 +160,10 @@ define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -175,10 +175,10 @@ define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -191,10 +191,10 @@ define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -206,10 +206,10 @@ define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -221,10 +221,10 @@ define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -236,10 +236,10 @@ define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -251,10 +251,10 @@ define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -266,10 +266,10 @@ define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -282,10 +282,10 @@ define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -297,10 +297,10 @@ define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -313,10 +313,10 @@ define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -328,10 +328,10 @@ define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -343,10 +343,10 @@ define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -358,10 +358,10 @@ define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -373,10 +373,10 @@ define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -388,10 +388,10 @@ define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -404,10 +404,10 @@ define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -419,10 +419,10 @@ define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -436,10 +436,10 @@ define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -451,10 +451,10 @@ define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -466,10 +466,10 @@ define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -481,10 +481,10 @@ define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -496,10 +496,10 @@ define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -511,10 +511,10 @@ define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -527,10 +527,10 @@ define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -542,10 +542,10 @@ define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -559,10 +559,10 @@ define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -574,10 +574,10 @@ define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -589,10 +589,10 @@ define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -604,10 +604,10 @@ define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -619,9 +619,9 @@ define signext i16 @vreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -633,9 +633,9 @@ define signext i16 @vreduce_umax_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -648,9 +648,9 @@ define signext i16 @vreduce_smax_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -662,9 +662,9 @@ define signext i16 @vreduce_umin_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -678,9 +678,9 @@ define signext i16 @vreduce_smin_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -692,9 +692,9 @@ define signext i16 @vreduce_and_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -706,9 +706,9 @@ define signext i16 @vreduce_or_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -720,9 +720,9 @@ define signext i16 @vreduce_xor_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -734,10 +734,10 @@ define i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -749,10 +749,10 @@ define i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -765,10 +765,10 @@ define i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -780,10 +780,10 @@ define i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -797,10 +797,10 @@ define i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -812,10 +812,10 @@ define i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -827,10 +827,10 @@ define i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -842,10 +842,10 @@ define i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -857,9 +857,9 @@ define i32 @vreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -871,9 +871,9 @@ define i32 @vreduce_umax_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -886,9 +886,9 @@ define i32 @vreduce_smax_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -900,9 +900,9 @@ define i32 @vreduce_umin_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -916,9 +916,9 @@ define i32 @vreduce_smin_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -930,9 +930,9 @@ define i32 @vreduce_and_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -944,9 +944,9 @@ define i32 @vreduce_or_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -958,9 +958,9 @@ define i32 @vreduce_xor_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -972,10 +972,10 @@ define i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -987,10 +987,10 @@ define i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1003,10 +1003,10 @@ define i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1018,10 +1018,10 @@ define i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1035,10 +1035,10 @@ define i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1050,10 +1050,10 @@ define i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1065,10 +1065,10 @@ define i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1080,10 +1080,10 @@ define i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1095,13 +1095,13 @@ define i64 @vreduce_add_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_add_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1113,13 +1113,13 @@ define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1137,13 +1137,13 @@ define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: sw zero, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)
@@ -1156,13 +1156,13 @@ define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1182,13 +1182,13 @@ define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
@@ -1201,13 +1201,13 @@ define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_and_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1219,13 +1219,13 @@ define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_or_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1237,13 +1237,13 @@ define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1255,14 +1255,14 @@ define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_add_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1274,14 +1274,14 @@ define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1299,14 +1299,14 @@ define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: sw zero, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
@@ -1319,14 +1319,14 @@ define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1346,14 +1346,14 @@ define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
@@ -1366,14 +1366,14 @@ define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_and_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1385,14 +1385,14 @@ define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_or_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1404,14 +1404,14 @@ define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1423,14 +1423,14 @@ define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_add_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1442,14 +1442,14 @@ define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1467,14 +1467,14 @@ define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: sw zero, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
@@ -1487,14 +1487,14 @@ define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1514,14 +1514,14 @@ define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
@@ -1534,14 +1534,14 @@ define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_and_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1553,14 +1553,14 @@ define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_or_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1572,14 +1572,14 @@ define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vsrl.vx v25, v25, a1
-; CHECK-NEXT: vmv.x.s a1, v25
+; CHECK-NEXT: vsrl.vx v8, v8, a1
+; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
index be7b735f4a28e..fa4d650ab710a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
@@ -7,10 +7,10 @@ define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -22,10 +22,10 @@ define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -38,10 +38,10 @@ define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -53,10 +53,10 @@ define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -69,10 +69,10 @@ define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -84,10 +84,10 @@ define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -99,10 +99,10 @@ define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -114,10 +114,10 @@ define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)
ret i8 %red
@@ -129,10 +129,10 @@ define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -144,10 +144,10 @@ define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -160,10 +160,10 @@ define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -175,10 +175,10 @@ define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -191,10 +191,10 @@ define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -206,10 +206,10 @@ define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -221,10 +221,10 @@ define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -236,10 +236,10 @@ define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)
ret i8 %red
@@ -251,10 +251,10 @@ define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -266,10 +266,10 @@ define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -282,10 +282,10 @@ define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -128
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -297,10 +297,10 @@ define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -313,10 +313,10 @@ define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 127
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -328,10 +328,10 @@ define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -343,10 +343,10 @@ define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -358,10 +358,10 @@ define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)
ret i8 %red
@@ -373,10 +373,10 @@ define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -388,10 +388,10 @@ define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -404,10 +404,10 @@ define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -419,10 +419,10 @@ define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -436,10 +436,10 @@ define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -451,10 +451,10 @@ define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -466,10 +466,10 @@ define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -481,10 +481,10 @@ define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)
ret i16 %red
@@ -496,10 +496,10 @@ define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -511,10 +511,10 @@ define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -527,10 +527,10 @@ define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -542,10 +542,10 @@ define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -559,10 +559,10 @@ define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -574,10 +574,10 @@ define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -589,10 +589,10 @@ define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -604,10 +604,10 @@ define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)
ret i16 %red
@@ -619,9 +619,9 @@ define signext i16 @vreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -633,9 +633,9 @@ define signext i16 @vreduce_umax_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -648,9 +648,9 @@ define signext i16 @vreduce_smax_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -662,9 +662,9 @@ define signext i16 @vreduce_umin_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -678,9 +678,9 @@ define signext i16 @vreduce_smin_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -692,9 +692,9 @@ define signext i16 @vreduce_and_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -706,9 +706,9 @@ define signext i16 @vreduce_or_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -720,9 +720,9 @@ define signext i16 @vreduce_xor_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16> %v)
ret i16 %red
@@ -734,10 +734,10 @@ define signext i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -749,10 +749,10 @@ define signext i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -765,10 +765,10 @@ define signext i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -780,10 +780,10 @@ define signext i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -797,10 +797,10 @@ define signext i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -812,10 +812,10 @@ define signext i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v9, -1
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -827,10 +827,10 @@ define signext i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -842,10 +842,10 @@ define signext i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)
ret i32 %red
@@ -857,9 +857,9 @@ define signext i32 @vreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -871,9 +871,9 @@ define signext i32 @vreduce_umax_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -886,9 +886,9 @@ define signext i32 @vreduce_smax_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -900,9 +900,9 @@ define signext i32 @vreduce_umin_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -916,9 +916,9 @@ define signext i32 @vreduce_smin_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -930,9 +930,9 @@ define signext i32 @vreduce_and_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -944,9 +944,9 @@ define signext i32 @vreduce_or_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -958,9 +958,9 @@ define signext i32 @vreduce_xor_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %v)
ret i32 %red
@@ -972,10 +972,10 @@ define signext i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -987,10 +987,10 @@ define signext i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1003,10 +1003,10 @@ define signext i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1018,10 +1018,10 @@ define signext i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1035,10 +1035,10 @@ define signext i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1050,10 +1050,10 @@ define signext i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1065,10 +1065,10 @@ define signext i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1080,10 +1080,10 @@ define signext i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
ret i32 %red
@@ -1095,9 +1095,9 @@ define i64 @vreduce_add_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_add_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredsum.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1109,9 +1109,9 @@ define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredmaxu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1125,9 +1125,9 @@ define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmax.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1139,9 +1139,9 @@ define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredminu.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1155,9 +1155,9 @@ define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vredmin.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1169,9 +1169,9 @@ define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_and_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, -1
+; CHECK-NEXT: vredand.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1183,9 +1183,9 @@ define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_or_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1197,9 +1197,9 @@ define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red
@@ -1211,10 +1211,10 @@ define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_add_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1226,10 +1226,10 @@ define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1243,10 +1243,10 @@ define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1258,10 +1258,10 @@ define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1275,10 +1275,10 @@ define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1290,10 +1290,10 @@ define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_and_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v10, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1305,10 +1305,10 @@ define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_or_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1320,10 +1320,10 @@ define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
ret i64 %red
@@ -1335,10 +1335,10 @@ define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_add_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1350,10 +1350,10 @@ define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1367,10 +1367,10 @@ define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1382,10 +1382,10 @@ define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1399,10 +1399,10 @@ define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1414,10 +1414,10 @@ define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_and_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, -1
+; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1429,10 +1429,10 @@ define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_or_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
@@ -1444,10 +1444,10 @@ define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v25, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v8, v8, v12
+; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
ret i64 %red
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index b190d66fa9753..c67ca4e208794 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -10,10 +10,10 @@ define signext i8 @vpreduce_add_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_add_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.add.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -26,10 +26,10 @@ define signext i8 @vpreduce_umax_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umax.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -41,10 +41,10 @@ define signext i8 @vpreduce_smax_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vs
; CHECK-LABEL: vpreduce_smax_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smax.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -57,10 +57,10 @@ define signext i8 @vpreduce_umin_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umin.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -72,10 +72,10 @@ define signext i8 @vpreduce_smin_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vs
; CHECK-LABEL: vpreduce_smin_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smin.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -87,10 +87,10 @@ define signext i8 @vpreduce_and_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_and_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.and.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -102,10 +102,10 @@ define signext i8 @vpreduce_or_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vsca
; CHECK-LABEL: vpreduce_or_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.or.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -117,10 +117,10 @@ define signext i8 @vpreduce_xor_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_xor_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.xor.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i8 %r
@@ -132,10 +132,10 @@ define signext i8 @vpreduce_add_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_add_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.add.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -148,10 +148,10 @@ define signext i8 @vpreduce_umax_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umax.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -163,10 +163,10 @@ define signext i8 @vpreduce_smax_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vs
; CHECK-LABEL: vpreduce_smax_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smax.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -179,10 +179,10 @@ define signext i8 @vpreduce_umin_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umin.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -194,10 +194,10 @@ define signext i8 @vpreduce_smin_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vs
; CHECK-LABEL: vpreduce_smin_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smin.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -209,10 +209,10 @@ define signext i8 @vpreduce_and_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_and_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.and.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -224,10 +224,10 @@ define signext i8 @vpreduce_or_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vsca
; CHECK-LABEL: vpreduce_or_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.or.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -239,10 +239,10 @@ define signext i8 @vpreduce_xor_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_xor_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.xor.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i8 %r
@@ -254,10 +254,10 @@ define signext i8 @vpreduce_add_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_add_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.add.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -270,10 +270,10 @@ define signext i8 @vpreduce_umax_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umax.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -285,10 +285,10 @@ define signext i8 @vpreduce_smax_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vs
; CHECK-LABEL: vpreduce_smax_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smax.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -301,10 +301,10 @@ define signext i8 @vpreduce_umin_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.umin.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -316,10 +316,10 @@ define signext i8 @vpreduce_smin_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vs
; CHECK-LABEL: vpreduce_smin_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.smin.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -331,10 +331,10 @@ define signext i8 @vpreduce_and_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_and_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.and.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -346,10 +346,10 @@ define signext i8 @vpreduce_or_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vsca
; CHECK-LABEL: vpreduce_or_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.or.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -361,10 +361,10 @@ define signext i8 @vpreduce_xor_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vsc
; CHECK-LABEL: vpreduce_xor_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i8 @llvm.vp.reduce.xor.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i8 %r
@@ -376,10 +376,10 @@ define signext i16 @vpreduce_add_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; CHECK-LABEL: vpreduce_add_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.add.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -394,10 +394,10 @@ define signext i16 @vpreduce_umax_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv1i16:
@@ -406,10 +406,10 @@ define signext i16 @vpreduce_umax_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umax.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -421,10 +421,10 @@ define signext i16 @vpreduce_smax_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; CHECK-LABEL: vpreduce_smax_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smax.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -439,10 +439,10 @@ define signext i16 @vpreduce_umin_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv1i16:
@@ -451,10 +451,10 @@ define signext i16 @vpreduce_umin_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umin.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -466,10 +466,10 @@ define signext i16 @vpreduce_smin_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; CHECK-LABEL: vpreduce_smin_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smin.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -481,10 +481,10 @@ define signext i16 @vpreduce_and_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; CHECK-LABEL: vpreduce_and_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.and.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -496,10 +496,10 @@ define signext i16 @vpreduce_or_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <
; CHECK-LABEL: vpreduce_or_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.or.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -511,10 +511,10 @@ define signext i16 @vpreduce_xor_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v,
; CHECK-LABEL: vpreduce_xor_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.xor.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i16 %r
@@ -526,10 +526,10 @@ define signext i16 @vpreduce_add_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; CHECK-LABEL: vpreduce_add_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.add.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -544,10 +544,10 @@ define signext i16 @vpreduce_umax_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv2i16:
@@ -556,10 +556,10 @@ define signext i16 @vpreduce_umax_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umax.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -571,10 +571,10 @@ define signext i16 @vpreduce_smax_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; CHECK-LABEL: vpreduce_smax_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smax.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -589,10 +589,10 @@ define signext i16 @vpreduce_umin_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv2i16:
@@ -601,10 +601,10 @@ define signext i16 @vpreduce_umin_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umin.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -616,10 +616,10 @@ define signext i16 @vpreduce_smin_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; CHECK-LABEL: vpreduce_smin_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smin.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -631,10 +631,10 @@ define signext i16 @vpreduce_and_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; CHECK-LABEL: vpreduce_and_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.and.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -646,10 +646,10 @@ define signext i16 @vpreduce_or_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <
; CHECK-LABEL: vpreduce_or_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.or.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -661,10 +661,10 @@ define signext i16 @vpreduce_xor_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v,
; CHECK-LABEL: vpreduce_xor_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.xor.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i16 %r
@@ -676,10 +676,10 @@ define signext i16 @vpreduce_add_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; CHECK-LABEL: vpreduce_add_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.add.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -694,10 +694,10 @@ define signext i16 @vpreduce_umax_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv4i16:
@@ -706,10 +706,10 @@ define signext i16 @vpreduce_umax_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umax.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -721,10 +721,10 @@ define signext i16 @vpreduce_smax_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; CHECK-LABEL: vpreduce_smax_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smax.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -739,10 +739,10 @@ define signext i16 @vpreduce_umin_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv4i16:
@@ -751,10 +751,10 @@ define signext i16 @vpreduce_umin_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i16 @llvm.vp.reduce.umin.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -766,10 +766,10 @@ define signext i16 @vpreduce_smin_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; CHECK-LABEL: vpreduce_smin_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.smin.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -781,10 +781,10 @@ define signext i16 @vpreduce_and_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; CHECK-LABEL: vpreduce_and_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.and.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -796,10 +796,10 @@ define signext i16 @vpreduce_or_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <
; CHECK-LABEL: vpreduce_or_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.or.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -811,10 +811,10 @@ define signext i16 @vpreduce_xor_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v,
; CHECK-LABEL: vpreduce_xor_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i16 @llvm.vp.reduce.xor.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i16 %r
@@ -826,10 +826,10 @@ define signext i32 @vpreduce_add_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; CHECK-LABEL: vpreduce_add_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.add.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -841,10 +841,10 @@ define signext i32 @vpreduce_umax_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; RV32-LABEL: vpreduce_umax_nxv1i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv1i32:
@@ -852,10 +852,10 @@ define signext i32 @vpreduce_umax_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -867,10 +867,10 @@ define signext i32 @vpreduce_smax_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; CHECK-LABEL: vpreduce_smax_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smax.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -882,10 +882,10 @@ define signext i32 @vpreduce_umin_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; RV32-LABEL: vpreduce_umin_nxv1i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv1i32:
@@ -893,10 +893,10 @@ define signext i32 @vpreduce_umin_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -908,10 +908,10 @@ define signext i32 @vpreduce_smin_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; CHECK-LABEL: vpreduce_smin_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smin.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -923,10 +923,10 @@ define signext i32 @vpreduce_and_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; CHECK-LABEL: vpreduce_and_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.and.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -938,10 +938,10 @@ define signext i32 @vpreduce_or_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <
; CHECK-LABEL: vpreduce_or_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.or.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -953,10 +953,10 @@ define signext i32 @vpreduce_xor_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v,
; CHECK-LABEL: vpreduce_xor_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.xor.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i32 %r
@@ -968,10 +968,10 @@ define signext i32 @vpreduce_add_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; CHECK-LABEL: vpreduce_add_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.add.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -983,10 +983,10 @@ define signext i32 @vpreduce_umax_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; RV32-LABEL: vpreduce_umax_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv2i32:
@@ -994,10 +994,10 @@ define signext i32 @vpreduce_umax_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -1009,10 +1009,10 @@ define signext i32 @vpreduce_smax_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; CHECK-LABEL: vpreduce_smax_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smax.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -1024,10 +1024,10 @@ define signext i32 @vpreduce_umin_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; RV32-LABEL: vpreduce_umin_nxv2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv2i32:
@@ -1035,10 +1035,10 @@ define signext i32 @vpreduce_umin_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -1050,10 +1050,10 @@ define signext i32 @vpreduce_smin_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; CHECK-LABEL: vpreduce_smin_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smin.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -1065,10 +1065,10 @@ define signext i32 @vpreduce_and_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; CHECK-LABEL: vpreduce_and_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.and.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -1080,10 +1080,10 @@ define signext i32 @vpreduce_or_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <
; CHECK-LABEL: vpreduce_or_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.or.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -1095,10 +1095,10 @@ define signext i32 @vpreduce_xor_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v,
; CHECK-LABEL: vpreduce_xor_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.xor.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i32 %r
@@ -1110,10 +1110,10 @@ define signext i32 @vpreduce_add_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; CHECK-LABEL: vpreduce_add_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredsum.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.add.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1125,10 +1125,10 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; RV32-LABEL: vpreduce_umax_nxv4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv4i32:
@@ -1136,10 +1136,10 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1151,10 +1151,10 @@ define signext i32 @vpreduce_smax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; CHECK-LABEL: vpreduce_smax_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmax.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smax.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1166,10 +1166,10 @@ define signext i32 @vpreduce_umin_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; RV32-LABEL: vpreduce_umin_nxv4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV32-NEXT: vmv.v.x v25, a0
+; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv4i32:
@@ -1177,10 +1177,10 @@ define signext i32 @vpreduce_umin_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1192,10 +1192,10 @@ define signext i32 @vpreduce_smin_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; CHECK-LABEL: vpreduce_smin_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmin.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.smin.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1207,10 +1207,10 @@ define signext i32 @vpreduce_and_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; CHECK-LABEL: vpreduce_and_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredand.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.and.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1222,10 +1222,10 @@ define signext i32 @vpreduce_or_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <
; CHECK-LABEL: vpreduce_or_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredor.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.or.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1237,10 +1237,10 @@ define signext i32 @vpreduce_xor_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
; CHECK-LABEL: vpreduce_xor_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v10, v8, v10, v0.t
+; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.xor.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i32 %r
@@ -1257,24 +1257,24 @@ define signext i64 @vpreduce_add_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_add_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.add.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1291,24 +1291,24 @@ define signext i64 @vpreduce_umax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umax.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1325,24 +1325,24 @@ define signext i64 @vpreduce_smax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smax_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smax.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1359,24 +1359,24 @@ define signext i64 @vpreduce_umin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umin.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1393,24 +1393,24 @@ define signext i64 @vpreduce_smin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smin_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smin.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1427,24 +1427,24 @@ define signext i64 @vpreduce_and_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_and_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.and.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1461,24 +1461,24 @@ define signext i64 @vpreduce_or_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_or_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.or.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1495,24 +1495,24 @@ define signext i64 @vpreduce_xor_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t
+; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v9, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_xor_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v9, v8, v9, v0.t
+; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.xor.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)
ret i64 %r
@@ -1529,24 +1529,24 @@ define signext i64 @vpreduce_add_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_add_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.add.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1563,24 +1563,24 @@ define signext i64 @vpreduce_umax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umax.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1597,24 +1597,24 @@ define signext i64 @vpreduce_smax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smax_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smax.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1631,24 +1631,24 @@ define signext i64 @vpreduce_umin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umin.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1665,24 +1665,24 @@ define signext i64 @vpreduce_smin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smin_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smin.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1699,24 +1699,24 @@ define signext i64 @vpreduce_and_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_and_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.and.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1733,24 +1733,24 @@ define signext i64 @vpreduce_or_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_or_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.or.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1767,24 +1767,24 @@ define signext i64 @vpreduce_xor_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t
+; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v10, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_xor_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v10, v8, v10, v0.t
+; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.xor.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)
ret i64 %r
@@ -1801,24 +1801,24 @@ define signext i64 @vpreduce_add_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredsum.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_add_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredsum.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.add.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1835,24 +1835,24 @@ define signext i64 @vpreduce_umax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmaxu.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmaxu.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umax.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1869,24 +1869,24 @@ define signext i64 @vpreduce_smax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmax.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smax_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmax.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smax.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1903,24 +1903,24 @@ define signext i64 @vpreduce_umin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredminu.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredminu.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.umin.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1937,24 +1937,24 @@ define signext i64 @vpreduce_smin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredmin.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_smin_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredmin.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.smin.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
@@ -1971,24 +1971,24 @@ define signext i64 @vpreduce_and_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredand.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_and_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredand.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredand.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.and.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
@@ -2005,24 +2005,24 @@ define signext i64 @vpreduce_or_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredor.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_or_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredor.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.or.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
@@ -2039,24 +2039,24 @@ define signext i64 @vpreduce_xor_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v,
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
-; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV32-NEXT: vmv.x.s a0, v25
+; RV32-NEXT: vredxor.vs v12, v8, v12, v0.t
+; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: addi a1, zero, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vsrl.vx v25, v25, a1
-; RV32-NEXT: vmv.x.s a1, v25
+; RV32-NEXT: vsrl.vx v8, v12, a1
+; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_xor_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu
-; RV64-NEXT: vmv.v.x v25, a0
+; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu
-; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t
-; RV64-NEXT: vmv.x.s a0, v25
+; RV64-NEXT: vredxor.vs v12, v8, v12, v0.t
+; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: ret
%r = call i64 @llvm.vp.reduce.xor.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)
ret i64 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
index acd8806516e21..1d8797daa6ebc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
@@ -8,9 +8,9 @@ define signext i1 @vpreduce_and_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vsc
; CHECK-LABEL: vpreduce_and_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -24,10 +24,10 @@ declare i1 @llvm.vp.reduce.or.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i
define signext i1 @vpreduce_or_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_nxv1i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -42,10 +42,10 @@ declare i1 @llvm.vp.reduce.xor.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>,
define signext i1 @vpreduce_xor_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_nxv1i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -60,9 +60,9 @@ define signext i1 @vpreduce_and_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vsc
; CHECK-LABEL: vpreduce_and_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -76,10 +76,10 @@ declare i1 @llvm.vp.reduce.or.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i
define signext i1 @vpreduce_or_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -94,10 +94,10 @@ declare i1 @llvm.vp.reduce.xor.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>,
define signext i1 @vpreduce_xor_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_nxv2i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -112,9 +112,9 @@ define signext i1 @vpreduce_and_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vsc
; CHECK-LABEL: vpreduce_and_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -128,10 +128,10 @@ declare i1 @llvm.vp.reduce.or.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i
define signext i1 @vpreduce_or_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_nxv4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -146,10 +146,10 @@ declare i1 @llvm.vp.reduce.xor.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>,
define signext i1 @vpreduce_xor_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_nxv4i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -164,9 +164,9 @@ define signext i1 @vpreduce_and_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vsc
; CHECK-LABEL: vpreduce_and_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -180,10 +180,10 @@ declare i1 @llvm.vp.reduce.or.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i
define signext i1 @vpreduce_or_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_nxv8i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -198,10 +198,10 @@ declare i1 @llvm.vp.reduce.xor.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>,
define signext i1 @vpreduce_xor_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_nxv8i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -216,9 +216,9 @@ define signext i1 @vpreduce_and_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <v
; CHECK-LABEL: vpreduce_and_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -232,10 +232,10 @@ declare i1 @llvm.vp.reduce.or.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>
define signext i1 @vpreduce_or_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_nxv16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -250,10 +250,10 @@ declare i1 @llvm.vp.reduce.xor.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1
define signext i1 @vpreduce_xor_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_nxv16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -268,9 +268,9 @@ define signext i1 @vpreduce_and_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <v
; CHECK-LABEL: vpreduce_and_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -284,10 +284,10 @@ declare i1 @llvm.vp.reduce.or.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>
define signext i1 @vpreduce_or_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_nxv32i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -302,10 +302,10 @@ declare i1 @llvm.vp.reduce.xor.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1
define signext i1 @vpreduce_xor_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_nxv32i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
@@ -320,9 +320,9 @@ define signext i1 @vpreduce_and_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <v
; CHECK-LABEL: vpreduce_and_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
+; CHECK-NEXT: vmnand.mm v9, v0, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: neg a0, a0
@@ -336,10 +336,10 @@ declare i1 @llvm.vp.reduce.or.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>
define signext i1 @vpreduce_or_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_or_nxv64i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
@@ -354,10 +354,10 @@ declare i1 @llvm.vp.reduce.xor.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1
define signext i1 @vpreduce_xor_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_xor_nxv64i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vpopc.m a1, v25, v0.t
+; CHECK-NEXT: vpopc.m a1, v9, v0.t
; CHECK-NEXT: xor a0, a1, a0
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: neg a0, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
index 93c22436f82e0..d3a595534ef76 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
@@ -36,8 +36,8 @@ define signext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -79,8 +79,8 @@ define signext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -122,8 +122,8 @@ define signext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -165,8 +165,8 @@ define signext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -208,8 +208,8 @@ define signext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -251,8 +251,8 @@ define signext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
@@ -294,8 +294,8 @@ define signext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {
; CHECK-LABEL: vreduce_and_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
-; CHECK-NEXT: vmnand.mm v25, v0, v0
-; CHECK-NEXT: vpopc.m a0, v25
+; CHECK-NEXT: vmnand.mm v8, v0, v0
+; CHECK-NEXT: vpopc.m a0, v8
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: neg a0, a0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
index fca64ecf037aa..f0bfe6c3226a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vrem_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vrem.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vrem.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vrem.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vrem_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vrem.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vrem.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vrem.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vrem_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vrem.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vrem.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vrem.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
index 3e287a8688727..a0580053cc922 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
@@ -28,13 +28,13 @@ define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -69,13 +69,13 @@ define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -110,13 +110,13 @@ define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -151,13 +151,13 @@ define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -192,13 +192,13 @@ define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vsrl.vi v28, v26, 7
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v10, v10, v8
+; CHECK-NEXT: vsra.vi v10, v10, 2
+; CHECK-NEXT: vsrl.vi v12, v10, 7
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -233,13 +233,13 @@ define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vsrl.vi v12, v28, 7
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v12, v12, v8
+; CHECK-NEXT: vsra.vi v12, v12, 2
+; CHECK-NEXT: vsrl.vi v16, v12, 7
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -316,12 +316,12 @@ define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -357,12 +357,12 @@ define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -398,12 +398,12 @@ define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -439,12 +439,12 @@ define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vsrl.vi v28, v26, 15
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsra.vi v10, v10, 1
+; CHECK-NEXT: vsrl.vi v12, v10, 15
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -480,12 +480,12 @@ define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vsrl.vi v12, v28, 15
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsra.vi v12, v12, 1
+; CHECK-NEXT: vsrl.vi v16, v12, 15
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -562,13 +562,13 @@ define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -604,13 +604,13 @@ define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -646,13 +646,13 @@ define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsrl.vi v28, v26, 31
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v10, v10, v8
+; CHECK-NEXT: vsrl.vi v12, v10, 31
+; CHECK-NEXT: vsra.vi v10, v10, 2
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -688,13 +688,13 @@ define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addi a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsrl.vi v12, v28, 31
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v12, v12, v8
+; CHECK-NEXT: vsrl.vi v16, v12, 31
+; CHECK-NEXT: vsra.vi v12, v12, 2
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -763,8 +763,8 @@ define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vrem.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vrem.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -786,14 +786,14 @@ define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmulh.vv v25, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmulh.vv v9, v8, v9
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v26, v25, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vsrl.vx v10, v9, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
@@ -821,8 +821,8 @@ define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vrem.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vrem.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -844,14 +844,14 @@ define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmulh.vv v26, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmulh.vv v10, v8, v10
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v28, v26, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vsrl.vx v12, v10, a0
+; CHECK-NEXT: vsra.vi v10, v10, 1
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
@@ -879,8 +879,8 @@ define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vrem.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vrem.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
@@ -902,14 +902,14 @@ define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmulh.vv v28, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmulh.vv v12, v8, v12
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v12, v28, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vsrl.vx v16, v12, a0
+; CHECK-NEXT: vsra.vi v12, v12, 1
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
index a56f28eb435e0..5fb123b5186de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
@@ -28,13 +28,13 @@ define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -69,13 +69,13 @@ define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -110,13 +110,13 @@ define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -151,13 +151,13 @@ define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 7
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -192,13 +192,13 @@ define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vsrl.vi v28, v26, 7
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v10, v10, v8
+; CHECK-NEXT: vsra.vi v10, v10, 2
+; CHECK-NEXT: vsrl.vi v12, v10, 7
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -233,13 +233,13 @@ define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 109
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vsrl.vi v12, v28, 7
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v12, v12, v8
+; CHECK-NEXT: vsra.vi v12, v12, 2
+; CHECK-NEXT: vsrl.vi v16, v12, 7
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -316,12 +316,12 @@ define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -357,12 +357,12 @@ define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -398,12 +398,12 @@ define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vsrl.vi v26, v25, 15
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -439,12 +439,12 @@ define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vsrl.vi v28, v26, 15
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsra.vi v10, v10, 1
+; CHECK-NEXT: vsrl.vi v12, v10, 15
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -480,12 +480,12 @@ define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 1048571
; CHECK-NEXT: addiw a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vsrl.vi v12, v28, 15
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsra.vi v12, v12, 1
+; CHECK-NEXT: vsrl.vi v16, v12, 15
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -562,13 +562,13 @@ define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -604,13 +604,13 @@ define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
-; CHECK-NEXT: vsub.vv v25, v25, v8
-; CHECK-NEXT: vsra.vi v25, v25, 2
-; CHECK-NEXT: vsrl.vi v26, v25, 31
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -646,13 +646,13 @@ define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
-; CHECK-NEXT: vsub.vv v26, v26, v8
-; CHECK-NEXT: vsra.vi v26, v26, 2
-; CHECK-NEXT: vsrl.vi v28, v26, 31
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v10, v10, v8
+; CHECK-NEXT: vsra.vi v10, v10, 2
+; CHECK-NEXT: vsrl.vi v12, v10, 31
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -688,13 +688,13 @@ define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 449390
; CHECK-NEXT: addiw a0, a0, -1171
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
-; CHECK-NEXT: vsub.vv v28, v28, v8
-; CHECK-NEXT: vsra.vi v28, v28, 2
-; CHECK-NEXT: vsrl.vi v12, v28, 31
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v12, v12, v8
+; CHECK-NEXT: vsra.vi v12, v12, 2
+; CHECK-NEXT: vsrl.vi v16, v12, 31
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -778,13 +778,13 @@ define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 12
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v25, v8, a0
+; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v26, v25, a0
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vadd.vv v25, v25, v26
+; CHECK-NEXT: vsrl.vx v10, v9, a0
+; CHECK-NEXT: vsra.vi v9, v9, 1
+; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -826,13 +826,13 @@ define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 12
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v26, v8, a0
+; CHECK-NEXT: vmulh.vx v10, v8, a0
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v28, v26, a0
-; CHECK-NEXT: vsra.vi v26, v26, 1
-; CHECK-NEXT: vadd.vv v26, v26, v28
+; CHECK-NEXT: vsrl.vx v12, v10, a0
+; CHECK-NEXT: vsra.vi v10, v10, 1
+; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -874,13 +874,13 @@ define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 12
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v28, v8, a0
+; CHECK-NEXT: vmulh.vx v12, v8, a0
; CHECK-NEXT: addi a0, zero, 63
-; CHECK-NEXT: vsrl.vx v12, v28, a0
-; CHECK-NEXT: vsra.vi v28, v28, 1
-; CHECK-NEXT: vadd.vv v28, v28, v12
+; CHECK-NEXT: vsrl.vx v16, v12, a0
+; CHECK-NEXT: vsra.vi v12, v12, 1
+; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
index ede8de0acadd1..5b299da083174 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
@@ -10,13 +10,13 @@ define <vscale x 8 x i7> @vrem_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vrem_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vv v25, v8, v8
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vadd.vv v26, v26, v26
-; CHECK-NEXT: vsra.vi v26, v26, 1
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vadd.vv v9, v9, v9
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vrem.vv v8, v25, v26, v0.t
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> undef, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> undef, <vscale x 8 x i32> zeroinitializer
@@ -969,9 +969,9 @@ define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v25, v0.t
+; RV32-NEXT: vrem.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -995,9 +995,9 @@ define <vscale x 1 x i64> @vrem_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v25
+; RV32-NEXT: vrem.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1047,9 +1047,9 @@ define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v26, v0.t
+; RV32-NEXT: vrem.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1073,9 +1073,9 @@ define <vscale x 2 x i64> @vrem_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v26
+; RV32-NEXT: vrem.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1125,9 +1125,9 @@ define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v28, v0.t
+; RV32-NEXT: vrem.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1151,9 +1151,9 @@ define <vscale x 4 x i64> @vrem_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vrem.vv v8, v8, v28
+; RV32-NEXT: vrem.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
index 9d468bd9a6c4a..8f1ebf185f620 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vremu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vremu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vremu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vremu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vremu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vremu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vremu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vremu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vremu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vremu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vremu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vremu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
index a1c7920f5b6d9..52e7c5e50e3af 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
@@ -28,10 +28,10 @@ define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -66,10 +66,10 @@ define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -104,10 +104,10 @@ define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -142,10 +142,10 @@ define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -180,10 +180,10 @@ define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v26, v26, 5
+; CHECK-NEXT: vmulhu.vx v10, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v10, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -218,10 +218,10 @@ define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v28, v28, 5
+; CHECK-NEXT: vmulhu.vx v12, v8, a0
+; CHECK-NEXT: vsrl.vi v12, v12, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -295,10 +295,10 @@ define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 13
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -334,10 +334,10 @@ define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 13
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -373,10 +373,10 @@ define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 13
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -412,10 +412,10 @@ define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v26, v26, 13
+; CHECK-NEXT: vmulhu.vx v10, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v10, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -451,10 +451,10 @@ define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v28, v28, 13
+; CHECK-NEXT: vmulhu.vx v12, v8, a0
+; CHECK-NEXT: vsrl.vi v12, v12, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -529,10 +529,10 @@ define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 29
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -568,10 +568,10 @@ define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 29
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -607,10 +607,10 @@ define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v26, v26, 29
+; CHECK-NEXT: vmulhu.vx v10, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v10, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -646,10 +646,10 @@ define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v28, v28, 29
+; CHECK-NEXT: vmulhu.vx v12, v8, a0
+; CHECK-NEXT: vsrl.vi v12, v12, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -715,8 +715,8 @@ define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vremu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vremu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -736,12 +736,12 @@ define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmulhu.vv v25, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmulhu.vv v9, v8, v9
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v25, v25, a0
+; CHECK-NEXT: vsrl.vx v9, v9, a0
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
@@ -769,10 +769,10 @@ define <vscale x 1 x i64> @vremu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vsll.vv v25, v25, v9
-; CHECK-NEXT: vadd.vi v25, v25, -1
-; CHECK-NEXT: vand.vv v8, v8, v25
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vsll.vv v9, v10, v9
+; CHECK-NEXT: vadd.vi v9, v9, -1
+; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -800,8 +800,8 @@ define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vremu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vremu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -821,12 +821,12 @@ define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmulhu.vv v26, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmulhu.vv v10, v8, v10
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v26, v26, a0
+; CHECK-NEXT: vsrl.vx v10, v10, a0
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
@@ -854,10 +854,10 @@ define <vscale x 2 x i64> @vremu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vsll.vv v26, v26, v10
-; CHECK-NEXT: vadd.vi v26, v26, -1
-; CHECK-NEXT: vand.vv v8, v8, v26
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vsll.vv v10, v12, v10
+; CHECK-NEXT: vadd.vi v10, v10, -1
+; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -885,8 +885,8 @@ define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vremu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vremu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
@@ -906,12 +906,12 @@ define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmulhu.vv v28, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmulhu.vv v12, v8, v12
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v28, v28, a0
+; CHECK-NEXT: vsrl.vx v12, v12, a0
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
@@ -939,10 +939,10 @@ define <vscale x 4 x i64> @vremu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vsll.vv v28, v28, v12
-; CHECK-NEXT: vadd.vi v28, v28, -1
-; CHECK-NEXT: vand.vv v8, v8, v28
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vsll.vv v12, v16, v12
+; CHECK-NEXT: vadd.vi v12, v12, -1
+; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
index 70bebb1fcf168..b8c112e94d788 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
@@ -28,10 +28,10 @@ define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -66,10 +66,10 @@ define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -104,10 +104,10 @@ define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -142,10 +142,10 @@ define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 5
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -180,10 +180,10 @@ define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v26, v26, 5
+; CHECK-NEXT: vmulhu.vx v10, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v10, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -218,10 +218,10 @@ define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 33
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v28, v28, 5
+; CHECK-NEXT: vmulhu.vx v12, v8, a0
+; CHECK-NEXT: vsrl.vi v12, v12, 5
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -295,10 +295,10 @@ define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 13
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -334,10 +334,10 @@ define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 13
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -373,10 +373,10 @@ define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 13
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -412,10 +412,10 @@ define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v26, v26, 13
+; CHECK-NEXT: vmulhu.vx v10, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v10, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -451,10 +451,10 @@ define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v28, v28, 13
+; CHECK-NEXT: vmulhu.vx v12, v8, a0
+; CHECK-NEXT: vsrl.vi v12, v12, 13
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -529,10 +529,10 @@ define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 29
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -568,10 +568,10 @@ define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
-; CHECK-NEXT: vsrl.vi v25, v25, 29
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v9, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -607,10 +607,10 @@ define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
-; CHECK-NEXT: vsrl.vi v26, v26, 29
+; CHECK-NEXT: vmulhu.vx v10, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v10, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -646,10 +646,10 @@ define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-NEXT: lui a0, 131072
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
-; CHECK-NEXT: vsrl.vi v28, v28, 29
+; CHECK-NEXT: vmulhu.vx v12, v8, a0
+; CHECK-NEXT: vsrl.vi v12, v12, 29
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -725,11 +725,11 @@ define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 61
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v25, v8, a0
+; CHECK-NEXT: vmulhu.vx v9, v8, a0
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v25, v25, a0
+; CHECK-NEXT: vsrl.vx v9, v9, a0
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v25
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -756,10 +756,10 @@ define <vscale x 1 x i64> @vremu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vsll.vv v25, v25, v9
-; CHECK-NEXT: vadd.vi v25, v25, -1
-; CHECK-NEXT: vand.vv v8, v8, v25
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vsll.vv v9, v10, v9
+; CHECK-NEXT: vadd.vi v9, v9, -1
+; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -797,11 +797,11 @@ define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 61
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v26, v8, a0
+; CHECK-NEXT: vmulhu.vx v10, v8, a0
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v26, v26, a0
+; CHECK-NEXT: vsrl.vx v10, v10, a0
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v26
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -828,10 +828,10 @@ define <vscale x 2 x i64> @vremu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vsll.vv v26, v26, v10
-; CHECK-NEXT: vadd.vi v26, v26, -1
-; CHECK-NEXT: vand.vv v8, v8, v26
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vsll.vv v10, v12, v10
+; CHECK-NEXT: vadd.vi v10, v10, -1
+; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -869,11 +869,11 @@ define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
; CHECK-NEXT: slli a0, a0, 61
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v28, v8, a0
+; CHECK-NEXT: vmulhu.vx v12, v8, a0
; CHECK-NEXT: addi a0, zero, 61
-; CHECK-NEXT: vsrl.vx v28, v28, a0
+; CHECK-NEXT: vsrl.vx v12, v12, a0
; CHECK-NEXT: addi a0, zero, -7
-; CHECK-NEXT: vnmsac.vx v8, a0, v28
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -900,10 +900,10 @@ define <vscale x 4 x i64> @vremu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v28, a0
-; CHECK-NEXT: vsll.vv v28, v28, v12
-; CHECK-NEXT: vadd.vi v28, v28, -1
-; CHECK-NEXT: vand.vv v8, v8, v28
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vsll.vv v12, v16, v12
+; CHECK-NEXT: vadd.vi v12, v12, -1
+; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
index d1ce409e62cd3..cd1a4379b38bc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
@@ -11,11 +11,11 @@ define <vscale x 8 x i7> @vremu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 127
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, mu
-; CHECK-NEXT: vand.vx v25, v8, a2
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vand.vx v26, v26, a2
+; CHECK-NEXT: vand.vx v8, v8, a2
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vremu.vv v8, v25, v26, v0.t
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> undef, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> undef, <vscale x 8 x i32> zeroinitializer
@@ -968,9 +968,9 @@ define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v25, v0.t
+; RV32-NEXT: vremu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -994,9 +994,9 @@ define <vscale x 1 x i64> @vremu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v25
+; RV32-NEXT: vremu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1046,9 +1046,9 @@ define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v26, v0.t
+; RV32-NEXT: vremu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1072,9 +1072,9 @@ define <vscale x 2 x i64> @vremu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v26
+; RV32-NEXT: vremu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1124,9 +1124,9 @@ define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v28, v0.t
+; RV32-NEXT: vremu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1150,9 +1150,9 @@ define <vscale x 4 x i64> @vremu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vremu.vv v8, v8, v28
+; RV32-NEXT: vremu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
index 3c596398d69aa..89bb37d9eb0e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i32(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i32(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i32(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i32(
@@ -194,8 +194,8 @@ define <vscale x 16 x i8> @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i32(
@@ -240,8 +240,8 @@ define <vscale x 32 x i8> @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i32(
@@ -333,8 +333,8 @@ define <vscale x 1 x i16> @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i32(
@@ -379,8 +379,8 @@ define <vscale x 2 x i16> @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i32(
@@ -425,8 +425,8 @@ define <vscale x 4 x i16> @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i32(
@@ -471,8 +471,8 @@ define <vscale x 8 x i16> @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i32(
@@ -517,8 +517,8 @@ define <vscale x 16 x i16> @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16(<vs
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i32(
@@ -610,8 +610,8 @@ define <vscale x 1 x i32> @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i32(
@@ -656,8 +656,8 @@ define <vscale x 2 x i32> @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i32(
@@ -702,8 +702,8 @@ define <vscale x 4 x i32> @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i32(
@@ -748,8 +748,8 @@ define <vscale x 8 x i32> @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i32(
@@ -841,8 +841,8 @@ define <vscale x 1 x half> @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i32(
@@ -887,8 +887,8 @@ define <vscale x 2 x half> @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i32(
@@ -933,8 +933,8 @@ define <vscale x 4 x half> @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i32(
@@ -979,8 +979,8 @@ define <vscale x 8 x half> @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i32(
@@ -1025,8 +1025,8 @@ define <vscale x 16 x half> @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16(<v
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i32(
@@ -1118,8 +1118,8 @@ define <vscale x 1 x float> @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.i32(
@@ -1164,8 +1164,8 @@ define <vscale x 2 x float> @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.i32(
@@ -1210,8 +1210,8 @@ define <vscale x 4 x float> @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.i32(
@@ -1256,8 +1256,8 @@ define <vscale x 8 x float> @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.i32(
@@ -1349,8 +1349,8 @@ define <vscale x 1 x double> @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64(<vsc
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.i32(
@@ -1395,8 +1395,8 @@ define <vscale x 2 x double> @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64(<vsc
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.i32(
@@ -1441,8 +1441,8 @@ define <vscale x 4 x double> @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64(<vsc
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.i32(
@@ -1534,8 +1534,8 @@ define <vscale x 1 x i8> @intrinsic_vrgather_vx_nxv1i8_nxv1i8_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i32(
@@ -1580,8 +1580,8 @@ define <vscale x 2 x i8> @intrinsic_vrgather_vx_nxv2i8_nxv2i8_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i32(
@@ -1626,8 +1626,8 @@ define <vscale x 4 x i8> @intrinsic_vrgather_vx_nxv4i8_nxv4i8_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i32(
@@ -1672,8 +1672,8 @@ define <vscale x 8 x i8> @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i32(
@@ -1718,8 +1718,8 @@ define <vscale x 16 x i8> @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i32(
@@ -1764,8 +1764,8 @@ define <vscale x 32 x i8> @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i32(<vscale x 3
; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i32(
@@ -1856,8 +1856,8 @@ define <vscale x 1 x i16> @intrinsic_vrgather_vx_nxv1i16_nxv1i16_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i32(
@@ -1902,8 +1902,8 @@ define <vscale x 2 x i16> @intrinsic_vrgather_vx_nxv2i16_nxv2i16_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i32(
@@ -1948,8 +1948,8 @@ define <vscale x 4 x i16> @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i32(
@@ -1994,8 +1994,8 @@ define <vscale x 8 x i16> @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i32(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i32(
@@ -2040,8 +2040,8 @@ define <vscale x 16 x i16> @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i32(
@@ -2132,8 +2132,8 @@ define <vscale x 1 x i32> @intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i32(
@@ -2178,8 +2178,8 @@ define <vscale x 2 x i32> @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i32(
@@ -2224,8 +2224,8 @@ define <vscale x 4 x i32> @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i32(
@@ -2270,8 +2270,8 @@ define <vscale x 8 x i32> @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i32(
@@ -2362,8 +2362,8 @@ define <vscale x 1 x half> @intrinsic_vrgather_vx_nxv1f16_nxv1f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i32(
@@ -2408,8 +2408,8 @@ define <vscale x 2 x half> @intrinsic_vrgather_vx_nxv2f16_nxv2f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i32(
@@ -2454,8 +2454,8 @@ define <vscale x 4 x half> @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i32(
@@ -2500,8 +2500,8 @@ define <vscale x 8 x half> @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i32(
@@ -2546,8 +2546,8 @@ define <vscale x 16 x half> @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i32(
@@ -2638,8 +2638,8 @@ define <vscale x 1 x float> @intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i32(
@@ -2684,8 +2684,8 @@ define <vscale x 2 x float> @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i32(
@@ -2730,8 +2730,8 @@ define <vscale x 4 x float> @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i32(
@@ -2776,8 +2776,8 @@ define <vscale x 8 x float> @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i32(
@@ -2868,8 +2868,8 @@ define <vscale x 1 x double> @intrinsic_vrgather_vx_nxv1f64_nxv1f64_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i32(
@@ -2914,8 +2914,8 @@ define <vscale x 2 x double> @intrinsic_vrgather_vx_nxv2f64_nxv2f64_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i32(
@@ -2960,8 +2960,8 @@ define <vscale x 4 x double> @intrinsic_vrgather_vx_nxv4f64_nxv4f64_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i32(
@@ -3047,8 +3047,8 @@ define <vscale x 1 x i8> @intrinsic_vrgather_vi_nxv1i8_nxv1i8_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i32(
@@ -3080,8 +3080,8 @@ define <vscale x 2 x i8> @intrinsic_vrgather_vi_nxv2i8_nxv2i8_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i32(
@@ -3113,8 +3113,8 @@ define <vscale x 4 x i8> @intrinsic_vrgather_vi_nxv4i8_nxv4i8_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i32(
@@ -3146,8 +3146,8 @@ define <vscale x 8 x i8> @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i32(<vscale x 8 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i32(
@@ -3179,8 +3179,8 @@ define <vscale x 16 x i8> @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i32(
@@ -3212,8 +3212,8 @@ define <vscale x 32 x i8> @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i32(<vscale x 3
; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i32(
@@ -3278,8 +3278,8 @@ define <vscale x 1 x i16> @intrinsic_vrgather_vi_nxv1i16_nxv1i16_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i32(
@@ -3311,8 +3311,8 @@ define <vscale x 2 x i16> @intrinsic_vrgather_vi_nxv2i16_nxv2i16_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i32(
@@ -3344,8 +3344,8 @@ define <vscale x 4 x i16> @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i32(
@@ -3377,8 +3377,8 @@ define <vscale x 8 x i16> @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i32(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i32(
@@ -3410,8 +3410,8 @@ define <vscale x 16 x i16> @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i32(
@@ -3476,8 +3476,8 @@ define <vscale x 1 x i32> @intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i32(
@@ -3509,8 +3509,8 @@ define <vscale x 2 x i32> @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i32(
@@ -3542,8 +3542,8 @@ define <vscale x 4 x i32> @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i32(
@@ -3575,8 +3575,8 @@ define <vscale x 8 x i32> @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i32(
@@ -3641,8 +3641,8 @@ define <vscale x 1 x half> @intrinsic_vrgather_vi_nxv1f16_nxv1f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i32(
@@ -3674,8 +3674,8 @@ define <vscale x 2 x half> @intrinsic_vrgather_vi_nxv2f16_nxv2f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i32(
@@ -3707,8 +3707,8 @@ define <vscale x 4 x half> @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i32(
@@ -3740,8 +3740,8 @@ define <vscale x 8 x half> @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i32(
@@ -3773,8 +3773,8 @@ define <vscale x 16 x half> @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i32(
@@ -3839,8 +3839,8 @@ define <vscale x 1 x float> @intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i32(
@@ -3872,8 +3872,8 @@ define <vscale x 2 x float> @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i32(
@@ -3905,8 +3905,8 @@ define <vscale x 4 x float> @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i32(
@@ -3938,8 +3938,8 @@ define <vscale x 8 x float> @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i32(
@@ -4004,8 +4004,8 @@ define <vscale x 1 x double> @intrinsic_vrgather_vi_nxv1f64_nxv1f64_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i32(
@@ -4037,8 +4037,8 @@ define <vscale x 2 x double> @intrinsic_vrgather_vi_nxv2f64_nxv2f64_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i32(
@@ -4070,8 +4070,8 @@ define <vscale x 4 x double> @intrinsic_vrgather_vi_nxv4f64_nxv4f64_i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
index 3c571f23af4a8..7c94903ee0644 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i64(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i64(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(
@@ -194,8 +194,8 @@ define <vscale x 16 x i8> @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i64(
@@ -240,8 +240,8 @@ define <vscale x 32 x i8> @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i64(
@@ -333,8 +333,8 @@ define <vscale x 1 x i16> @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i64(
@@ -379,8 +379,8 @@ define <vscale x 2 x i16> @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i64(
@@ -425,8 +425,8 @@ define <vscale x 4 x i16> @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i64(
@@ -471,8 +471,8 @@ define <vscale x 8 x i16> @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i64(
@@ -517,8 +517,8 @@ define <vscale x 16 x i16> @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16(<vs
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i64(
@@ -610,8 +610,8 @@ define <vscale x 1 x i32> @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i64(
@@ -656,8 +656,8 @@ define <vscale x 2 x i32> @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i64(
@@ -702,8 +702,8 @@ define <vscale x 4 x i32> @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i64(
@@ -748,8 +748,8 @@ define <vscale x 8 x i32> @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i64(
@@ -841,8 +841,8 @@ define <vscale x 1 x i64> @intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i64(
@@ -887,8 +887,8 @@ define <vscale x 2 x i64> @intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i64(
@@ -933,8 +933,8 @@ define <vscale x 4 x i64> @intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i64(
@@ -1026,8 +1026,8 @@ define <vscale x 1 x half> @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(
@@ -1072,8 +1072,8 @@ define <vscale x 2 x half> @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(
@@ -1118,8 +1118,8 @@ define <vscale x 4 x half> @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(
@@ -1164,8 +1164,8 @@ define <vscale x 8 x half> @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16(<vscal
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(
@@ -1210,8 +1210,8 @@ define <vscale x 16 x half> @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16(<v
; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(
@@ -1303,8 +1303,8 @@ define <vscale x 1 x float> @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.i64(
@@ -1349,8 +1349,8 @@ define <vscale x 2 x float> @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.i64(
@@ -1395,8 +1395,8 @@ define <vscale x 4 x float> @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.i64(
@@ -1441,8 +1441,8 @@ define <vscale x 8 x float> @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32(<vsca
; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.i64(
@@ -1534,8 +1534,8 @@ define <vscale x 1 x double> @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64(<vsc
; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.i64(
@@ -1580,8 +1580,8 @@ define <vscale x 2 x double> @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64(<vsc
; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.i64(
@@ -1626,8 +1626,8 @@ define <vscale x 4 x double> @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64(<vsc
; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.i64(
@@ -1719,8 +1719,8 @@ define <vscale x 1 x i8> @intrinsic_vrgather_vx_nxv1i8_nxv1i8_i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i64(
@@ -1765,8 +1765,8 @@ define <vscale x 2 x i8> @intrinsic_vrgather_vx_nxv2i8_nxv2i8_i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i64(
@@ -1811,8 +1811,8 @@ define <vscale x 4 x i8> @intrinsic_vrgather_vx_nxv4i8_nxv4i8_i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i64(
@@ -1857,8 +1857,8 @@ define <vscale x 8 x i8> @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i64(
@@ -1903,8 +1903,8 @@ define <vscale x 16 x i8> @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i64(
@@ -1949,8 +1949,8 @@ define <vscale x 32 x i8> @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i64(<vscale x 3
; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i64(
@@ -2041,8 +2041,8 @@ define <vscale x 1 x i16> @intrinsic_vrgather_vx_nxv1i16_nxv1i16_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i64(
@@ -2087,8 +2087,8 @@ define <vscale x 2 x i16> @intrinsic_vrgather_vx_nxv2i16_nxv2i16_i64(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i64(
@@ -2133,8 +2133,8 @@ define <vscale x 4 x i16> @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i64(
@@ -2179,8 +2179,8 @@ define <vscale x 8 x i16> @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i64(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i64(
@@ -2225,8 +2225,8 @@ define <vscale x 16 x i16> @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i64(
@@ -2317,8 +2317,8 @@ define <vscale x 1 x i32> @intrinsic_vrgather_vx_nxv1i32_nxv1i32_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i64(
@@ -2363,8 +2363,8 @@ define <vscale x 2 x i32> @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i64(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i64(
@@ -2409,8 +2409,8 @@ define <vscale x 4 x i32> @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i64(
@@ -2455,8 +2455,8 @@ define <vscale x 8 x i32> @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i64(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i64(
@@ -2547,8 +2547,8 @@ define <vscale x 1 x i64> @intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i64(
@@ -2593,8 +2593,8 @@ define <vscale x 2 x i64> @intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i64(
@@ -2639,8 +2639,8 @@ define <vscale x 4 x i64> @intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i64(
@@ -2731,8 +2731,8 @@ define <vscale x 1 x half> @intrinsic_vrgather_vx_nxv1f16_nxv1f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(
@@ -2777,8 +2777,8 @@ define <vscale x 2 x half> @intrinsic_vrgather_vx_nxv2f16_nxv2f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(
@@ -2823,8 +2823,8 @@ define <vscale x 4 x half> @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(
@@ -2869,8 +2869,8 @@ define <vscale x 8 x half> @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(
@@ -2915,8 +2915,8 @@ define <vscale x 16 x half> @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(
@@ -3007,8 +3007,8 @@ define <vscale x 1 x float> @intrinsic_vrgather_vx_nxv1f32_nxv1f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i64(
@@ -3053,8 +3053,8 @@ define <vscale x 2 x float> @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(
@@ -3099,8 +3099,8 @@ define <vscale x 4 x float> @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i64(
@@ -3145,8 +3145,8 @@ define <vscale x 8 x float> @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i64(
@@ -3237,8 +3237,8 @@ define <vscale x 1 x double> @intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i64(
@@ -3283,8 +3283,8 @@ define <vscale x 2 x double> @intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i64(
@@ -3329,8 +3329,8 @@ define <vscale x 4 x double> @intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i64(
@@ -3416,8 +3416,8 @@ define <vscale x 1 x i8> @intrinsic_vrgather_vi_nxv1i8_nxv1i8_i64(<vscale x 1 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i64(
@@ -3449,8 +3449,8 @@ define <vscale x 2 x i8> @intrinsic_vrgather_vi_nxv2i8_nxv2i8_i64(<vscale x 2 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i64(
@@ -3482,8 +3482,8 @@ define <vscale x 4 x i8> @intrinsic_vrgather_vi_nxv4i8_nxv4i8_i64(<vscale x 4 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i64(
@@ -3515,8 +3515,8 @@ define <vscale x 8 x i8> @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i64(<vscale x 8 x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i64(
@@ -3548,8 +3548,8 @@ define <vscale x 16 x i8> @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i64(
@@ -3581,8 +3581,8 @@ define <vscale x 32 x i8> @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i64(<vscale x 3
; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i64(
@@ -3647,8 +3647,8 @@ define <vscale x 1 x i16> @intrinsic_vrgather_vi_nxv1i16_nxv1i16_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i64(
@@ -3680,8 +3680,8 @@ define <vscale x 2 x i16> @intrinsic_vrgather_vi_nxv2i16_nxv2i16_i64(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i64(
@@ -3713,8 +3713,8 @@ define <vscale x 4 x i16> @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i64(
@@ -3746,8 +3746,8 @@ define <vscale x 8 x i16> @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i64(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i64(
@@ -3779,8 +3779,8 @@ define <vscale x 16 x i16> @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i64(
@@ -3845,8 +3845,8 @@ define <vscale x 1 x i32> @intrinsic_vrgather_vi_nxv1i32_nxv1i32_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i64(
@@ -3878,8 +3878,8 @@ define <vscale x 2 x i32> @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i64(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i64(
@@ -3911,8 +3911,8 @@ define <vscale x 4 x i32> @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i64(
@@ -3944,8 +3944,8 @@ define <vscale x 8 x i32> @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i64(<vscale x 8
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i64(
@@ -4010,8 +4010,8 @@ define <vscale x 1 x i64> @intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64(<vscale x 1
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i64(
@@ -4043,8 +4043,8 @@ define <vscale x 2 x i64> @intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64(<vscale x 2
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i64(
@@ -4076,8 +4076,8 @@ define <vscale x 4 x i64> @intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i64(
@@ -4142,8 +4142,8 @@ define <vscale x 1 x half> @intrinsic_vrgather_vi_nxv1f16_nxv1f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(
@@ -4175,8 +4175,8 @@ define <vscale x 2 x half> @intrinsic_vrgather_vi_nxv2f16_nxv2f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(
@@ -4208,8 +4208,8 @@ define <vscale x 4 x half> @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(
@@ -4241,8 +4241,8 @@ define <vscale x 8 x half> @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(
@@ -4274,8 +4274,8 @@ define <vscale x 16 x half> @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(
@@ -4340,8 +4340,8 @@ define <vscale x 1 x float> @intrinsic_vrgather_vi_nxv1f32_nxv1f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i64(
@@ -4373,8 +4373,8 @@ define <vscale x 2 x float> @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(
@@ -4406,8 +4406,8 @@ define <vscale x 4 x float> @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i64(
@@ -4439,8 +4439,8 @@ define <vscale x 8 x float> @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i64(<vscale x
; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i64(
@@ -4505,8 +4505,8 @@ define <vscale x 1 x double> @intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v25, v8, 9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgather.vi v9, v8, 9
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i64(
@@ -4538,8 +4538,8 @@ define <vscale x 2 x double> @intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v26, v8, 9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgather.vi v10, v8, 9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i64(
@@ -4571,8 +4571,8 @@ define <vscale x 4 x double> @intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64(<vscale
; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v28, v8, 9
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgather.vi v12, v8, 9
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
index f4842d35b82b5..91d2d15a89849 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8(<vscale x 1
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8(
@@ -240,8 +240,8 @@ define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8(<vscale x 3
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16(<vscale x 1
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16(<vscale x 2
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16(<vscale x 4
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16(<vscale x 8
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16(
@@ -470,8 +470,8 @@ define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16(<vscale
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16(
@@ -563,8 +563,8 @@ define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32(
@@ -609,8 +609,8 @@ define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32(<vscale x 4
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(
@@ -655,8 +655,8 @@ define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32(<vscale x 8
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32(
@@ -724,9 +724,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
@@ -748,8 +748,8 @@ define <vscale x 4 x i64> @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64(
@@ -817,9 +817,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64(
define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64(
@@ -841,8 +841,8 @@ define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16(
@@ -887,8 +887,8 @@ define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16(
@@ -933,8 +933,8 @@ define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16(
@@ -979,8 +979,8 @@ define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16(
@@ -1025,8 +1025,8 @@ define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16(<vscale
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16(
@@ -1118,8 +1118,8 @@ define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32(
@@ -1164,8 +1164,8 @@ define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32(
@@ -1210,8 +1210,8 @@ define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32(
@@ -1279,9 +1279,9 @@ declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
@@ -1303,8 +1303,8 @@ define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64(<vscale
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64(
@@ -1372,9 +1372,9 @@ declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
index 44a6cff647ff0..f08d485c64b3a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v9, v8, v10
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8(<vscale x 1
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v12
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8(
@@ -240,8 +240,8 @@ define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8(<vscale x 3
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v16
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16(<vscale x 1
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16(<vscale x 2
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16(<vscale x 4
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16(<vscale x 8
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16(
@@ -470,8 +470,8 @@ define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16(<vscale
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16(
@@ -563,8 +563,8 @@ define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32(<vscale x 1
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32(
@@ -609,8 +609,8 @@ define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32(<vscale x 4
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(
@@ -655,8 +655,8 @@ define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32(<vscale x 8
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32(
@@ -724,9 +724,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(
@@ -748,8 +748,8 @@ define <vscale x 4 x i64> @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64(<vscale x 4
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64(
@@ -817,9 +817,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64(
define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64(
@@ -841,8 +841,8 @@ define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16(
@@ -887,8 +887,8 @@ define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16(
@@ -933,8 +933,8 @@ define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16(
@@ -979,8 +979,8 @@ define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16(
@@ -1025,8 +1025,8 @@ define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16(<vscale
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16(
@@ -1118,8 +1118,8 @@ define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32(
@@ -1164,8 +1164,8 @@ define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v26, v8, v10
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vrgatherei16.vv v12, v8, v10
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32(
@@ -1210,8 +1210,8 @@ define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32(<vscale x
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32(
@@ -1279,9 +1279,9 @@ declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(
@@ -1303,8 +1303,8 @@ define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64(<vscale
; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v28, v8, v12
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64(
@@ -1372,9 +1372,9 @@ declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl2re16.v v26, (a0)
+; CHECK-NEXT: vl2re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
+; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
index e9675eb310320..d0474e9397b5b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
@@ -824,8 +824,8 @@ define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v25, v8
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v9, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -853,9 +853,9 @@ define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v25, v9, v0.t
+; CHECK-NEXT: vsub.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -882,8 +882,8 @@ define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v26, v8
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v10, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -911,9 +911,9 @@ define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v26, v10, v0.t
+; CHECK-NEXT: vsub.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -940,8 +940,8 @@ define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v28, v8
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v12, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -969,9 +969,9 @@ define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v28, v12, v0.t
+; CHECK-NEXT: vsub.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
index f25d4deaa9627..c90c64dd5cf36 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
@@ -442,8 +442,8 @@ define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v25, v8
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v9, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -473,8 +473,8 @@ define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v26, v8
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v10, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -504,8 +504,8 @@ define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v28, v8
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v12, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
index 333b519dd5edd..99bf38d64c92b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
@@ -987,9 +987,9 @@ define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v25, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1013,9 +1013,9 @@ define <vscale x 1 x i64> @vrsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v25, v8
+; RV32-NEXT: vsub.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1069,9 +1069,9 @@ define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v26, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v10, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1095,9 +1095,9 @@ define <vscale x 2 x i64> @vrsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v26, v8
+; RV32-NEXT: vsub.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1151,9 +1151,9 @@ define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v28, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v12, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1177,9 +1177,9 @@ define <vscale x 4 x i64> @vrsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v28, v8
+; RV32-NEXT: vsub.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
index b5036009a589f..610e277942d5a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsadd.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vsadd.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsadd.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vsadd.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsadd.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vsadd.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
index 14899a5f2321c..ab07fd7d20bf1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
@@ -673,8 +673,8 @@ define <vscale x 1 x i64> @sadd_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -722,8 +722,8 @@ define <vscale x 2 x i64> @sadd_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -771,8 +771,8 @@ define <vscale x 4 x i64> @sadd_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vsadd.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
index 609ba4a28baa6..7223bf6f11d5d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsaddu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vsaddu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsaddu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vsaddu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsaddu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vsaddu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
index 5e7a429167d67..8eec3839a37c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
@@ -673,8 +673,8 @@ define <vscale x 1 x i64> @uadd_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -722,8 +722,8 @@ define <vscale x 2 x i64> @uadd_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -771,8 +771,8 @@ define <vscale x 4 x i64> @uadd_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vsaddu.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
index 422463b7bb0bc..c15ad9f2f3a1b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
@@ -895,8 +895,8 @@ define <vscale x 1 x i64> @intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsbc.vvm v8, v8, v25, v0
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -923,8 +923,8 @@ define <vscale x 2 x i64> @intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsbc.vvm v8, v8, v26, v0
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -951,8 +951,8 @@ define <vscale x 4 x i64> @intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsbc.vvm v8, v8, v28, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
index cb03f962215db..3d344f85a8b4c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
@@ -408,13 +408,13 @@ define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %v
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v25, v16, 0
+; CHECK-NEXT: vmseq.vi v24, v16, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmseq.vi v0, v16, 0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
@@ -435,8 +435,8 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-LABEL: vselect_legalize_regression:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vmand.mm v1, v0, v25
+; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: vmand.mm v1, v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a2, a0, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
index 1363412dbdffc..0a09d71976d04 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
@@ -408,13 +408,13 @@ define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %v
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v25, v16, 0
+; CHECK-NEXT: vmseq.vi v24, v16, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmseq.vi v0, v16, 0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
@@ -435,8 +435,8 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-LABEL: vselect_legalize_regression:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vlm.v v25, (a0)
-; CHECK-NEXT: vmand.mm v1, v0, v25
+; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: vmand.mm v1, v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a2, a0, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
index acdc64002e001..e9c53906b75d7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
@@ -632,8 +632,8 @@ define <vscale x 1 x i64> @vmerge_xv_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -673,8 +673,8 @@ define <vscale x 2 x i64> @vmerge_xv_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vs
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -714,8 +714,8 @@ define <vscale x 4 x i64> @vmerge_xv_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vs
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll
index bff226bc11f8d..0862603c3200d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll
@@ -6,9 +6,9 @@ define <vscale x 1 x i1> @vselect_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>
; CHECK-LABEL: vselect_nxv1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <vscale x 1 x i1> %cc, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b
ret <vscale x 1 x i1> %v
@@ -18,9 +18,9 @@ define <vscale x 2 x i1> @vselect_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1>
; CHECK-LABEL: vselect_nxv2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <vscale x 2 x i1> %cc, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b
ret <vscale x 2 x i1> %v
@@ -30,9 +30,9 @@ define <vscale x 4 x i1> @vselect_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1>
; CHECK-LABEL: vselect_nxv4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <vscale x 4 x i1> %cc, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b
ret <vscale x 4 x i1> %v
@@ -42,9 +42,9 @@ define <vscale x 8 x i1> @vselect_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1>
; CHECK-LABEL: vselect_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <vscale x 8 x i1> %cc, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b
ret <vscale x 8 x i1> %v
@@ -54,9 +54,9 @@ define <vscale x 16 x i1> @vselect_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x
; CHECK-LABEL: vselect_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <vscale x 16 x i1> %cc, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b
ret <vscale x 16 x i1> %v
@@ -66,9 +66,9 @@ define <vscale x 32 x i1> @vselect_nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x
; CHECK-LABEL: vselect_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <vscale x 32 x i1> %cc, <vscale x 32 x i1> %a, <vscale x 32 x i1> %b
ret <vscale x 32 x i1> %v
@@ -78,9 +78,9 @@ define <vscale x 64 x i1> @vselect_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x
; CHECK-LABEL: vselect_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
-; CHECK-NEXT: vmandnot.mm v25, v8, v9
-; CHECK-NEXT: vmand.mm v26, v0, v9
-; CHECK-NEXT: vmor.mm v0, v26, v25
+; CHECK-NEXT: vmandnot.mm v8, v8, v9
+; CHECK-NEXT: vmand.mm v9, v0, v9
+; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret
%v = select <vscale x 64 x i1> %cc, <vscale x 64 x i1> %a, <vscale x 64 x i1> %b
ret <vscale x 64 x i1> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
index a77e7712e32c2..b5ac6cba9b482 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
@@ -57,12 +57,12 @@ define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
; CHECK-NEXT: beqz a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: vfadd.vv v25, v8, v9
-; CHECK-NEXT: vfmul.vv v8, v25, v8
+; CHECK-NEXT: vfadd.vv v9, v8, v9
+; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: # %if.else
-; CHECK-NEXT: vfsub.vv v25, v8, v9
-; CHECK-NEXT: vfmul.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v9, v8, v9
+; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
@@ -89,13 +89,13 @@ define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: beqz a1, .LBB2_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfadd.vv v25, v8, v9
-; CHECK-NEXT: vfmul.vv v8, v25, v8
+; CHECK-NEXT: vfadd.vv v9, v8, v9
+; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: # %if.else
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
-; CHECK-NEXT: vfsub.vv v25, v8, v9
-; CHECK-NEXT: vfmul.vv v8, v25, v8
+; CHECK-NEXT: vfsub.vv v9, v8, v9
+; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
entry:
%tobool = icmp eq i8 %cond, 0
@@ -126,27 +126,27 @@ define <vscale x 1 x double> @test4(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: lui a1, %hi(.LCPI3_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_0)
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vlse64.v v25, (a1), zero
+; CHECK-NEXT: vlse64.v v10, (a1), zero
; CHECK-NEXT: lui a1, %hi(.LCPI3_1)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_1)
-; CHECK-NEXT: vlse64.v v26, (a1), zero
-; CHECK-NEXT: vfadd.vv v25, v25, v26
+; CHECK-NEXT: vlse64.v v11, (a1), zero
+; CHECK-NEXT: vfadd.vv v10, v10, v11
; CHECK-NEXT: lui a1, %hi(scratch)
; CHECK-NEXT: addi a1, a1, %lo(scratch)
-; CHECK-NEXT: vse64.v v25, (a1)
+; CHECK-NEXT: vse64.v v10, (a1)
; CHECK-NEXT: j .LBB3_3
; CHECK-NEXT: .LBB3_2: # %if.else
; CHECK-NEXT: lui a1, %hi(.LCPI3_2)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_2)
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vlse32.v v25, (a1), zero
+; CHECK-NEXT: vlse32.v v10, (a1), zero
; CHECK-NEXT: lui a1, %hi(.LCPI3_3)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_3)
-; CHECK-NEXT: vlse32.v v26, (a1), zero
-; CHECK-NEXT: vfadd.vv v25, v25, v26
+; CHECK-NEXT: vlse32.v v11, (a1), zero
+; CHECK-NEXT: vfadd.vv v10, v10, v11
; CHECK-NEXT: lui a1, %hi(scratch)
; CHECK-NEXT: addi a1, a1, %lo(scratch)
-; CHECK-NEXT: vse32.v v25, (a1)
+; CHECK-NEXT: vse32.v v10, (a1)
; CHECK-NEXT: .LBB3_3: # %if.end
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfmul.vv v8, v8, v9
@@ -183,18 +183,18 @@ define <vscale x 1 x double> @test5(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
; CHECK-NEXT: bnez a2, .LBB4_3
; CHECK-NEXT: # %bb.1: # %if.else
-; CHECK-NEXT: vfsub.vv v25, v8, v9
+; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: andi a0, a1, 2
; CHECK-NEXT: beqz a0, .LBB4_4
; CHECK-NEXT: .LBB4_2: # %if.then4
-; CHECK-NEXT: vfmul.vv v8, v25, v8
+; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_3: # %if.then
-; CHECK-NEXT: vfadd.vv v25, v8, v9
+; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: andi a0, a1, 2
; CHECK-NEXT: bnez a0, .LBB4_2
; CHECK-NEXT: .LBB4_4: # %if.else5
-; CHECK-NEXT: vfmul.vv v8, v8, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
@@ -240,41 +240,41 @@ define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, mu
; CHECK-NEXT: bnez a3, .LBB5_3
; CHECK-NEXT: # %bb.1: # %if.else
-; CHECK-NEXT: vfsub.vv v25, v8, v9
+; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: andi a1, a1, 2
; CHECK-NEXT: beqz a1, .LBB5_4
; CHECK-NEXT: .LBB5_2: # %if.then4
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_1)
-; CHECK-NEXT: vlse64.v v27, (a0), zero
-; CHECK-NEXT: vfadd.vv v26, v26, v27
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vfadd.vv v9, v9, v10
; CHECK-NEXT: lui a0, %hi(scratch)
; CHECK-NEXT: addi a0, a0, %lo(scratch)
-; CHECK-NEXT: vse64.v v26, (a0)
+; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: j .LBB5_5
; CHECK-NEXT: .LBB5_3: # %if.then
-; CHECK-NEXT: vfadd.vv v25, v8, v9
+; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: andi a1, a1, 2
; CHECK-NEXT: bnez a1, .LBB5_2
; CHECK-NEXT: .LBB5_4: # %if.else5
; CHECK-NEXT: vsetvli a0, a0, e32, m1, ta, mu
; CHECK-NEXT: lui a0, %hi(.LCPI5_2)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_2)
-; CHECK-NEXT: vlse32.v v26, (a0), zero
+; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: lui a0, %hi(.LCPI5_3)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_3)
-; CHECK-NEXT: vlse32.v v27, (a0), zero
-; CHECK-NEXT: vfadd.vv v26, v26, v27
+; CHECK-NEXT: vlse32.v v10, (a0), zero
+; CHECK-NEXT: vfadd.vv v9, v9, v10
; CHECK-NEXT: lui a0, %hi(scratch)
; CHECK-NEXT: addi a0, a0, %lo(scratch)
-; CHECK-NEXT: vse32.v v26, (a0)
+; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: .LBB5_5: # %if.end10
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v25, v25
+; CHECK-NEXT: vfmul.vv v8, v8, v8
; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
@@ -350,10 +350,10 @@ define <vscale x 1 x double> @test8(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vfsub.vv v8, v26, v25
+; CHECK-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfsub.vv v8, v9, v8
; CHECK-NEXT: .LBB6_3: # %if.then
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
@@ -395,26 +395,26 @@ define <vscale x 1 x double> @test9(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, mu
; CHECK-NEXT: beqz a1, .LBB7_2
; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: vfadd.vv v25, v8, v9
+; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: call foo at plt
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: j .LBB7_3
; CHECK-NEXT: .LBB7_2: # %if.else
-; CHECK-NEXT: vfsub.vv v25, v8, v9
+; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: .LBB7_3: # %if.end
; CHECK-NEXT: vsetvli zero, s0, e64, m1, ta, mu
-; CHECK-NEXT: vfmul.vv v8, v25, v8
+; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -503,16 +503,16 @@ define <vscale x 2 x i32> @test_vsetvli_x0_x0(<vscale x 2 x i32>* %x, <vscale x
; CHECK-LABEL: test_vsetvli_x0_x0:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: andi a0, a3, 1
; CHECK-NEXT: beqz a0, .LBB9_2
; CHECK-NEXT: # %bb.1: # %if
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwadd.vx v8, v26, zero
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwadd.vx v8, v10, zero
; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v25, v8
+; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32>* %x, i64 %vl)
@@ -542,23 +542,23 @@ define <vscale x 2 x i32> @test_vsetvli_x0_x0_2(<vscale x 2 x i32>* %x, <vscale
; CHECK-LABEL: test_vsetvli_x0_x0_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, mu
-; CHECK-NEXT: vle32.v v25, (a0)
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: andi a0, a4, 1
; CHECK-NEXT: beqz a0, .LBB10_2
; CHECK-NEXT: # %bb.1: # %if
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a1)
-; CHECK-NEXT: vwadd.wv v25, v25, v26
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: vwadd.wv v9, v9, v10
; CHECK-NEXT: .LBB10_2: # %if.end
; CHECK-NEXT: andi a0, a5, 1
; CHECK-NEXT: beqz a0, .LBB10_4
; CHECK-NEXT: # %bb.3: # %if2
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vle16.v v26, (a2)
-; CHECK-NEXT: vwadd.wv v25, v25, v26
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: vwadd.wv v9, v9, v10
; CHECK-NEXT: .LBB10_4: # %if2.end
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v25, v8
+; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(<vscale x 2 x i32>* %x, i64 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
index dd760f3e6abaa..3c8e5d9c0d5b0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
@@ -10,8 +10,8 @@ define i32 @illegal_preserve_vl(<vscale x 2 x i32> %a, <vscale x 4 x i64> %x, <v
; CHECK-LABEL: illegal_preserve_vl:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vv v28, v12, v12
-; CHECK-NEXT: vs4r.v v28, (a0)
+; CHECK-NEXT: vadd.vv v12, v12, v12
+; CHECK-NEXT: vs4r.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
index 6bfa11bea561f..5c58ae0855340 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x i64> @intrinsic_vsext_vf8_nxv2i64(<vscale x 2 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x i64> @intrinsic_vsext_vf8_nxv4i64(<vscale x 4 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8(
@@ -177,8 +177,8 @@ define <vscale x 1 x i64> @intrinsic_vsext_vf4_nxv1i64(<vscale x 1 x i16> %0, i3
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16(
@@ -219,8 +219,8 @@ define <vscale x 2 x i64> @intrinsic_vsext_vf4_nxv2i64(<vscale x 2 x i16> %0, i3
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16(
@@ -261,8 +261,8 @@ define <vscale x 4 x i64> @intrinsic_vsext_vf4_nxv4i64(<vscale x 4 x i16> %0, i3
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16(
@@ -345,8 +345,8 @@ define <vscale x 1 x i32> @intrinsic_vsext_vf4_nxv1i32(<vscale x 1 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8(
@@ -387,8 +387,8 @@ define <vscale x 2 x i32> @intrinsic_vsext_vf4_nxv2i32(<vscale x 2 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8(
@@ -429,8 +429,8 @@ define <vscale x 4 x i32> @intrinsic_vsext_vf4_nxv4i32(<vscale x 4 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(
@@ -471,8 +471,8 @@ define <vscale x 8 x i32> @intrinsic_vsext_vf4_nxv8i32(<vscale x 8 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8(
@@ -555,8 +555,8 @@ define <vscale x 1 x i32> @intrinsic_vsext_vf2_nxv1i32(<vscale x 1 x i16> %0, i3
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16(
@@ -597,8 +597,8 @@ define <vscale x 2 x i32> @intrinsic_vsext_vf2_nxv2i32(<vscale x 2 x i16> %0, i3
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16(
@@ -639,8 +639,8 @@ define <vscale x 4 x i32> @intrinsic_vsext_vf2_nxv4i32(<vscale x 4 x i16> %0, i3
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(
@@ -681,8 +681,8 @@ define <vscale x 8 x i32> @intrinsic_vsext_vf2_nxv8i32(<vscale x 8 x i16> %0, i3
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16(
@@ -765,8 +765,8 @@ define <vscale x 1 x i16> @intrinsic_vsext_vf2_nxv1i16(<vscale x 1 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8(
@@ -807,8 +807,8 @@ define <vscale x 2 x i16> @intrinsic_vsext_vf2_nxv2i16(<vscale x 2 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8(
@@ -849,8 +849,8 @@ define <vscale x 4 x i16> @intrinsic_vsext_vf2_nxv4i16(<vscale x 4 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8(
@@ -891,8 +891,8 @@ define <vscale x 8 x i16> @intrinsic_vsext_vf2_nxv8i16(<vscale x 8 x i8> %0, i32
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8(
@@ -933,8 +933,8 @@ define <vscale x 16 x i16> @intrinsic_vsext_vf2_nxv16i16(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
index 61037177d3da8..209c9c70f3b24 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x i64> @intrinsic_vsext_vf8_nxv2i64(<vscale x 2 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x i64> @intrinsic_vsext_vf8_nxv4i64(<vscale x 4 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8(
@@ -177,8 +177,8 @@ define <vscale x 1 x i64> @intrinsic_vsext_vf4_nxv1i64(<vscale x 1 x i16> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16(
@@ -219,8 +219,8 @@ define <vscale x 2 x i64> @intrinsic_vsext_vf4_nxv2i64(<vscale x 2 x i16> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16(
@@ -261,8 +261,8 @@ define <vscale x 4 x i64> @intrinsic_vsext_vf4_nxv4i64(<vscale x 4 x i16> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16(
@@ -345,8 +345,8 @@ define <vscale x 1 x i32> @intrinsic_vsext_vf4_nxv1i32(<vscale x 1 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8(
@@ -387,8 +387,8 @@ define <vscale x 2 x i32> @intrinsic_vsext_vf4_nxv2i32(<vscale x 2 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8(
@@ -429,8 +429,8 @@ define <vscale x 4 x i32> @intrinsic_vsext_vf4_nxv4i32(<vscale x 4 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(
@@ -471,8 +471,8 @@ define <vscale x 8 x i32> @intrinsic_vsext_vf4_nxv8i32(<vscale x 8 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8(
@@ -555,8 +555,8 @@ define <vscale x 1 x i64> @intrinsic_vsext_vf2_nxv1i64(<vscale x 1 x i32> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32(
@@ -597,8 +597,8 @@ define <vscale x 2 x i64> @intrinsic_vsext_vf2_nxv2i64(<vscale x 2 x i32> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32(
@@ -639,8 +639,8 @@ define <vscale x 4 x i64> @intrinsic_vsext_vf2_nxv4i64(<vscale x 4 x i32> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32(
@@ -723,8 +723,8 @@ define <vscale x 1 x i32> @intrinsic_vsext_vf2_nxv1i32(<vscale x 1 x i16> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16(
@@ -765,8 +765,8 @@ define <vscale x 2 x i32> @intrinsic_vsext_vf2_nxv2i32(<vscale x 2 x i16> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16(
@@ -807,8 +807,8 @@ define <vscale x 4 x i32> @intrinsic_vsext_vf2_nxv4i32(<vscale x 4 x i16> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(
@@ -849,8 +849,8 @@ define <vscale x 8 x i32> @intrinsic_vsext_vf2_nxv8i32(<vscale x 8 x i16> %0, i6
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16(
@@ -933,8 +933,8 @@ define <vscale x 1 x i16> @intrinsic_vsext_vf2_nxv1i16(<vscale x 1 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8(
@@ -975,8 +975,8 @@ define <vscale x 2 x i16> @intrinsic_vsext_vf2_nxv2i16(<vscale x 2 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8(
@@ -1017,8 +1017,8 @@ define <vscale x 4 x i16> @intrinsic_vsext_vf2_nxv4i16(<vscale x 4 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vsext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8(
@@ -1059,8 +1059,8 @@ define <vscale x 8 x i16> @intrinsic_vsext_vf2_nxv8i16(<vscale x 8 x i8> %0, i64
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vsext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8(
@@ -1101,8 +1101,8 @@ define <vscale x 16 x i16> @intrinsic_vsext_vf2_nxv16i16(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vsext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
index aaf7db3a34adc..8dabc1395187d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
@@ -10,11 +10,11 @@ define <vscale x 8 x i7> @vsll_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vsll_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: addi a0, zero, 127
-; CHECK-NEXT: vand.vx v25, v25, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsll.vv v8, v8, v25, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> undef, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
index 4b45bc6750ab7..9674d9d711c9a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
@@ -821,8 +821,8 @@ define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
-; CHECK-NEXT: vslide1down.vx v25, v8, a0
-; CHECK-NEXT: vslide1down.vx v8, v25, a1
+; CHECK-NEXT: vslide1down.vx v8, v8, a0
+; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
@@ -846,10 +846,10 @@ define <vscale x 1 x i64> @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64(<vs
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a3, a2, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, mu
-; CHECK-NEXT: vslide1down.vx v25, v9, a0
-; CHECK-NEXT: vslide1down.vx v25, v25, a1
+; CHECK-NEXT: vslide1down.vx v9, v9, a0
+; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0
+; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
@@ -872,8 +872,8 @@ define <vscale x 2 x i64> @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
-; CHECK-NEXT: vslide1down.vx v26, v8, a0
-; CHECK-NEXT: vslide1down.vx v8, v26, a1
+; CHECK-NEXT: vslide1down.vx v8, v8, a0
+; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(
@@ -897,10 +897,10 @@ define <vscale x 2 x i64> @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64(<vs
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a3, a2, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, mu
-; CHECK-NEXT: vslide1down.vx v26, v10, a0
-; CHECK-NEXT: vslide1down.vx v26, v26, a1
+; CHECK-NEXT: vslide1down.vx v10, v10, a0
+; CHECK-NEXT: vslide1down.vx v10, v10, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64(
@@ -923,8 +923,8 @@ define <vscale x 4 x i64> @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
-; CHECK-NEXT: vslide1down.vx v28, v8, a0
-; CHECK-NEXT: vslide1down.vx v8, v28, a1
+; CHECK-NEXT: vslide1down.vx v8, v8, a0
+; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(
@@ -948,10 +948,10 @@ define <vscale x 4 x i64> @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64(<vs
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a3, a2, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, mu
-; CHECK-NEXT: vslide1down.vx v28, v12, a0
-; CHECK-NEXT: vslide1down.vx v28, v28, a1
+; CHECK-NEXT: vslide1down.vx v12, v12, a0
+; CHECK-NEXT: vslide1down.vx v12, v12, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
index b13605200d999..2e40e606fb147 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i8> @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8(<vscale x 1
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslide1up.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8(
@@ -240,8 +240,8 @@ define <vscale x 32 x i8> @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8(<vscale x 3
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vslide1up.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8(
@@ -332,8 +332,8 @@ define <vscale x 1 x i16> @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16(
@@ -378,8 +378,8 @@ define <vscale x 2 x i16> @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16(
@@ -424,8 +424,8 @@ define <vscale x 4 x i16> @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16(
@@ -470,8 +470,8 @@ define <vscale x 8 x i16> @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslide1up.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16(
@@ -516,8 +516,8 @@ define <vscale x 16 x i16> @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16(<vscale
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vslide1up.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16(
@@ -608,8 +608,8 @@ define <vscale x 1 x i32> @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32(
@@ -654,8 +654,8 @@ define <vscale x 2 x i32> @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32(
@@ -700,8 +700,8 @@ define <vscale x 4 x i32> @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslide1up.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32(
@@ -746,8 +746,8 @@ define <vscale x 8 x i32> @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vslide1up.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32(
@@ -839,8 +839,8 @@ define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a1
-; CHECK-NEXT: vslide1up.vx v8, v25, a0
+; CHECK-NEXT: vslide1up.vx v9, v8, a1
+; CHECK-NEXT: vslide1up.vx v8, v9, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
@@ -864,10 +864,10 @@ define <vscale x 1 x i64> @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a3, a2, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v9, a1
-; CHECK-NEXT: vslide1up.vx v26, v25, a0
+; CHECK-NEXT: vslide1up.vx v10, v9, a1
+; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64(
@@ -890,8 +890,8 @@ define <vscale x 2 x i64> @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a1
-; CHECK-NEXT: vslide1up.vx v8, v26, a0
+; CHECK-NEXT: vslide1up.vx v10, v8, a1
+; CHECK-NEXT: vslide1up.vx v8, v10, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
@@ -915,10 +915,10 @@ define <vscale x 2 x i64> @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a3, a2, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v10, a1
-; CHECK-NEXT: vslide1up.vx v28, v26, a0
+; CHECK-NEXT: vslide1up.vx v12, v10, a1
+; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64(
@@ -941,8 +941,8 @@ define <vscale x 4 x i64> @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a1
-; CHECK-NEXT: vslide1up.vx v8, v28, a0
+; CHECK-NEXT: vslide1up.vx v12, v8, a1
+; CHECK-NEXT: vslide1up.vx v8, v12, a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
@@ -966,8 +966,8 @@ define <vscale x 4 x i64> @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: slli a3, a2, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v12, a1
-; CHECK-NEXT: vslide1up.vx v12, v28, a0
+; CHECK-NEXT: vslide1up.vx v16, v12, a1
+; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
index eaa7e934c5384..05800b4b7971d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i8> @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i8> @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i8> @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i8> @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8(<vscale x 1
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslide1up.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8(
@@ -240,8 +240,8 @@ define <vscale x 32 x i8> @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8(<vscale x 3
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vslide1up.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8(
@@ -332,8 +332,8 @@ define <vscale x 1 x i16> @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16(
@@ -378,8 +378,8 @@ define <vscale x 2 x i16> @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16(
@@ -424,8 +424,8 @@ define <vscale x 4 x i16> @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16(
@@ -470,8 +470,8 @@ define <vscale x 8 x i16> @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslide1up.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16(
@@ -516,8 +516,8 @@ define <vscale x 16 x i16> @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16(<vscale
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vslide1up.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16(
@@ -608,8 +608,8 @@ define <vscale x 1 x i32> @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32(
@@ -654,8 +654,8 @@ define <vscale x 2 x i32> @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32(
@@ -700,8 +700,8 @@ define <vscale x 4 x i32> @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslide1up.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32(
@@ -746,8 +746,8 @@ define <vscale x 8 x i32> @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vslide1up.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32(
@@ -838,8 +838,8 @@ define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vslide1up.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vslide1up.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
@@ -884,8 +884,8 @@ define <vscale x 2 x i64> @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vslide1up.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vslide1up.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
@@ -930,8 +930,8 @@ define <vscale x 4 x i64> @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vslide1up.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vslide1up.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
index 51a15cd9b2059..2736ac8d2cc6e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
@@ -103,8 +103,8 @@ define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vsc
; CHECK-LABEL: test_vsetvli_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
@@ -124,8 +124,8 @@ define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vsc
; CHECK-LABEL: test_vsetvli_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
index a0fba4301bb4d..2547cf3386f18 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
@@ -103,8 +103,8 @@ define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vsc
; CHECK-LABEL: test_vsetvli_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
@@ -124,8 +124,8 @@ define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vsc
; CHECK-LABEL: test_vsetvli_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: vmseq.vv v8, v8, v9
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
index 61eed5f8c6a3e..caaecbba2bb86 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsmul.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsmul.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vsmul.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsmul.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsmul.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vsmul.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsmul.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsmul.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vsmul.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
index 72d6e9c1ef1d4..686cabbd44a56 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
@@ -9,10 +9,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
@@ -23,10 +23,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -40,10 +40,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16* %base
; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
@@ -54,10 +54,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -100,10 +100,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -114,10 +114,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -131,10 +131,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -145,10 +145,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -162,10 +162,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -176,10 +176,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -870,10 +870,10 @@ define void @test_vsoxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
@@ -884,10 +884,10 @@ define void @test_vsoxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -1122,10 +1122,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -1136,10 +1136,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -1153,10 +1153,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -1167,10 +1167,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -1184,10 +1184,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -1198,10 +1198,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -1863,10 +1863,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -1877,10 +1877,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -1894,10 +1894,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -1908,10 +1908,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -2602,10 +2602,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -2616,10 +2616,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -2633,10 +2633,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -2647,10 +2647,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -2664,10 +2664,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -2678,10 +2678,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -3343,10 +3343,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -3357,10 +3357,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -3374,10 +3374,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -3388,10 +3388,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -3655,10 +3655,10 @@ define void @test_vsoxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -3669,10 +3669,10 @@ define void @test_vsoxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4363,10 +4363,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -4377,10 +4377,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4394,10 +4394,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -4408,10 +4408,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4425,10 +4425,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
@@ -4439,10 +4439,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4456,10 +4456,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -4470,10 +4470,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -4487,10 +4487,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -4501,10 +4501,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -5195,10 +5195,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -5209,10 +5209,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -5226,10 +5226,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -5240,10 +5240,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -5257,10 +5257,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -5271,10 +5271,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -5965,10 +5965,10 @@ define void @test_vsoxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
@@ -5979,10 +5979,10 @@ define void @test_vsoxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
@@ -5996,10 +5996,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -6010,10 +6010,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6027,10 +6027,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -6041,10 +6041,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6058,10 +6058,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -6072,10 +6072,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6737,10 +6737,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -6751,10 +6751,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6768,10 +6768,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -6782,10 +6782,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6799,10 +6799,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -6813,10 +6813,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -7478,10 +7478,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -7492,10 +7492,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7509,10 +7509,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -7523,10 +7523,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7540,10 +7540,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
@@ -7554,10 +7554,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7763,10 +7763,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %b
; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
@@ -7777,10 +7777,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, hal
; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -7794,10 +7794,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %ba
; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
@@ -7808,10 +7808,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half
; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -7854,10 +7854,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -7868,10 +7868,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7885,10 +7885,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %b
; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -7899,10 +7899,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, doubl
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7916,10 +7916,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
@@ -7930,10 +7930,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7947,10 +7947,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %b
; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -7961,10 +7961,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, doubl
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -7978,10 +7978,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -7992,10 +7992,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -8009,10 +8009,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -8023,10 +8023,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -8688,10 +8688,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -8702,10 +8702,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -8719,10 +8719,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -8733,10 +8733,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -8750,10 +8750,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -8764,10 +8764,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -9429,10 +9429,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -9443,10 +9443,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -9460,10 +9460,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -9474,10 +9474,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -9491,10 +9491,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -9505,10 +9505,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10170,10 +10170,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -10184,10 +10184,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10201,10 +10201,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -10215,10 +10215,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10232,10 +10232,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -10246,10 +10246,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10911,10 +10911,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -10925,10 +10925,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -10942,10 +10942,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -10956,10 +10956,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11194,10 +11194,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -11208,10 +11208,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11225,10 +11225,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -11239,10 +11239,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11256,10 +11256,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
@@ -11270,10 +11270,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11287,10 +11287,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -11301,10 +11301,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -11318,10 +11318,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %b
; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -11332,10 +11332,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, doubl
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -11349,10 +11349,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -11363,10 +11363,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -11572,10 +11572,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -11586,10 +11586,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -11603,10 +11603,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -11617,10 +11617,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -12311,10 +12311,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -12325,10 +12325,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -12342,10 +12342,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -12356,10 +12356,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -12373,10 +12373,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -12387,10 +12387,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -13052,10 +13052,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -13066,10 +13066,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -13083,10 +13083,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -13097,10 +13097,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -13114,10 +13114,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
@@ -13128,10 +13128,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
index b1a94bfe1920a..d499471d57023 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
@@ -9,10 +9,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
@@ -23,10 +23,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -40,10 +40,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16* %base
; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
@@ -54,10 +54,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -100,10 +100,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -114,10 +114,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -131,10 +131,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -145,10 +145,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -191,10 +191,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -205,10 +205,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -507,10 +507,10 @@ define void @test_vsoxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
@@ -521,10 +521,10 @@ define void @test_vsoxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -759,10 +759,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -773,10 +773,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -790,10 +790,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -804,10 +804,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -821,10 +821,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -835,10 +835,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -852,10 +852,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -866,10 +866,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1747,10 +1747,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -1761,10 +1761,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1778,10 +1778,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -1792,10 +1792,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1809,10 +1809,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -1823,10 +1823,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1840,10 +1840,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -1854,10 +1854,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -2735,10 +2735,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -2749,10 +2749,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -2766,10 +2766,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -2780,10 +2780,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -3140,10 +3140,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -3154,10 +3154,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -3200,10 +3200,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -3214,10 +3214,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -4095,10 +4095,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -4109,10 +4109,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -4126,10 +4126,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -4140,10 +4140,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -4157,10 +4157,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -4171,10 +4171,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -4188,10 +4188,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -4202,10 +4202,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -5083,10 +5083,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -5097,10 +5097,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -5114,10 +5114,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -5128,10 +5128,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -5145,10 +5145,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -5159,10 +5159,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -6098,10 +6098,10 @@ define void @test_vsoxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -6112,10 +6112,10 @@ define void @test_vsoxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -7051,10 +7051,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -7065,10 +7065,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7082,10 +7082,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -7096,10 +7096,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7113,10 +7113,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
@@ -7127,10 +7127,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7144,10 +7144,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -7158,10 +7158,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7204,10 +7204,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -7218,10 +7218,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7264,10 +7264,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -7278,10 +7278,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -8159,10 +8159,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -8173,10 +8173,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -8190,10 +8190,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -8204,10 +8204,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -8221,10 +8221,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -8235,10 +8235,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -8252,10 +8252,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -8266,10 +8266,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -9147,10 +9147,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -9161,10 +9161,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -9178,10 +9178,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -9192,10 +9192,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -9209,10 +9209,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsoxseg2_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -9223,10 +9223,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -10133,10 +10133,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -10147,10 +10147,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -10164,10 +10164,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -10178,10 +10178,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -10224,10 +10224,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
@@ -10238,10 +10238,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -10284,10 +10284,10 @@ define void @test_vsoxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
@@ -10298,10 +10298,10 @@ define void @test_vsoxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
@@ -10315,10 +10315,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -10329,10 +10329,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -10346,10 +10346,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -10360,10 +10360,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -10377,10 +10377,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -10391,10 +10391,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11301,10 +11301,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -11315,10 +11315,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11332,10 +11332,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <
; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -11346,10 +11346,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %ba
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11363,10 +11363,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -11377,10 +11377,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11394,10 +11394,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
@@ -11408,10 +11408,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %b
; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11681,10 +11681,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %b
; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
@@ -11695,10 +11695,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, hal
; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -11712,10 +11712,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %ba
; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
@@ -11726,10 +11726,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half
; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -11772,10 +11772,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -11786,10 +11786,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11803,10 +11803,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %b
; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -11817,10 +11817,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, doubl
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11834,10 +11834,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
@@ -11848,10 +11848,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i64(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11865,10 +11865,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -11879,10 +11879,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11896,10 +11896,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -11910,10 +11910,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -11927,10 +11927,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -11941,10 +11941,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -11958,10 +11958,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -11972,10 +11972,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -11989,10 +11989,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %b
; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -12003,10 +12003,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, doubl
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -12884,10 +12884,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -12898,10 +12898,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -12915,10 +12915,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -12929,10 +12929,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -12946,10 +12946,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -12960,10 +12960,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -13870,10 +13870,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -13884,10 +13884,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -13901,10 +13901,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -13915,10 +13915,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -13932,10 +13932,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -13946,10 +13946,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -13963,10 +13963,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -13977,10 +13977,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14858,10 +14858,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -14872,10 +14872,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14889,10 +14889,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -14903,10 +14903,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14920,10 +14920,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -14934,10 +14934,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14951,10 +14951,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -14965,10 +14965,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -15846,10 +15846,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -15860,10 +15860,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -15877,10 +15877,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -15891,10 +15891,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16222,10 +16222,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -16236,10 +16236,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16253,10 +16253,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -16267,10 +16267,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16313,10 +16313,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
@@ -16327,10 +16327,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16344,10 +16344,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -16358,10 +16358,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16375,10 +16375,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %b
; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -16389,10 +16389,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, doubl
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16406,10 +16406,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -16420,10 +16420,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16437,10 +16437,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
@@ -16451,10 +16451,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16753,10 +16753,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -16767,10 +16767,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -16813,10 +16813,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -16827,10 +16827,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -17708,10 +17708,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -17722,10 +17722,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -17739,10 +17739,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base,
; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -17753,10 +17753,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -17770,10 +17770,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -17784,10 +17784,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -18694,10 +18694,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -18708,10 +18708,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -18725,10 +18725,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %bas
; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -18739,10 +18739,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float*
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -18785,10 +18785,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -18799,10 +18799,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
index 974ea638750aa..29073eb2c8fd5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
@@ -29,8 +29,8 @@ define <vscale x 1 x i1> @vsplat_nxv1i1_2(i1 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> undef, i1 %x, i32 0
%splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
@@ -43,8 +43,8 @@ define <vscale x 1 x i1> @vsplat_nxv1i1_3(i32 signext %x, i32 signext %y) {
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%c = icmp ne i32 %x, %y
%head = insertelement <vscale x 1 x i1> undef, i1 %c, i32 0
@@ -79,8 +79,8 @@ define <vscale x 2 x i1> @vsplat_nxv2i1_2(i1 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> undef, i1 %x, i32 0
%splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
@@ -114,8 +114,8 @@ define <vscale x 4 x i1> @vsplat_nxv4i1_2(i1 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> undef, i1 %x, i32 0
%splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
@@ -149,8 +149,8 @@ define <vscale x 8 x i1> @vsplat_nxv8i1_2(i1 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v25, a0
-; CHECK-NEXT: vmsne.vi v0, v25, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> undef, i1 %x, i32 0
%splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
@@ -184,8 +184,8 @@ define <vscale x 16 x i1> @vsplat_nxv16i1_2(i1 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vmsne.vi v0, v26, 0
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> undef, i1 %x, i32 0
%splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
index f86ba341ef4df..32a351f3a766e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
@@ -10,13 +10,13 @@ define <vscale x 8 x i7> @vsra_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK-LABEL: vsra_vx_nxv8i7:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vv v25, v8, v8
-; CHECK-NEXT: vsra.vi v25, v25, 1
-; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: addi a0, zero, 127
-; CHECK-NEXT: vand.vx v26, v26, a0
+; CHECK-NEXT: vand.vx v9, v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsra.vv v8, v25, v26, v0.t
+; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> undef, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
index bb35b36132fda..24c6497a0a644 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
@@ -11,11 +11,11 @@ define <vscale x 8 x i7> @vsrl_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 127
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, mu
-; CHECK-NEXT: vand.vx v25, v8, a2
-; CHECK-NEXT: vmv.v.x v26, a0
-; CHECK-NEXT: vand.vx v26, v26, a2
+; CHECK-NEXT: vand.vx v8, v8, a2
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vand.vx v9, v9, a2
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsrl.vv v8, v25, v26, v0.t
+; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i7> undef, i7 %b, i32 0
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
index 73c9670d83cbe..d79d235d7dfdf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vssub.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vssub.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vssub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vssub.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vssub.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vssub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vssub.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vssub.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
index 102d562cdfe2a..dd3f5c630e0fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
@@ -691,8 +691,8 @@ define <vscale x 1 x i64> @ssub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -741,8 +741,8 @@ define <vscale x 2 x i64> @ssub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -791,8 +791,8 @@ define <vscale x 4 x i64> @ssub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vssub.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
index 9ac0944f13a1f..d3eeb06981798 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vssubu.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vssubu.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vssubu.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vssubu.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vssubu.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vssubu.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
index 3e64fa8e535e5..d8a3989cb04e4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
@@ -691,8 +691,8 @@ define <vscale x 1 x i64> @usub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v25
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -741,8 +741,8 @@ define <vscale x 2 x i64> @usub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v26
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -791,8 +791,8 @@ define <vscale x 4 x i64> @usub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
-; RV32-NEXT: vssubu.vv v8, v8, v28
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
index b247135d34dbe..536d4223cf95c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
index 32f5b5b987910..88f972424d4f5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
@@ -665,8 +665,8 @@ define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -707,8 +707,8 @@ define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -749,8 +749,8 @@ define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
index 499d1ca4064be..d4818c7514049 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
@@ -1001,9 +1001,9 @@ define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v25, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1027,9 +1027,9 @@ define <vscale x 1 x i64> @vsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v25
+; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1079,9 +1079,9 @@ define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v26, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1105,9 +1105,9 @@ define <vscale x 2 x i64> @vsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v26
+; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1157,9 +1157,9 @@ define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v28, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1183,9 +1183,9 @@ define <vscale x 4 x i64> @vsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vsub.vv v8, v8, v28
+; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
index ba9db863b0e31..690ec3b4c466a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
@@ -9,10 +9,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
@@ -23,10 +23,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -40,10 +40,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16* %base
; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
@@ -54,10 +54,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -100,10 +100,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -114,10 +114,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -131,10 +131,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -145,10 +145,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -162,10 +162,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -176,10 +176,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -870,10 +870,10 @@ define void @test_vsuxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
@@ -884,10 +884,10 @@ define void @test_vsuxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -1122,10 +1122,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -1136,10 +1136,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -1153,10 +1153,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -1167,10 +1167,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -1184,10 +1184,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -1198,10 +1198,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -1863,10 +1863,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -1877,10 +1877,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -1894,10 +1894,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -1908,10 +1908,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -2602,10 +2602,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -2616,10 +2616,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -2633,10 +2633,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -2647,10 +2647,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -2664,10 +2664,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -2678,10 +2678,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -3343,10 +3343,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -3357,10 +3357,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -3374,10 +3374,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -3388,10 +3388,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -3655,10 +3655,10 @@ define void @test_vsuxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -3669,10 +3669,10 @@ define void @test_vsuxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4363,10 +4363,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -4377,10 +4377,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4394,10 +4394,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -4408,10 +4408,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4425,10 +4425,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
@@ -4439,10 +4439,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -4456,10 +4456,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -4470,10 +4470,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -4487,10 +4487,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -4501,10 +4501,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -5195,10 +5195,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -5209,10 +5209,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -5226,10 +5226,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -5240,10 +5240,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -5257,10 +5257,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -5271,10 +5271,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -5965,10 +5965,10 @@ define void @test_vsuxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
@@ -5979,10 +5979,10 @@ define void @test_vsuxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
@@ -5996,10 +5996,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -6010,10 +6010,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6027,10 +6027,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -6041,10 +6041,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6058,10 +6058,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -6072,10 +6072,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6737,10 +6737,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -6751,10 +6751,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6768,10 +6768,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -6782,10 +6782,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -6799,10 +6799,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -6813,10 +6813,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -7478,10 +7478,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -7492,10 +7492,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7509,10 +7509,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -7523,10 +7523,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7540,10 +7540,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
@@ -7554,10 +7554,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7763,10 +7763,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %b
; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
@@ -7777,10 +7777,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, hal
; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -7794,10 +7794,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %ba
; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
@@ -7808,10 +7808,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half
; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
@@ -7854,10 +7854,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -7868,10 +7868,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7885,10 +7885,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %b
; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -7899,10 +7899,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, doubl
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7916,10 +7916,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
@@ -7930,10 +7930,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -7947,10 +7947,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %b
; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -7961,10 +7961,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, doubl
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -7978,10 +7978,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -7992,10 +7992,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -8009,10 +8009,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -8023,10 +8023,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -8688,10 +8688,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -8702,10 +8702,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -8719,10 +8719,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -8733,10 +8733,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -8750,10 +8750,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -8764,10 +8764,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -9429,10 +9429,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -9443,10 +9443,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -9460,10 +9460,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -9474,10 +9474,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -9491,10 +9491,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -9505,10 +9505,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10170,10 +10170,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
@@ -10184,10 +10184,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10201,10 +10201,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
@@ -10215,10 +10215,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10232,10 +10232,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
@@ -10246,10 +10246,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
@@ -10911,10 +10911,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -10925,10 +10925,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -10942,10 +10942,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -10956,10 +10956,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11194,10 +11194,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
@@ -11208,10 +11208,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11225,10 +11225,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
@@ -11239,10 +11239,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11256,10 +11256,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
@@ -11270,10 +11270,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
@@ -11287,10 +11287,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -11301,10 +11301,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -11318,10 +11318,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %b
; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -11332,10 +11332,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, doubl
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -11349,10 +11349,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -11363,10 +11363,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -11572,10 +11572,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -11586,10 +11586,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -11603,10 +11603,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -11617,10 +11617,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -12311,10 +12311,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
@@ -12325,10 +12325,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -12342,10 +12342,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
@@ -12356,10 +12356,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -12373,10 +12373,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
@@ -12387,10 +12387,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
@@ -13052,10 +13052,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
@@ -13066,10 +13066,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -13083,10 +13083,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
@@ -13097,10 +13097,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
@@ -13114,10 +13114,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
@@ -13128,10 +13128,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
index f89f8ab96b796..b0c4c51ea7389 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
@@ -9,10 +9,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
@@ -23,10 +23,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -40,10 +40,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16* %base
; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
@@ -54,10 +54,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -100,10 +100,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -114,10 +114,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -131,10 +131,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -145,10 +145,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -191,10 +191,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -205,10 +205,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -507,10 +507,10 @@ define void @test_vsuxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
@@ -521,10 +521,10 @@ define void @test_vsuxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -759,10 +759,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -773,10 +773,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -790,10 +790,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -804,10 +804,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -821,10 +821,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -835,10 +835,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -852,10 +852,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -866,10 +866,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1747,10 +1747,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -1761,10 +1761,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1778,10 +1778,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -1792,10 +1792,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1809,10 +1809,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -1823,10 +1823,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -1840,10 +1840,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -1854,10 +1854,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -2735,10 +2735,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -2749,10 +2749,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -2766,10 +2766,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -2780,10 +2780,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -3140,10 +3140,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -3154,10 +3154,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -3200,10 +3200,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -3214,10 +3214,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -4095,10 +4095,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -4109,10 +4109,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -4126,10 +4126,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -4140,10 +4140,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -4157,10 +4157,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -4171,10 +4171,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -4188,10 +4188,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -4202,10 +4202,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -5083,10 +5083,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -5097,10 +5097,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -5114,10 +5114,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -5128,10 +5128,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -5145,10 +5145,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -5159,10 +5159,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -6098,10 +6098,10 @@ define void @test_vsuxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -6112,10 +6112,10 @@ define void @test_vsuxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -7051,10 +7051,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -7065,10 +7065,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7082,10 +7082,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -7096,10 +7096,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7113,10 +7113,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
@@ -7127,10 +7127,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7144,10 +7144,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -7158,10 +7158,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7204,10 +7204,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -7218,10 +7218,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -7264,10 +7264,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -7278,10 +7278,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -8159,10 +8159,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -8173,10 +8173,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -8190,10 +8190,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -8204,10 +8204,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -8221,10 +8221,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -8235,10 +8235,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -8252,10 +8252,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -8266,10 +8266,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -9147,10 +9147,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -9161,10 +9161,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -9178,10 +9178,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vsc
; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -9192,10 +9192,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base,
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -9209,10 +9209,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vs
; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -9223,10 +9223,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -10133,10 +10133,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -10147,10 +10147,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -10164,10 +10164,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -10178,10 +10178,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -10224,10 +10224,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
@@ -10238,10 +10238,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -10284,10 +10284,10 @@ define void @test_vsuxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
@@ -10298,10 +10298,10 @@ define void @test_vsuxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
@@ -10315,10 +10315,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -10329,10 +10329,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -10346,10 +10346,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -10360,10 +10360,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -10377,10 +10377,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -10391,10 +10391,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11301,10 +11301,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -11315,10 +11315,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11332,10 +11332,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <
; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -11346,10 +11346,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %ba
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11363,10 +11363,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -11377,10 +11377,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11394,10 +11394,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
@@ -11408,10 +11408,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %b
; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -11681,10 +11681,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %b
; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
@@ -11695,10 +11695,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, hal
; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -11712,10 +11712,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %ba
; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
@@ -11726,10 +11726,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half
; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
@@ -11772,10 +11772,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -11786,10 +11786,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11803,10 +11803,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %b
; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -11817,10 +11817,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, doubl
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11834,10 +11834,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
@@ -11848,10 +11848,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i64(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11865,10 +11865,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -11879,10 +11879,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -11896,10 +11896,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -11910,10 +11910,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -11927,10 +11927,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -11941,10 +11941,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -11958,10 +11958,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -11972,10 +11972,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -11989,10 +11989,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %b
; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -12003,10 +12003,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, doubl
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -12884,10 +12884,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -12898,10 +12898,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -12915,10 +12915,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -12929,10 +12929,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -12946,10 +12946,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -12960,10 +12960,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -13870,10 +13870,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -13884,10 +13884,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -13901,10 +13901,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -13915,10 +13915,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -13932,10 +13932,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -13946,10 +13946,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -13963,10 +13963,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -13977,10 +13977,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14858,10 +14858,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
@@ -14872,10 +14872,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14889,10 +14889,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
@@ -14903,10 +14903,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14920,10 +14920,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
@@ -14934,10 +14934,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -14951,10 +14951,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
@@ -14965,10 +14965,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
@@ -15846,10 +15846,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -15860,10 +15860,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -15877,10 +15877,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -15891,10 +15891,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16222,10 +16222,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
@@ -16236,10 +16236,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv2r.v v26, v12
+; CHECK-NEXT: vmv2r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16253,10 +16253,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
@@ -16267,10 +16267,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv1r.v v25, v12
+; CHECK-NEXT: vmv1r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16313,10 +16313,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
@@ -16327,10 +16327,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
@@ -16344,10 +16344,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -16358,10 +16358,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16375,10 +16375,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %b
; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -16389,10 +16389,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, doubl
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16406,10 +16406,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -16420,10 +16420,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16437,10 +16437,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %
; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
@@ -16451,10 +16451,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, doub
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -16753,10 +16753,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -16767,10 +16767,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -16813,10 +16813,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -16827,10 +16827,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -17708,10 +17708,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
@@ -17722,10 +17722,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -17739,10 +17739,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base,
; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
@@ -17753,10 +17753,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -17770,10 +17770,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base
; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
@@ -17784,10 +17784,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half*
; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT: vmv1r.v v25, v9
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v9, v8
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
@@ -18694,10 +18694,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
@@ -18708,10 +18708,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv2r.v v26, v10
+; CHECK-NEXT: vmv2r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -18725,10 +18725,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %bas
; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
@@ -18739,10 +18739,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float*
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
@@ -18785,10 +18785,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %ba
; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
@@ -18799,10 +18799,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float
; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT: vmv1r.v v25, v10
+; CHECK-NEXT: vmv1r.v v12, v10
; CHECK-NEXT: vmv2r.v v10, v8
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
index 26f4bb49c6947..d359263def2e9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
@@ -35,8 +35,8 @@ define <vscale x 8 x i8> @vtrunc_nxv8i16_nxv8i8(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i16> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec
@@ -46,8 +46,8 @@ define <vscale x 16 x i8> @vtrunc_nxv16i16_nxv16i8(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i16> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %tvec
@@ -57,9 +57,9 @@ define <vscale x 1 x i8> @vtrunc_nxv1i32_nxv1i8(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
@@ -79,9 +79,9 @@ define <vscale x 2 x i8> @vtrunc_nxv2i32_nxv2i8(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec
@@ -101,9 +101,9 @@ define <vscale x 4 x i8> @vtrunc_nxv4i32_nxv4i8(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec
@@ -113,8 +113,8 @@ define <vscale x 4 x i16> @vtrunc_nxv4i32_nxv4i16(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %tvec
@@ -124,9 +124,9 @@ define <vscale x 8 x i8> @vtrunc_nxv8i32_nxv8i8(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec
@@ -136,8 +136,8 @@ define <vscale x 8 x i16> @vtrunc_nxv8i32_nxv8i16(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %tvec
@@ -147,9 +147,9 @@ define <vscale x 16 x i8> @vtrunc_nxv16i32_nxv16i8(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %tvec
@@ -159,8 +159,8 @@ define <vscale x 16 x i16> @vtrunc_nxv16i32_nxv16i16(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %tvec
@@ -170,11 +170,11 @@ define <vscale x 1 x i8> @vtrunc_nxv1i64_nxv1i8(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
@@ -184,9 +184,9 @@ define <vscale x 1 x i16> @vtrunc_nxv1i64_nxv1i16(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %tvec
@@ -206,11 +206,11 @@ define <vscale x 2 x i8> @vtrunc_nxv2i64_nxv2i8(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec
@@ -220,9 +220,9 @@ define <vscale x 2 x i16> @vtrunc_nxv2i64_nxv2i16(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %tvec
@@ -232,8 +232,8 @@ define <vscale x 2 x i32> @vtrunc_nxv2i64_nxv2i32(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %tvec
@@ -243,11 +243,11 @@ define <vscale x 4 x i8> @vtrunc_nxv4i64_nxv4i8(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec
@@ -257,9 +257,9 @@ define <vscale x 4 x i16> @vtrunc_nxv4i64_nxv4i16(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %tvec
@@ -269,8 +269,8 @@ define <vscale x 4 x i32> @vtrunc_nxv4i64_nxv4i32(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %tvec
@@ -280,11 +280,11 @@ define <vscale x 8 x i8> @vtrunc_nxv8i64_nxv8i8(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v28, 0
+; CHECK-NEXT: vnsrl.wi v10, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec
@@ -294,9 +294,9 @@ define <vscale x 8 x i16> @vtrunc_nxv8i64_nxv8i16(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %tvec
@@ -306,8 +306,8 @@ define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %tvec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
index d204f44fadd1a..138f1e6f805f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
@@ -35,8 +35,8 @@ define <vscale x 8 x i8> @vtrunc_nxv8i16_nxv8i8(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i16> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec
@@ -46,8 +46,8 @@ define <vscale x 16 x i8> @vtrunc_nxv16i16_nxv16i8(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i16> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %tvec
@@ -57,9 +57,9 @@ define <vscale x 1 x i8> @vtrunc_nxv1i32_nxv1i8(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
@@ -79,9 +79,9 @@ define <vscale x 2 x i8> @vtrunc_nxv2i32_nxv2i8(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec
@@ -101,9 +101,9 @@ define <vscale x 4 x i8> @vtrunc_nxv4i32_nxv4i8(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec
@@ -113,8 +113,8 @@ define <vscale x 4 x i16> @vtrunc_nxv4i32_nxv4i16(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %tvec
@@ -124,9 +124,9 @@ define <vscale x 8 x i8> @vtrunc_nxv8i32_nxv8i8(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec
@@ -136,8 +136,8 @@ define <vscale x 8 x i16> @vtrunc_nxv8i32_nxv8i16(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %tvec
@@ -147,9 +147,9 @@ define <vscale x 16 x i8> @vtrunc_nxv16i32_nxv16i8(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i8>
ret <vscale x 16 x i8> %tvec
@@ -159,8 +159,8 @@ define <vscale x 16 x i16> @vtrunc_nxv16i32_nxv16i16(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %tvec
@@ -170,11 +170,11 @@ define <vscale x 1 x i8> @vtrunc_nxv1i64_nxv1i8(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>
ret <vscale x 1 x i8> %tvec
@@ -184,9 +184,9 @@ define <vscale x 1 x i16> @vtrunc_nxv1i64_nxv1i16(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %tvec
@@ -206,11 +206,11 @@ define <vscale x 2 x i8> @vtrunc_nxv2i64_nxv2i8(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>
ret <vscale x 2 x i8> %tvec
@@ -220,9 +220,9 @@ define <vscale x 2 x i16> @vtrunc_nxv2i64_nxv2i16(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %tvec
@@ -232,8 +232,8 @@ define <vscale x 2 x i32> @vtrunc_nxv2i64_nxv2i32(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v8, 0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vnsrl.wi v10, v8, 0
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %tvec
@@ -243,11 +243,11 @@ define <vscale x 4 x i8> @vtrunc_nxv4i64_nxv4i8(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v25, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v25, 0
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i8>
ret <vscale x 4 x i8> %tvec
@@ -257,9 +257,9 @@ define <vscale x 4 x i16> @vtrunc_nxv4i64_nxv4i16(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %tvec
@@ -269,8 +269,8 @@ define <vscale x 4 x i32> @vtrunc_nxv4i64_nxv4i32(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v8, 0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vnsrl.wi v12, v8, 0
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %tvec
@@ -280,11 +280,11 @@ define <vscale x 8 x i8> @vtrunc_nxv8i64_nxv8i8(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v26, v28, 0
+; CHECK-NEXT: vnsrl.wi v10, v16, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v26, 0
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i8>
ret <vscale x 8 x i8> %tvec
@@ -294,9 +294,9 @@ define <vscale x 8 x i16> @vtrunc_nxv8i64_nxv8i16(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-NEXT: vnsrl.wi v8, v28, 0
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %tvec
@@ -306,8 +306,8 @@ define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; CHECK-NEXT: vnsrl.wi v28, v8, 0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vnsrl.wi v16, v8, 0
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %tvec
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
index 19e2d3459d681..f57bf32b789cd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwadd.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwadd.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwadd.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwadd.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
index fa250394fdab7..7ec1fa4e4a950 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8
; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwadd.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwadd.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwadd.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwadd.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
index ffc5bfce5077d..d88618fd7a66b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
index 916ee88c5cbba..9c383c2dfee96 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vs
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwadd.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwadd.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwadd.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwadd.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<v
; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwadd.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwadd.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
index 0480753c043c2..e42ccf233604b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwaddu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwaddu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwaddu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwaddu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwaddu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwaddu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwaddu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwaddu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
index f63f3db025507..f9ad3eb2a24ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwaddu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwaddu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwaddu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwaddu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwaddu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwaddu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwaddu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwaddu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
index d904716bce829..0ffeabaa38290 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwaddu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwaddu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwaddu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwaddu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwaddu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwaddu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwaddu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwaddu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
index 4a35416acf0c5..044737e1e3007 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwaddu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwaddu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwaddu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwaddu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<v
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwaddu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwaddu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwaddu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwaddu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwaddu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwaddu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwaddu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwaddu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<
; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwaddu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwaddu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
index b04e2c0d171fc..47ecba522f2fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwmul.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwmul.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwmul.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwmul.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwmul.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwmul.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
index 0e8567dcfdc8a..05bdcf70f5480 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwmul.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwmul.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwmul.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8
; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwmul.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwmul.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwmul.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwmul.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwmul.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmul.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwmul.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmul.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwmul.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmul.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
index b3cc2e7d13557..0d91f668b792d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8(<vscal
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16(<vscale x 2
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16(<vscale x 4
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16(<vscale x 8
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
index d121b66424af7..4ac17a317522a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8(<vscal
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16(<vscale x 2
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16(<vscale x 4
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16(<vscale x 8
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulsu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32(<vscale x 2
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwmulsu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulsu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32(<vscale x 4
; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwmulsu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulsu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
index f2ee2f583ff39..9f46f19b99386 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwmulu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwmulu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwmulu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwmulu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwmulu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwmulu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwmulu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwmulu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwmulu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwmulu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwmulu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwmulu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
index ba274eed8e389..99a0d2183133a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwmulu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwmulu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwmulu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwmulu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwmulu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwmulu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwmulu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwmulu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmulu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmulu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwmulu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmulu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwmulu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmulu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwmulu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwmulu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmulu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwmulu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwmulu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmulu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwmulu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwmulu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
index 9dd180c412f5d..82b59dc788f5a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwsub.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwsub.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwsub.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwsub.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
index 904e8ee4cae14..9aac53ae44b5c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8
; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwsub.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwsub.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwsub.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwsub.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
index 3ee54535f7f33..42c6411fa4d65 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
index 5ef9b77be484b..1257f5a546307 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vs
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsub.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsub.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsub.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsub.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<v
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsub.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsub.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
index 1292599d6ea74..acee77f9bbd01 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsubu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsubu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsubu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsubu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwsubu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwsubu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwsubu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwsubu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
index 40d197de57b56..65a7c23e6225c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
@@ -10,8 +10,8 @@ define <vscale x 1 x i16> @intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8(
@@ -56,8 +56,8 @@ define <vscale x 2 x i16> @intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8(
@@ -102,8 +102,8 @@ define <vscale x 4 x i16> @intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8(
@@ -148,8 +148,8 @@ define <vscale x 8 x i16> @intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsubu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.nxv8i16.nxv8i8.nxv8i8(
@@ -194,8 +194,8 @@ define <vscale x 16 x i16> @intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsubu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.nxv16i16.nxv16i8.nxv16i8(
@@ -286,8 +286,8 @@ define <vscale x 1 x i32> @intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.nxv1i32.nxv1i16.nxv1i16(
@@ -332,8 +332,8 @@ define <vscale x 2 x i32> @intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.nxv2i32.nxv2i16.nxv2i16(
@@ -378,8 +378,8 @@ define <vscale x 4 x i32> @intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsubu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.nxv4i32.nxv4i16.nxv4i16(
@@ -424,8 +424,8 @@ define <vscale x 8 x i32> @intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsubu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.nxv8i32.nxv8i16.nxv8i16(
@@ -516,8 +516,8 @@ define <vscale x 1 x i64> @intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vv v25, v8, v9
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.nxv1i64.nxv1i32.nxv1i32(
@@ -562,8 +562,8 @@ define <vscale x 2 x i64> @intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.vv v26, v8, v9
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vv v10, v8, v9
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.nxv2i64.nxv2i32.nxv2i32(
@@ -608,8 +608,8 @@ define <vscale x 4 x i64> @intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.vv v28, v8, v10
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vv v12, v8, v10
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32(
@@ -700,8 +700,8 @@ define <vscale x 1 x i16> @intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8(
@@ -746,8 +746,8 @@ define <vscale x 2 x i16> @intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8(
@@ -792,8 +792,8 @@ define <vscale x 4 x i16> @intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8(
@@ -838,8 +838,8 @@ define <vscale x 8 x i16> @intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vwsubu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.nxv8i16.nxv8i8.i8(
@@ -884,8 +884,8 @@ define <vscale x 16 x i16> @intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vwsubu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.nxv16i16.nxv16i8.i8(
@@ -976,8 +976,8 @@ define <vscale x 1 x i32> @intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.nxv1i32.nxv1i16.i16(
@@ -1022,8 +1022,8 @@ define <vscale x 2 x i32> @intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.nxv2i32.nxv2i16.i16(
@@ -1068,8 +1068,8 @@ define <vscale x 4 x i32> @intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vwsubu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.nxv4i32.nxv4i16.i16(
@@ -1114,8 +1114,8 @@ define <vscale x 8 x i32> @intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vwsubu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.nxv8i32.nxv8i16.i16(
@@ -1206,8 +1206,8 @@ define <vscale x 1 x i64> @intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.vx v25, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.nxv1i64.nxv1i32.i32(
@@ -1252,8 +1252,8 @@ define <vscale x 2 x i64> @intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.vx v26, v8, a0
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.nxv2i64.nxv2i32.i32(
@@ -1298,8 +1298,8 @@ define <vscale x 4 x i64> @intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.vx v28, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.vx v12, v8, a0
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
index f821f81508401..7a4ac1c97e4be 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsubu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsubu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsubu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsubu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
index 7272d7ee6fcfe..4de4be003f58a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
@@ -257,9 +257,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4r.v v28, (a0)
+; CHECK-NEXT: vl4r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
@@ -483,9 +483,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re16.v v28, (a0)
+; CHECK-NEXT: vl4re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
@@ -664,9 +664,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(
define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl4re32.v v28, (a0)
+; CHECK-NEXT: vl4re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
+; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(
@@ -1868,8 +1868,8 @@ define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(
@@ -1884,8 +1884,8 @@ define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(
@@ -1900,8 +1900,8 @@ define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(
@@ -1916,8 +1916,8 @@ define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<v
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vwsubu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(
@@ -1932,8 +1932,8 @@ define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vwsubu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(
@@ -1964,8 +1964,8 @@ define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(
@@ -1980,8 +1980,8 @@ define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(
@@ -1996,8 +1996,8 @@ define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vwsubu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(
@@ -2012,8 +2012,8 @@ define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vwsubu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(
@@ -2028,8 +2028,8 @@ define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vwsubu.wv v25, v9, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vwsubu.wv v10, v9, v8
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(
@@ -2044,8 +2044,8 @@ define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vwsubu.wv v26, v10, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vwsubu.wv v12, v10, v8
+; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(
@@ -2060,8 +2060,8 @@ define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vwsubu.wv v28, v12, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vwsubu.wv v16, v12, v8
+; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
index e580e5533a532..418aee23c1363 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
@@ -1818,8 +1818,8 @@ define <vscale x 1 x i64> @intrinsic_vxor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vxor.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vxor.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1847,9 +1847,9 @@ define <vscale x 1 x i64> @intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
+; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: vxor.vv v8, v9, v25, v0.t
+; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1876,8 +1876,8 @@ define <vscale x 2 x i64> @intrinsic_vxor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vxor.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vxor.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1905,9 +1905,9 @@ define <vscale x 2 x i64> @intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
+; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: vxor.vv v8, v10, v26, v0.t
+; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1934,8 +1934,8 @@ define <vscale x 4 x i64> @intrinsic_vxor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vxor.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vxor.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
@@ -1963,9 +1963,9 @@ define <vscale x 4 x i64> @intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
+; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: vxor.vv v8, v12, v28, v0.t
+; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
index 6b518f25a74b7..05ef9b085f13f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
@@ -1082,8 +1082,8 @@ define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v25, (a0), zero
-; CHECK-NEXT: vxor.vv v8, v8, v25
+; CHECK-NEXT: vlse64.v v9, (a0), zero
+; CHECK-NEXT: vxor.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
@@ -1148,8 +1148,8 @@ define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v26, (a0), zero
-; CHECK-NEXT: vxor.vv v8, v8, v26
+; CHECK-NEXT: vlse64.v v10, (a0), zero
+; CHECK-NEXT: vxor.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
@@ -1214,8 +1214,8 @@ define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v28, (a0), zero
-; CHECK-NEXT: vxor.vv v8, v8, v28
+; CHECK-NEXT: vlse64.v v12, (a0), zero
+; CHECK-NEXT: vxor.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
index daf6cb5f15b09..7d7d67d673bd0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
@@ -1989,9 +1989,9 @@ define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v25, v0.t
+; RV32-NEXT: vxor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -2015,9 +2015,9 @@ define <vscale x 1 x i64> @vxor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v25, (a0), zero
+; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v25
+; RV32-NEXT: vxor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -2119,9 +2119,9 @@ define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v26, v0.t
+; RV32-NEXT: vxor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -2145,9 +2145,9 @@ define <vscale x 2 x i64> @vxor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v26, (a0), zero
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v26
+; RV32-NEXT: vxor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -2249,9 +2249,9 @@ define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v28, v0.t
+; RV32-NEXT: vxor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -2275,9 +2275,9 @@ define <vscale x 4 x i64> @vxor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v28, (a0), zero
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vxor.vv v8, v8, v28
+; RV32-NEXT: vxor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
index 3031b116c315d..57c8ad7ce5eb4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x i64> @intrinsic_vzext_vf8_nxv2i64(<vscale x 2 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x i64> @intrinsic_vzext_vf8_nxv4i64(<vscale x 4 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8(
@@ -177,8 +177,8 @@ define <vscale x 1 x i64> @intrinsic_vzext_vf4_nxv1i64(<vscale x 1 x i16> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16(
@@ -219,8 +219,8 @@ define <vscale x 2 x i64> @intrinsic_vzext_vf4_nxv2i64(<vscale x 2 x i16> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16(
@@ -261,8 +261,8 @@ define <vscale x 4 x i64> @intrinsic_vzext_vf4_nxv4i64(<vscale x 4 x i16> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16(
@@ -345,8 +345,8 @@ define <vscale x 1 x i32> @intrinsic_vzext_vf4_nxv1i32(<vscale x 1 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8(
@@ -387,8 +387,8 @@ define <vscale x 2 x i32> @intrinsic_vzext_vf4_nxv2i32(<vscale x 2 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8(
@@ -429,8 +429,8 @@ define <vscale x 4 x i32> @intrinsic_vzext_vf4_nxv4i32(<vscale x 4 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8(
@@ -471,8 +471,8 @@ define <vscale x 8 x i32> @intrinsic_vzext_vf4_nxv8i32(<vscale x 8 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8(
@@ -555,8 +555,8 @@ define <vscale x 1 x i64> @intrinsic_vzext_vf2_nxv1i64(<vscale x 1 x i32> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32(
@@ -597,8 +597,8 @@ define <vscale x 2 x i64> @intrinsic_vzext_vf2_nxv2i64(<vscale x 2 x i32> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32(
@@ -639,8 +639,8 @@ define <vscale x 4 x i64> @intrinsic_vzext_vf2_nxv4i64(<vscale x 4 x i32> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32(
@@ -723,8 +723,8 @@ define <vscale x 1 x i32> @intrinsic_vzext_vf2_nxv1i32(<vscale x 1 x i16> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16(
@@ -765,8 +765,8 @@ define <vscale x 2 x i32> @intrinsic_vzext_vf2_nxv2i32(<vscale x 2 x i16> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16(
@@ -807,8 +807,8 @@ define <vscale x 4 x i32> @intrinsic_vzext_vf2_nxv4i32(<vscale x 4 x i16> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16(
@@ -849,8 +849,8 @@ define <vscale x 8 x i32> @intrinsic_vzext_vf2_nxv8i32(<vscale x 8 x i16> %0, i3
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16(
@@ -933,8 +933,8 @@ define <vscale x 1 x i16> @intrinsic_vzext_vf2_nxv1i16(<vscale x 1 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8(
@@ -975,8 +975,8 @@ define <vscale x 2 x i16> @intrinsic_vzext_vf2_nxv2i16(<vscale x 2 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8(
@@ -1017,8 +1017,8 @@ define <vscale x 4 x i16> @intrinsic_vzext_vf2_nxv4i16(<vscale x 4 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8(
@@ -1059,8 +1059,8 @@ define <vscale x 8 x i16> @intrinsic_vzext_vf2_nxv8i16(<vscale x 8 x i8> %0, i32
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8(
@@ -1101,8 +1101,8 @@ define <vscale x 16 x i16> @intrinsic_vzext_vf2_nxv16i16(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
index df42a045534e6..f6c4aac0e22f7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
@@ -9,8 +9,8 @@ define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf8 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf8 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
@@ -51,8 +51,8 @@ define <vscale x 2 x i64> @intrinsic_vzext_vf8_nxv2i64(<vscale x 2 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf8 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8(
@@ -93,8 +93,8 @@ define <vscale x 4 x i64> @intrinsic_vzext_vf8_nxv4i64(<vscale x 4 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf8 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf8 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8(
@@ -177,8 +177,8 @@ define <vscale x 1 x i64> @intrinsic_vzext_vf4_nxv1i64(<vscale x 1 x i16> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16(
@@ -219,8 +219,8 @@ define <vscale x 2 x i64> @intrinsic_vzext_vf4_nxv2i64(<vscale x 2 x i16> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16(
@@ -261,8 +261,8 @@ define <vscale x 4 x i64> @intrinsic_vzext_vf4_nxv4i64(<vscale x 4 x i16> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16(
@@ -345,8 +345,8 @@ define <vscale x 1 x i32> @intrinsic_vzext_vf4_nxv1i32(<vscale x 1 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8(
@@ -387,8 +387,8 @@ define <vscale x 2 x i32> @intrinsic_vzext_vf4_nxv2i32(<vscale x 2 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf4 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf4 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8(
@@ -429,8 +429,8 @@ define <vscale x 4 x i32> @intrinsic_vzext_vf4_nxv4i32(<vscale x 4 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf4 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf4 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8(
@@ -471,8 +471,8 @@ define <vscale x 8 x i32> @intrinsic_vzext_vf4_nxv8i32(<vscale x 8 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf4 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf4 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8(
@@ -555,8 +555,8 @@ define <vscale x 1 x i64> @intrinsic_vzext_vf2_nxv1i64(<vscale x 1 x i32> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32(
@@ -597,8 +597,8 @@ define <vscale x 2 x i64> @intrinsic_vzext_vf2_nxv2i64(<vscale x 2 x i32> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32(
@@ -639,8 +639,8 @@ define <vscale x 4 x i64> @intrinsic_vzext_vf2_nxv4i64(<vscale x 4 x i32> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32(
@@ -723,8 +723,8 @@ define <vscale x 1 x i32> @intrinsic_vzext_vf2_nxv1i32(<vscale x 1 x i16> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16(
@@ -765,8 +765,8 @@ define <vscale x 2 x i32> @intrinsic_vzext_vf2_nxv2i32(<vscale x 2 x i16> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16(
@@ -807,8 +807,8 @@ define <vscale x 4 x i32> @intrinsic_vzext_vf2_nxv4i32(<vscale x 4 x i16> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16(
@@ -849,8 +849,8 @@ define <vscale x 8 x i32> @intrinsic_vzext_vf2_nxv8i32(<vscale x 8 x i16> %0, i6
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16(
@@ -933,8 +933,8 @@ define <vscale x 1 x i16> @intrinsic_vzext_vf2_nxv1i16(<vscale x 1 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8(
@@ -975,8 +975,8 @@ define <vscale x 2 x i16> @intrinsic_vzext_vf2_nxv2i16(<vscale x 2 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8(
@@ -1017,8 +1017,8 @@ define <vscale x 4 x i16> @intrinsic_vzext_vf2_nxv4i16(<vscale x 4 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vzext.vf2 v25, v8
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8(
@@ -1059,8 +1059,8 @@ define <vscale x 8 x i16> @intrinsic_vzext_vf2_nxv8i16(<vscale x 8 x i8> %0, i64
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vzext.vf2 v26, v8
-; CHECK-NEXT: vmv2r.v v8, v26
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8(
@@ -1101,8 +1101,8 @@ define <vscale x 16 x i16> @intrinsic_vzext_vf2_nxv16i16(<vscale x 16 x i8> %0,
; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vzext.vf2 v28, v8
-; CHECK-NEXT: vmv4r.v v8, v28
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8(
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
index 55c97c83fd450..98d1630053d16 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
@@ -187,10 +187,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
@@ -201,10 +201,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
-; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
@@ -218,10 +218,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
@@ -232,10 +232,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
-; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir b/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir
index 62e8b9f86dbfd..f4fb4a5bb8360 100644
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir
@@ -48,92 +48,116 @@ body: |
; RV32I-LABEL: name: cmov_interleaved_bad
; RV32I: successors: %bb.1, %bb.2
- ; RV32I: liveins: $x10, $x11, $x12, $x13
- ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV32I: .1:
- ; RV32I: .2:
- ; RV32I: successors: %bb.3, %bb.4
- ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
- ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4
- ; RV32I: .3:
- ; RV32I: .4:
- ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
- ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV32I: $x10 = COPY [[ADD]]
- ; RV32I: PseudoRET implicit $x10
+ ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: .1:
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: .2:
+ ; RV32I-NEXT: successors: %bb.3, %bb.4
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
+ ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: .3:
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: .4:
+ ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
+ ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV32I-NEXT: $x10 = COPY [[ADD]]
+ ; RV32I-NEXT: PseudoRET implicit $x10
; RV32IBT-LABEL: name: cmov_interleaved_bad
; RV32IBT: successors: %bb.1, %bb.2
- ; RV32IBT: liveins: $x10, $x11, $x12, $x13
- ; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV32IBT: .1:
- ; RV32IBT: .2:
- ; RV32IBT: successors: %bb.3, %bb.4
- ; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
- ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.4
- ; RV32IBT: .3:
- ; RV32IBT: .4:
- ; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
- ; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV32IBT: $x10 = COPY [[ADD]]
- ; RV32IBT: PseudoRET implicit $x10
+ ; RV32IBT-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV32IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV32IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV32IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV32IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV32IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: .1:
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: .2:
+ ; RV32IBT-NEXT: successors: %bb.3, %bb.4
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
+ ; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: .3:
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: .4:
+ ; RV32IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
+ ; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV32IBT-NEXT: $x10 = COPY [[ADD]]
+ ; RV32IBT-NEXT: PseudoRET implicit $x10
; RV64I-LABEL: name: cmov_interleaved_bad
; RV64I: successors: %bb.1, %bb.2
- ; RV64I: liveins: $x10, $x11, $x12, $x13
- ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV64I: .1:
- ; RV64I: .2:
- ; RV64I: successors: %bb.3, %bb.4
- ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
- ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4
- ; RV64I: .3:
- ; RV64I: .4:
- ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
- ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV64I: $x10 = COPY [[ADD]]
- ; RV64I: PseudoRET implicit $x10
+ ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: .1:
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: .2:
+ ; RV64I-NEXT: successors: %bb.3, %bb.4
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
+ ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: .3:
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: .4:
+ ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
+ ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV64I-NEXT: $x10 = COPY [[ADD]]
+ ; RV64I-NEXT: PseudoRET implicit $x10
; RV64IBT-LABEL: name: cmov_interleaved_bad
; RV64IBT: successors: %bb.1, %bb.2
- ; RV64IBT: liveins: $x10, $x11, $x12, $x13
- ; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV64IBT: .1:
- ; RV64IBT: .2:
- ; RV64IBT: successors: %bb.3, %bb.4
- ; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
- ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.4
- ; RV64IBT: .3:
- ; RV64IBT: .4:
- ; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
- ; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV64IBT: $x10 = COPY [[ADD]]
- ; RV64IBT: PseudoRET implicit $x10
+ ; RV64IBT-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV64IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV64IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV64IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV64IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV64IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: .1:
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: .2:
+ ; RV64IBT-NEXT: successors: %bb.3, %bb.4
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
+ ; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: .3:
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: .4:
+ ; RV64IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
+ ; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV64IBT-NEXT: $x10 = COPY [[ADD]]
+ ; RV64IBT-NEXT: PseudoRET implicit $x10
%3:gpr = COPY $x13
%2:gpr = COPY $x12
%1:gpr = COPY $x11
@@ -178,88 +202,100 @@ body: |
; RV32I-LABEL: name: cmov_interleaved_debug_value
; RV32I: successors: %bb.1, %bb.2
- ; RV32I: liveins: $x10, $x11, $x12, $x13
- ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
- ; RV32I: DBG_VALUE [[ADDI]], $noreg
- ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV32I: .1:
- ; RV32I: .2:
- ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
- ; RV32I: DBG_VALUE [[PHI]], $noreg
- ; RV32I: DBG_VALUE [[PHI1]], $noreg
- ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV32I: $x10 = COPY [[ADD]]
- ; RV32I: PseudoRET implicit $x10
+ ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
+ ; RV32I-NEXT: DBG_VALUE [[ADDI]], $noreg
+ ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: .1:
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: .2:
+ ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+ ; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg
+ ; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg
+ ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV32I-NEXT: $x10 = COPY [[ADD]]
+ ; RV32I-NEXT: PseudoRET implicit $x10
; RV32IBT-LABEL: name: cmov_interleaved_debug_value
; RV32IBT: successors: %bb.1, %bb.2
- ; RV32IBT: liveins: $x10, $x11, $x12, $x13
- ; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
- ; RV32IBT: DBG_VALUE [[ADDI]], $noreg
- ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV32IBT: .1:
- ; RV32IBT: .2:
- ; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
- ; RV32IBT: DBG_VALUE [[PHI]], $noreg
- ; RV32IBT: DBG_VALUE [[PHI1]], $noreg
- ; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV32IBT: $x10 = COPY [[ADD]]
- ; RV32IBT: PseudoRET implicit $x10
+ ; RV32IBT-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV32IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV32IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV32IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV32IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV32IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
+ ; RV32IBT-NEXT: DBG_VALUE [[ADDI]], $noreg
+ ; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: .1:
+ ; RV32IBT-NEXT: {{ $}}
+ ; RV32IBT-NEXT: .2:
+ ; RV32IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV32IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+ ; RV32IBT-NEXT: DBG_VALUE [[PHI]], $noreg
+ ; RV32IBT-NEXT: DBG_VALUE [[PHI1]], $noreg
+ ; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV32IBT-NEXT: $x10 = COPY [[ADD]]
+ ; RV32IBT-NEXT: PseudoRET implicit $x10
; RV64I-LABEL: name: cmov_interleaved_debug_value
; RV64I: successors: %bb.1, %bb.2
- ; RV64I: liveins: $x10, $x11, $x12, $x13
- ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
- ; RV64I: DBG_VALUE [[ADDI]], $noreg
- ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV64I: .1:
- ; RV64I: .2:
- ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
- ; RV64I: DBG_VALUE [[PHI]], $noreg
- ; RV64I: DBG_VALUE [[PHI1]], $noreg
- ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV64I: $x10 = COPY [[ADD]]
- ; RV64I: PseudoRET implicit $x10
+ ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
+ ; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg
+ ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: .1:
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: .2:
+ ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+ ; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg
+ ; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg
+ ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV64I-NEXT: $x10 = COPY [[ADD]]
+ ; RV64I-NEXT: PseudoRET implicit $x10
; RV64IBT-LABEL: name: cmov_interleaved_debug_value
; RV64IBT: successors: %bb.1, %bb.2
- ; RV64IBT: liveins: $x10, $x11, $x12, $x13
- ; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
- ; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
- ; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
- ; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
- ; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
- ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
- ; RV64IBT: DBG_VALUE [[ADDI]], $noreg
- ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
- ; RV64IBT: .1:
- ; RV64IBT: .2:
- ; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
- ; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
- ; RV64IBT: DBG_VALUE [[PHI]], $noreg
- ; RV64IBT: DBG_VALUE [[PHI1]], $noreg
- ; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
- ; RV64IBT: $x10 = COPY [[ADD]]
- ; RV64IBT: PseudoRET implicit $x10
+ ; RV64IBT-NEXT: liveins: $x10, $x11, $x12, $x13
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
+ ; RV64IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
+ ; RV64IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
+ ; RV64IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
+ ; RV64IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
+ ; RV64IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
+ ; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
+ ; RV64IBT-NEXT: DBG_VALUE [[ADDI]], $noreg
+ ; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: .1:
+ ; RV64IBT-NEXT: {{ $}}
+ ; RV64IBT-NEXT: .2:
+ ; RV64IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
+ ; RV64IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+ ; RV64IBT-NEXT: DBG_VALUE [[PHI]], $noreg
+ ; RV64IBT-NEXT: DBG_VALUE [[PHI1]], $noreg
+ ; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
+ ; RV64IBT-NEXT: $x10 = COPY [[ADD]]
+ ; RV64IBT-NEXT: PseudoRET implicit $x10
%3:gpr = COPY $x13
%2:gpr = COPY $x12
%1:gpr = COPY $x11
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index dccdbdb844dbf..8bbe40ff27058 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -715,39 +715,39 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
; RV32MV-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32MV-NEXT: vmv.s.x v0, a0
; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV32MV-NEXT: vmv.v.i v26, 1
+; RV32MV-NEXT: vmv.v.i v8, 1
; RV32MV-NEXT: addi a0, sp, 32
-; RV32MV-NEXT: vle32.v v28, (a0)
+; RV32MV-NEXT: vle32.v v10, (a0)
; RV32MV-NEXT: lui a0, %hi(.LCPI3_0)
; RV32MV-NEXT: addi a0, a0, %lo(.LCPI3_0)
-; RV32MV-NEXT: vle32.v v30, (a0)
-; RV32MV-NEXT: vmerge.vim v26, v26, -1, v0
-; RV32MV-NEXT: vand.vv v26, v28, v26
+; RV32MV-NEXT: vle32.v v12, (a0)
+; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0
+; RV32MV-NEXT: vand.vv v8, v10, v8
; RV32MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32MV-NEXT: vmsne.vv v0, v26, v30
-; RV32MV-NEXT: vmv.v.i v26, 0
-; RV32MV-NEXT: vmerge.vim v26, v26, -1, v0
+; RV32MV-NEXT: vmsne.vv v0, v8, v12
+; RV32MV-NEXT: vmv.v.i v8, 0
+; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0
; RV32MV-NEXT: vsetivli zero, 1, e32, m2, ta, mu
-; RV32MV-NEXT: vse32.v v26, (s1)
-; RV32MV-NEXT: vslidedown.vi v28, v26, 1
-; RV32MV-NEXT: vmv.x.s a0, v28
-; RV32MV-NEXT: vslidedown.vi v28, v26, 2
-; RV32MV-NEXT: vmv.x.s a1, v28
+; RV32MV-NEXT: vse32.v v8, (s1)
+; RV32MV-NEXT: vslidedown.vi v10, v8, 1
+; RV32MV-NEXT: vmv.x.s a0, v10
+; RV32MV-NEXT: vslidedown.vi v10, v8, 2
+; RV32MV-NEXT: vmv.x.s a1, v10
; RV32MV-NEXT: slli a2, a1, 1
; RV32MV-NEXT: sub a0, a2, a0
; RV32MV-NEXT: sw a0, 4(s1)
-; RV32MV-NEXT: vslidedown.vi v28, v26, 4
-; RV32MV-NEXT: vmv.x.s a0, v28
+; RV32MV-NEXT: vslidedown.vi v10, v8, 4
+; RV32MV-NEXT: vmv.x.s a0, v10
; RV32MV-NEXT: srli a2, a0, 30
-; RV32MV-NEXT: vslidedown.vi v28, v26, 5
-; RV32MV-NEXT: vmv.x.s a3, v28
+; RV32MV-NEXT: vslidedown.vi v10, v8, 5
+; RV32MV-NEXT: vmv.x.s a3, v10
; RV32MV-NEXT: slli a3, a3, 2
; RV32MV-NEXT: or a2, a3, a2
; RV32MV-NEXT: andi a2, a2, 7
; RV32MV-NEXT: sb a2, 12(s1)
; RV32MV-NEXT: srli a1, a1, 31
-; RV32MV-NEXT: vslidedown.vi v26, v26, 3
-; RV32MV-NEXT: vmv.x.s a2, v26
+; RV32MV-NEXT: vslidedown.vi v8, v8, 3
+; RV32MV-NEXT: vmv.x.s a2, v8
; RV32MV-NEXT: andi a2, a2, 1
; RV32MV-NEXT: slli a2, a2, 1
; RV32MV-NEXT: or a1, a1, a2
@@ -838,29 +838,29 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
; RV64MV-NEXT: sd a1, 40(sp)
; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64MV-NEXT: addi a1, sp, 32
-; RV64MV-NEXT: vle64.v v26, (a1)
+; RV64MV-NEXT: vle64.v v8, (a1)
; RV64MV-NEXT: lui a1, %hi(.LCPI3_0)
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_0)
-; RV64MV-NEXT: vle64.v v28, (a1)
+; RV64MV-NEXT: vle64.v v10, (a1)
; RV64MV-NEXT: srli a1, a6, 31
-; RV64MV-NEXT: vand.vx v26, v26, a1
-; RV64MV-NEXT: vmsne.vv v0, v26, v28
-; RV64MV-NEXT: vmv.v.i v26, 0
-; RV64MV-NEXT: vmerge.vim v26, v26, -1, v0
+; RV64MV-NEXT: vand.vx v8, v8, a1
+; RV64MV-NEXT: vmsne.vv v0, v8, v10
+; RV64MV-NEXT: vmv.v.i v8, 0
+; RV64MV-NEXT: vmerge.vim v8, v8, -1, v0
; RV64MV-NEXT: vsetivli zero, 1, e64, m2, ta, mu
-; RV64MV-NEXT: vslidedown.vi v28, v26, 2
-; RV64MV-NEXT: vmv.x.s a2, v28
+; RV64MV-NEXT: vslidedown.vi v10, v8, 2
+; RV64MV-NEXT: vmv.x.s a2, v10
; RV64MV-NEXT: srli a3, a2, 30
; RV64MV-NEXT: andi a3, a3, 7
; RV64MV-NEXT: sb a3, 12(a0)
; RV64MV-NEXT: slli a2, a2, 2
-; RV64MV-NEXT: vslidedown.vi v28, v26, 1
-; RV64MV-NEXT: vmv.x.s a3, v28
+; RV64MV-NEXT: vslidedown.vi v10, v8, 1
+; RV64MV-NEXT: vmv.x.s a3, v10
; RV64MV-NEXT: and a3, a3, a1
; RV64MV-NEXT: srli a4, a3, 31
; RV64MV-NEXT: or a2, a4, a2
; RV64MV-NEXT: sw a2, 8(a0)
-; RV64MV-NEXT: vmv.x.s a2, v26
+; RV64MV-NEXT: vmv.x.s a2, v8
; RV64MV-NEXT: and a1, a2, a1
; RV64MV-NEXT: slli a2, a3, 33
; RV64MV-NEXT: or a1, a1, a2
diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
index b57f68a330c30..dbb8b31759d6a 100644
--- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
@@ -568,46 +568,46 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV32MV-NEXT: sh a1, 12(sp)
; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV32MV-NEXT: addi a1, sp, 8
-; RV32MV-NEXT: vle16.v v25, (a1)
+; RV32MV-NEXT: vle16.v v8, (a1)
; RV32MV-NEXT: lui a1, %hi(.LCPI4_0)
; RV32MV-NEXT: addi a1, a1, %lo(.LCPI4_0)
-; RV32MV-NEXT: vle16.v v26, (a1)
-; RV32MV-NEXT: vid.v v27
-; RV32MV-NEXT: vsub.vv v25, v25, v27
-; RV32MV-NEXT: vmul.vv v25, v25, v26
-; RV32MV-NEXT: vadd.vv v26, v25, v25
+; RV32MV-NEXT: vle16.v v9, (a1)
+; RV32MV-NEXT: vid.v v10
+; RV32MV-NEXT: vsub.vv v8, v8, v10
+; RV32MV-NEXT: vmul.vv v8, v8, v9
+; RV32MV-NEXT: vadd.vv v9, v8, v8
; RV32MV-NEXT: addi a1, zero, 9
-; RV32MV-NEXT: vmv.v.i v27, 10
+; RV32MV-NEXT: vmv.v.i v10, 10
; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
-; RV32MV-NEXT: vmv.s.x v27, a1
+; RV32MV-NEXT: vmv.s.x v10, a1
; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV32MV-NEXT: vsll.vv v26, v26, v27
+; RV32MV-NEXT: vsll.vv v9, v9, v10
; RV32MV-NEXT: addi a1, zero, 2047
-; RV32MV-NEXT: vand.vx v25, v25, a1
-; RV32MV-NEXT: vmv.v.i v27, 0
+; RV32MV-NEXT: vand.vx v8, v8, a1
+; RV32MV-NEXT: vmv.v.i v10, 0
; RV32MV-NEXT: addi a2, zero, 1
; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
-; RV32MV-NEXT: vmv1r.v v28, v27
-; RV32MV-NEXT: vmv.s.x v28, a2
+; RV32MV-NEXT: vmv1r.v v11, v10
+; RV32MV-NEXT: vmv.s.x v11, a2
; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32MV-NEXT: lui a2, %hi(.LCPI4_1)
; RV32MV-NEXT: addi a2, a2, %lo(.LCPI4_1)
-; RV32MV-NEXT: vle16.v v29, (a2)
-; RV32MV-NEXT: vsrl.vv v25, v25, v28
-; RV32MV-NEXT: vor.vv v25, v25, v26
-; RV32MV-NEXT: vand.vx v25, v25, a1
-; RV32MV-NEXT: vmsltu.vv v0, v29, v25
-; RV32MV-NEXT: vmerge.vim v25, v27, -1, v0
+; RV32MV-NEXT: vle16.v v12, (a2)
+; RV32MV-NEXT: vsrl.vv v8, v8, v11
+; RV32MV-NEXT: vor.vv v8, v8, v9
+; RV32MV-NEXT: vand.vx v8, v8, a1
+; RV32MV-NEXT: vmsltu.vv v0, v12, v8
+; RV32MV-NEXT: vmerge.vim v8, v10, -1, v0
; RV32MV-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV32MV-NEXT: vslidedown.vi v26, v25, 2
-; RV32MV-NEXT: vmv.x.s a1, v26
+; RV32MV-NEXT: vslidedown.vi v9, v8, 2
+; RV32MV-NEXT: vmv.x.s a1, v9
; RV32MV-NEXT: srli a2, a1, 10
; RV32MV-NEXT: andi a2, a2, 1
; RV32MV-NEXT: sb a2, 4(a0)
-; RV32MV-NEXT: vmv.x.s a2, v25
+; RV32MV-NEXT: vmv.x.s a2, v8
; RV32MV-NEXT: andi a2, a2, 2047
-; RV32MV-NEXT: vslidedown.vi v25, v25, 1
-; RV32MV-NEXT: vmv.x.s a3, v25
+; RV32MV-NEXT: vslidedown.vi v8, v8, 1
+; RV32MV-NEXT: vmv.x.s a3, v8
; RV32MV-NEXT: andi a3, a3, 2047
; RV32MV-NEXT: slli a3, a3, 11
; RV32MV-NEXT: or a2, a2, a3
@@ -633,46 +633,46 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64MV-NEXT: sh a1, 10(sp)
; RV64MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64MV-NEXT: addi a1, sp, 8
-; RV64MV-NEXT: vle16.v v25, (a1)
+; RV64MV-NEXT: vle16.v v8, (a1)
; RV64MV-NEXT: lui a1, %hi(.LCPI4_0)
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_0)
-; RV64MV-NEXT: vle16.v v26, (a1)
-; RV64MV-NEXT: vid.v v27
-; RV64MV-NEXT: vsub.vv v25, v25, v27
-; RV64MV-NEXT: vmul.vv v25, v25, v26
-; RV64MV-NEXT: vadd.vv v26, v25, v25
+; RV64MV-NEXT: vle16.v v9, (a1)
+; RV64MV-NEXT: vid.v v10
+; RV64MV-NEXT: vsub.vv v8, v8, v10
+; RV64MV-NEXT: vmul.vv v8, v8, v9
+; RV64MV-NEXT: vadd.vv v9, v8, v8
; RV64MV-NEXT: addi a1, zero, 9
-; RV64MV-NEXT: vmv.v.i v27, 10
+; RV64MV-NEXT: vmv.v.i v10, 10
; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
-; RV64MV-NEXT: vmv.s.x v27, a1
+; RV64MV-NEXT: vmv.s.x v10, a1
; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; RV64MV-NEXT: vsll.vv v26, v26, v27
+; RV64MV-NEXT: vsll.vv v9, v9, v10
; RV64MV-NEXT: addi a1, zero, 2047
-; RV64MV-NEXT: vand.vx v25, v25, a1
-; RV64MV-NEXT: vmv.v.i v27, 0
+; RV64MV-NEXT: vand.vx v8, v8, a1
+; RV64MV-NEXT: vmv.v.i v10, 0
; RV64MV-NEXT: addi a2, zero, 1
; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
-; RV64MV-NEXT: vmv1r.v v28, v27
-; RV64MV-NEXT: vmv.s.x v28, a2
+; RV64MV-NEXT: vmv1r.v v11, v10
+; RV64MV-NEXT: vmv.s.x v11, a2
; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64MV-NEXT: lui a2, %hi(.LCPI4_1)
; RV64MV-NEXT: addi a2, a2, %lo(.LCPI4_1)
-; RV64MV-NEXT: vle16.v v29, (a2)
-; RV64MV-NEXT: vsrl.vv v25, v25, v28
-; RV64MV-NEXT: vor.vv v25, v25, v26
-; RV64MV-NEXT: vand.vx v25, v25, a1
-; RV64MV-NEXT: vmsltu.vv v0, v29, v25
-; RV64MV-NEXT: vmerge.vim v25, v27, -1, v0
-; RV64MV-NEXT: vmv.x.s a1, v25
+; RV64MV-NEXT: vle16.v v12, (a2)
+; RV64MV-NEXT: vsrl.vv v8, v8, v11
+; RV64MV-NEXT: vor.vv v8, v8, v9
+; RV64MV-NEXT: vand.vx v8, v8, a1
+; RV64MV-NEXT: vmsltu.vv v0, v12, v8
+; RV64MV-NEXT: vmerge.vim v8, v10, -1, v0
+; RV64MV-NEXT: vmv.x.s a1, v8
; RV64MV-NEXT: andi a1, a1, 2047
; RV64MV-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
-; RV64MV-NEXT: vslidedown.vi v26, v25, 1
-; RV64MV-NEXT: vmv.x.s a2, v26
+; RV64MV-NEXT: vslidedown.vi v9, v8, 1
+; RV64MV-NEXT: vmv.x.s a2, v9
; RV64MV-NEXT: andi a2, a2, 2047
; RV64MV-NEXT: slli a2, a2, 11
; RV64MV-NEXT: or a1, a1, a2
-; RV64MV-NEXT: vslidedown.vi v25, v25, 2
-; RV64MV-NEXT: vmv.x.s a2, v25
+; RV64MV-NEXT: vslidedown.vi v8, v8, 2
+; RV64MV-NEXT: vmv.x.s a2, v8
; RV64MV-NEXT: slli a2, a2, 22
; RV64MV-NEXT: or a1, a1, a2
; RV64MV-NEXT: sw a1, 0(a0)
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