[PATCH] D107582: [CodeGen] Fix dependence breaking for tied operands

[Danila Malyutin via Phabricator via llvm-commits]

danilaml added a comment.

In D107582#3071113 <https://reviews.llvm.org/D107582#3071113>, @MatzeB wrote:

>> The overall issue here is that this pass doesn't seem to correctly handle instructions with implicit defs and tied reg operands. One case of it was fixed in https://reviews.llvm.org/D4351 , and this tries to fix similar issue (see the end of the summary and the test case)
>
> Correct me if I'm wrong, but my impression of D4351 <https://reviews.llvm.org/D4351> / line 225/226 is that the pass intends to simply not deal with tied-operands at all (regardless of implicit defs/uses being present or not); that seems reasonable enough for me. Though line 226 somehow stopped that logic from kicking in when there are undef operands involved right? So it seems to me the bug happens when you have a tied + undef operand at the same time? I don't see yet how (or if at all) implicit defs/uses play into the picture.

Well, the comment says that `If this reg is tied and live (Classes[Reg] is set to -1)`, but 1) Reg might still be live with `Classes[reg] != -1` (see my question on the D4351 <https://reviews.llvm.org/D4351> review) 2)  ...
This patch doesn't fix the underlying issue with implicit-def regs (as I'm uncertain on how to fix it besides bailing out as soo as an implicit reg is encountered), just prevents the code even reaching it for the test case, by moving the check after the implicit register is encountered and all its aliases are marked as -1 at the line 200.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107582/new/

https://reviews.llvm.org/D107582