[llvm] 84d9bc5 - [RISCV] Rewrite forwardCopyWillClobberTuple to not assume that there are exactly 32 registers. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-10-18T09:57:38-07:00
New Revision: 84d9bc51a33bc4dfaab32473fe301170a984ca93

URL: https://github.com/llvm/llvm-project/commit/84d9bc51a33bc4dfaab32473fe301170a984ca93
DIFF: https://github.com/llvm/llvm-project/commit/84d9bc51a33bc4dfaab32473fe301170a984ca93.diff

LOG: [RISCV] Rewrite forwardCopyWillClobberTuple to not assume that there are exactly 32 registers. NFC

This function was copied from ARM where register pairs/triples/quads can wrap around the 32 encoding space. So register 31 can pair with register 0. This is not true for RISCV vectors. The spec specifically mentions the possibility of a future encoding that has more than 32 registers.

This patch removes the modulo from the code and directly checks that destination register is in the source register range and not the beginning of the range. Though I don't expect an identity copy will occur.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D111467

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 882ad58fa3db2..efb9d7d623004 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -113,9 +113,7 @@ unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
 
 static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
                                         unsigned NumRegs) {
-  // We really want the positive remainder mod 32 here, that happens to be
-  // easily obtainable with a mask.
-  return ((DstReg - SrcReg) & 0x1f) < NumRegs;
+  return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs;
 }
 
 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,