[PATCH] D111885: [SelectionDAG] Fix illegal widening of scalable-vector loads
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 18 02:08:56 PDT 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3d850d03ae4d: [SelectionDAG] Fix illegal widening of scalable-vector loads (authored by frasercrmck).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D111885/new/
https://reviews.llvm.org/D111885
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
Index: llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+
+; Check that we are able to legalize scalable-vector stores that require widening.
+
+; FIXME: LLVM can't yet widen scalable-vector stores.
+
+define void @store_nxv3i8(<vscale x 3 x i8> %val, <vscale x 3 x i8>* %ptr) {
+ store <vscale x 3 x i8> %val, <vscale x 3 x i8>* %ptr
+ ret void
+}
+
+define void @store_nxv7f64(<vscale x 7 x double> %val, <vscale x 7 x double>* %ptr) {
+ store <vscale x 7 x double> %val, <vscale x 7 x double>* %ptr
+ ret void
+}
Index: llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
@@ -0,0 +1,16 @@
+; RUN: not --crash llc -mtriple=riscv32 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+m,+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs < %s
+
+; Check that we are able to legalize scalable-vector loads that require widening.
+
+; FIXME: LLVM can't yet widen scalable-vector loads.
+
+define <vscale x 3 x i8> @load_nxv3i8(<vscale x 3 x i8>* %ptr) {
+ %v = load <vscale x 3 x i8>, <vscale x 3 x i8>* %ptr
+ ret <vscale x 3 x i8> %v
+}
+
+define <vscale x 5 x half> @load_nxv5f16(<vscale x 5 x half>* %ptr) {
+ %v = load <vscale x 5 x half>, <vscale x 5 x half>* %ptr
+ ret <vscale x 5 x half> %v
+}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -5394,7 +5394,8 @@
TypeSize WidthDiff = WidenWidth - LdWidth;
// Allow wider loads if they are sufficiently aligned to avoid memory faults
// and if the original load is simple.
- unsigned LdAlign = (!LD->isSimple()) ? 0 : LD->getAlignment();
+ unsigned LdAlign =
+ (!LD->isSimple() || LdVT.isScalableVector()) ? 0 : LD->getAlignment();
// Find the vector type that can load from.
EVT NewVT = FindMemType(DAG, TLI, LdWidth.getKnownMinSize(), WidenVT, LdAlign,
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