[llvm] 3f0b178 - [AArch64] Fixed a bug on AArch64MIPeepholeOpt
Jingu Kang via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 18 00:56:15 PDT 2021
Author: Jingu Kang
Date: 2021-10-18T08:55:42+01:00
New Revision: 3f0b178de21ee82791a6ebe198314f14c0287a44
URL: https://github.com/llvm/llvm-project/commit/3f0b178de21ee82791a6ebe198314f14c0287a44
DIFF: https://github.com/llvm/llvm-project/commit/3f0b178de21ee82791a6ebe198314f14c0287a44.diff
LOG: [AArch64] Fixed a bug on AArch64MIPeepholeOpt
Create new virtual register for the definition of new AND instruction and
replace old register by the new one to keep SSA form.
Differential Revision: https://reviews.llvm.org/D109963
Added:
Modified:
llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index d091c8fd6a033..42f683613698a 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -127,11 +127,16 @@ bool AArch64MIPeepholeOpt::visitAND(
// Check whether AND's operand is MOV with immediate.
MachineInstr *MovMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg());
+ if (!MovMI)
+ return false;
+
MachineInstr *SubregToRegMI = nullptr;
// If it is SUBREG_TO_REG, check its operand.
if (MovMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) {
SubregToRegMI = MovMI;
MovMI = MRI->getUniqueVRegDef(MovMI->getOperand(2).getReg());
+ if (!MovMI)
+ return false;
}
if (MovMI->getOpcode() != AArch64::MOVi32imm &&
@@ -165,6 +170,7 @@ bool AArch64MIPeepholeOpt::visitAND(
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
Register NewTmpReg = MRI->createVirtualRegister(ANDImmRC);
+ Register NewDstReg = MRI->createVirtualRegister(ANDImmRC);
unsigned Opcode = (RegSize == 32) ? AArch64::ANDWri : AArch64::ANDXri;
MRI->constrainRegClass(NewTmpReg, MRI->getRegClass(SrcReg));
@@ -172,11 +178,16 @@ bool AArch64MIPeepholeOpt::visitAND(
.addReg(SrcReg)
.addImm(Imm1Enc);
- MRI->constrainRegClass(DstReg, ANDImmRC);
- BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
+ MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg));
+ BuildMI(*MBB, MI, DL, TII->get(Opcode), NewDstReg)
.addReg(NewTmpReg)
.addImm(Imm2Enc);
+ MRI->replaceRegWith(DstReg, NewDstReg);
+ // replaceRegWith changes MI's definition register. Keep it for SSA form until
+ // deleting MI.
+ MI.getOperand(0).setReg(DstReg);
+
ToBeRemoved.insert(&MI);
if (SubregToRegMI)
ToBeRemoved.insert(SubregToRegMI);
More information about the llvm-commits
mailing list