[PATCH] D111907: [AMDGPU] Divergence driven selection for fused bitlogic

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

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The change adds divergence predicates for fused logical operations.
The problem with selecting a scalar fused op such as S_NOR_B32 is
that it does not have a VALU counterpart and will be split in
moveToVALU. At the same time it prevents selection of a better
opcode on the VALU side (such as V_OR3_B32) which does not have a
counterpart on SALU side.

XNOR opcodes are left as is and selected as scalar to get advantage
of the SIInstrInfo::lowerScalarXnor() code which can commute
operations to keep one of two opcodes on SALU if possible. See
xnor.ll test for this.


https://reviews.llvm.org/D111907

Files:
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll

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