[PATCH] D111941: [X86][Costmodel] Add SSE2 sub-128bit vXi8/16/32 and 128/256-bit vXi32/64 stride 2 interleaved store costs

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

I suppose this is a better ballpark, but i'm not really sold on i64/i32-vf4 part.



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Comment at: llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll:13
 
 ; CHECK: LV: Checking a loop in "test"
 ;
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LG


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Comment at: llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll:13
 
 ; CHECK: LV: Checking a loop in "test"
 ;
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`@store_i32_stride2_vf4`'s codegen looks really different, i'm not sure this is right:
https://godbolt.org/z/dojn9enWK
https://godbolt.org/z/zfEPrYovd


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Comment at: llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll:13
 
 ; CHECK: LV: Checking a loop in "test"
 ;
----------------
All of `@store_i64_stride2_vf2`/`@store_i64_stride2_vf4`'s codegen looks really different.



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Comment at: llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll:13
 
 ; CHECK: LV: Checking a loop in "test"
 ;
----------------
LG


Repository:
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https://reviews.llvm.org/D111941