[PATCH] D111945: [X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs

Sat Oct 16 10:49:21 PDT 2021

lebedev.ri created this revision.
lebedev.ri added a reviewer: RKSimon.
lebedev.ri added a project: LLVM.
Herald added subscribers: pengfei, hiraditya.
lebedev.ri requested review of this revision.

A few more tuples are being queried after D111546 <https://reviews.llvm.org/D111546>. Might be good to model them,
They all require a lot of manual assembly surgery.

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/9bnKrefcG - for intels `Block RThroughput: =40.0`; for ryzens, `Block RThroughput: =16.0`
So could pick cost of `40`

For store we have:
https://godbolt.org/z/5s3s14dEY - for intels `Block RThroughput: =40.0`; for ryzens, `Block RThroughput: =16.0`
So we could pick cost of `40`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111945

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
===================================================================

--- llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   store i64 %v3, i64* %out3, align 8
 ; AVX2: LV: Found an estimated cost of 12 for VF 4 For instruction:   store i64 %v3, i64* %out3, align 8
 ; AVX2: LV: Found an estimated cost of 28 for VF 8 For instruction:   store i64 %v3, i64* %out3, align 8
-; AVX2: LV: Found an estimated cost of 208 for VF 16 For instruction:   store i64 %v3, i64* %out3, align 8
+; AVX2: LV: Found an estimated cost of 56 for VF 16 For instruction:   store i64 %v3, i64* %out3, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i64 %v3, i64* %out3, align 8
 ; AVX512: LV: Found an estimated cost of 5 for VF 2 For instruction:   store i64 %v3, i64* %out3, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   store double %v3, double* %out3, align 8
 ; AVX2: LV: Found an estimated cost of 12 for VF 4 For instruction:   store double %v3, double* %out3, align 8
 ; AVX2: LV: Found an estimated cost of 28 for VF 8 For instruction:   store double %v3, double* %out3, align 8
-; AVX2: LV: Found an estimated cost of 128 for VF 16 For instruction:   store double %v3, double* %out3, align 8
+; AVX2: LV: Found an estimated cost of 56 for VF 16 For instruction:   store double %v3, double* %out3, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store double %v3, double* %out3, align 8
 ; AVX512: LV: Found an estimated cost of 5 for VF 2 For instruction:   store double %v3, double* %out3, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 12 for VF 4 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 28 for VF 8 For instruction:   %v0 = load i64, i64* %in0, align 8
-; AVX2: LV: Found an estimated cost of 208 for VF 16 For instruction:   %v0 = load i64, i64* %in0, align 8
+; AVX2: LV: Found an estimated cost of 56 for VF 16 For instruction:   %v0 = load i64, i64* %in0, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX512: LV: Found an estimated cost of 5 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 12 for VF 4 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 28 for VF 8 For instruction:   %v0 = load double, double* %in0, align 8
-; AVX2: LV: Found an estimated cost of 128 for VF 16 For instruction:   %v0 = load double, double* %in0, align 8
+; AVX2: LV: Found an estimated cost of 56 for VF 16 For instruction:   %v0 = load double, double* %in0, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX512: LV: Found an estimated cost of 5 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5282,6 +5282,7 @@
       {4, MVT::v2i64, 6},  // (load 8i64 and) deinterleave into 4 x 2i64
       {4, MVT::v4i64, 8},  // (load 16i64 and) deinterleave into 4 x 4i64
       {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64
+      {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64
 
       {6, MVT::v2i8, 6},   // (load 12i8 and) deinterleave into 6 x 2i8
       {6, MVT::v4i8, 14},  // (load 24i8 and) deinterleave into 6 x 4i8
@@ -5376,6 +5377,7 @@
       {4, MVT::v2i64, 6},  // interleave 4 x 2i64 into 8i64 (and store)
       {4, MVT::v4i64, 8},  // interleave 4 x 4i64 into 16i64 (and store)
       {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store)
+      {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store)
 
       {6, MVT::v2i8, 7},   // interleave 6 x 2i8 into 12i8 (and store)
       {6, MVT::v4i8, 9},   // interleave 6 x 4i8 into 24i8 (and store)


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