[llvm] 8cd9c35 - [VectorCombine] add tests for shuffle of binops; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 15 08:22:11 PDT 2021
Author: Sanjay Patel
Date: 2021-10-15T11:22:06-04:00
New Revision: 8cd9c351a1af93ba37e9da1ca2f5896ca2878a7a
URL: https://github.com/llvm/llvm-project/commit/8cd9c351a1af93ba37e9da1ca2f5896ca2878a7a
DIFF: https://github.com/llvm/llvm-project/commit/8cd9c351a1af93ba37e9da1ca2f5896ca2878a7a.diff
LOG: [VectorCombine] add tests for shuffle of binops; NFC
Added:
Modified:
llvm/test/Transforms/VectorCombine/X86/shuffle.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll
index c779e72984bf5..a49d874e32009 100644
--- a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll
@@ -150,3 +150,163 @@ define <2 x i64> @PR35454_2(<2 x i64> %v) {
%bc3 = bitcast <4 x i32> %permil1 to <2 x i64>
ret <2 x i64> %bc3
}
+
+define <4 x float> @shuf_fdiv_v4f32_yy(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; CHECK-LABEL: @shuf_fdiv_v4f32_yy(
+; CHECK-NEXT: [[B0:%.*]] = fdiv fast <4 x float> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = fdiv arcp <4 x float> [[Z:%.*]], [[Y]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT: ret <4 x float> [[R]]
+;
+ %b0 = fdiv fast <4 x float> %x, %y
+ %b1 = fdiv arcp <4 x float> %z, %y
+ %r = shufflevector <4 x float> %b0, <4 x float> %b1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ ret <4 x float> %r
+}
+
+define <4 x i32> @shuf_add_v4i32_xx(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: @shuf_add_v4i32_xx(
+; CHECK-NEXT: [[B0:%.*]] = add <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = add <4 x i32> [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 undef, i32 undef, i32 6, i32 0>
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %b0 = add <4 x i32> %x, %y
+ %b1 = add <4 x i32> %x, %z
+ %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 poison, i32 poison, i32 6, i32 0>
+ ret <4 x i32> %r
+}
+
+define <4 x float> @shuf_fmul_v4f32_xx_swap(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; CHECK-LABEL: @shuf_fmul_v4f32_xx_swap(
+; CHECK-NEXT: [[B0:%.*]] = fmul <4 x float> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = fmul <4 x float> [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <4 x i32> <i32 0, i32 3, i32 4, i32 7>
+; CHECK-NEXT: ret <4 x float> [[R]]
+;
+ %b0 = fmul <4 x float> %x, %y
+ %b1 = fmul <4 x float> %z, %x
+ %r = shufflevector <4 x float> %b0, <4 x float> %b1, <4 x i32> <i32 0, i32 3, i32 4, i32 7>
+ ret <4 x float> %r
+}
+
+define <2 x i64> @shuf_and_v2i64_yy_swap(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
+; CHECK-LABEL: @shuf_and_v2i64_yy_swap(
+; CHECK-NEXT: [[B0:%.*]] = and <2 x i64> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = and <2 x i64> [[Y]], [[Z:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i64> [[B0]], <2 x i64> [[B1]], <2 x i32> <i32 3, i32 0>
+; CHECK-NEXT: ret <2 x i64> [[R]]
+;
+ %b0 = and <2 x i64> %x, %y
+ %b1 = and <2 x i64> %y, %z
+ %r = shufflevector <2 x i64> %b0, <2 x i64> %b1, <2 x i32> <i32 3, i32 0>
+ ret <2 x i64> %r
+}
+
+define <4 x i32> @shuf_shl_v4i32_xx(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: @shuf_shl_v4i32_xx(
+; CHECK-NEXT: [[B0:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = shl <4 x i32> [[X]], [[Z:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 3, i32 1, i32 1, i32 6>
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %b0 = shl <4 x i32> %x, %y
+ %b1 = shl <4 x i32> %x, %z
+ %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 3, i32 1, i32 1, i32 6>
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @shuf_shl_v4i32_xx_swap(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: @shuf_shl_v4i32_xx_swap(
+; CHECK-NEXT: [[B0:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = shl <4 x i32> [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 3, i32 2, i32 2, i32 5>
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %b0 = shl <4 x i32> %x, %y
+ %b1 = shl <4 x i32> %z, %x
+ %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 3, i32 2, i32 2, i32 5>
+ ret <4 x i32> %r
+}
+
+define <2 x i64> @shuf_sub_add_v2i64_yy(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
+; CHECK-LABEL: @shuf_sub_add_v2i64_yy(
+; CHECK-NEXT: [[B0:%.*]] = sub <2 x i64> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = add <2 x i64> [[Z:%.*]], [[Y]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i64> [[B0]], <2 x i64> [[B1]], <2 x i32> <i32 3, i32 0>
+; CHECK-NEXT: ret <2 x i64> [[R]]
+;
+ %b0 = sub <2 x i64> %x, %y
+ %b1 = add <2 x i64> %z, %y
+ %r = shufflevector <2 x i64> %b0, <2 x i64> %b1, <2 x i32> <i32 3, i32 0>
+ ret <2 x i64> %r
+}
+
+define <8 x float> @shuf_fmul_v4f32_xx_type(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; CHECK-LABEL: @shuf_fmul_v4f32_xx_type(
+; CHECK-NEXT: [[B0:%.*]] = fmul <4 x float> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = fmul <4 x float> [[Z:%.*]], [[X]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <8 x i32> <i32 0, i32 3, i32 4, i32 7, i32 0, i32 1, i32 1, i32 6>
+; CHECK-NEXT: ret <8 x float> [[R]]
+;
+ %b0 = fmul <4 x float> %x, %y
+ %b1 = fmul <4 x float> %z, %x
+ %r = shufflevector <4 x float> %b0, <4 x float> %b1, <8 x i32> <i32 0, i32 3, i32 4, i32 7, i32 0, i32 1, i32 1, i32 6>
+ ret <8 x float> %r
+}
+
+define <4 x i32> @shuf_lshr_v4i32_yy_use1(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: @shuf_lshr_v4i32_yy_use1(
+; CHECK-NEXT: [[B0:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: call void @use(<4 x i32> [[B0]])
+; CHECK-NEXT: [[B1:%.*]] = lshr <4 x i32> [[Z:%.*]], [[Y]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %b0 = lshr <4 x i32> %x, %y
+ call void @use(<4 x i32> %b0)
+ %b1 = lshr <4 x i32> %z, %y
+ %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @shuf_mul_v4i32_yy_use2(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: @shuf_mul_v4i32_yy_use2(
+; CHECK-NEXT: [[B0:%.*]] = mul <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = mul <4 x i32> [[Z:%.*]], [[Y]]
+; CHECK-NEXT: call void @use(<4 x i32> [[B1]])
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[R]]
+;
+ %b0 = mul <4 x i32> %x, %y
+ %b1 = mul <4 x i32> %z, %y
+ call void @use(<4 x i32> %b1)
+ %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ ret <4 x i32> %r
+}
+
+define <4 x float> @shuf_fadd_v4f32_no_common_op(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
+; CHECK-LABEL: @shuf_fadd_v4f32_no_common_op(
+; CHECK-NEXT: [[B0:%.*]] = fadd <4 x float> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = fadd <4 x float> [[Z:%.*]], [[W:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT: ret <4 x float> [[R]]
+;
+ %b0 = fadd <4 x float> %x, %y
+ %b1 = fadd <4 x float> %z, %w
+ %r = shufflevector <4 x float> %b0, <4 x float> %b1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ ret <4 x float> %r
+}
+
+define <16 x i16> @shuf_and_v16i16_yy_expensive_shuf(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) {
+; CHECK-LABEL: @shuf_and_v16i16_yy_expensive_shuf(
+; CHECK-NEXT: [[B0:%.*]] = and <16 x i16> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[B1:%.*]] = and <16 x i16> [[Y]], [[Z:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shufflevector <16 x i16> [[B0]], <16 x i16> [[B1]], <16 x i32> <i32 15, i32 22, i32 25, i32 13, i32 28, i32 0, i32 undef, i32 3, i32 0, i32 30, i32 3, i32 7, i32 9, i32 19, i32 2, i32 22>
+; CHECK-NEXT: ret <16 x i16> [[R]]
+;
+ %b0 = and <16 x i16> %x, %y
+ %b1 = and <16 x i16> %y, %z
+ %r = shufflevector <16 x i16> %b0, <16 x i16> %b1, <16 x i32> <i32 15, i32 22, i32 25, i32 13, i32 28, i32 0, i32 poison, i32 3, i32 0, i32 30, i32 3, i32 7, i32 9, i32 19, i32 2, i32 22>
+ ret <16 x i16> %r
+}
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