[llvm] e23351c - [Test][InstCombine] Precommit tests for PR52078

[Anton Afanasyev via llvm-commits]

Author: Anton Afanasyev
Date: 2021-10-15T13:38:40+03:00
New Revision: e23351cdc9bc78d06c239dc0de8a4ca70acdef65

URL: https://github.com/llvm/llvm-project/commit/e23351cdc9bc78d06c239dc0de8a4ca70acdef65
DIFF: https://github.com/llvm/llvm-project/commit/e23351cdc9bc78d06c239dc0de8a4ca70acdef65.diff

LOG: [Test][InstCombine] Precommit tests for PR52078

Added: 
    llvm/test/Transforms/PhaseOrdering/X86/pr52078.ll

Modified: 
    llvm/test/Transforms/InstCombine/lshr.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 571d86d059ae0..89f36e5409260 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -617,3 +617,51 @@ define i12 @trunc_sandwich_big_sum_shift2_use1(i32 %x) {
   %r = lshr i12 %tr, 1
   ret i12 %r
 }
+
+define i16 @lshr_sext_i1_to_i16(i1 %a) {
+; CHECK-LABEL: @lshr_sext_i1_to_i16(
+; CHECK-NEXT:    [[SEXT:%.*]] = sext i1 [[A:%.*]] to i16
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i16 [[SEXT]], 4
+; CHECK-NEXT:    ret i16 [[LSHR]]
+;
+  %sext = sext i1 %a to i16
+  %lshr = lshr i16 %sext, 4
+  ret i16 %lshr
+}
+
+define i128 @lshr_sext_i1_to_i128(i1 %a) {
+; CHECK-LABEL: @lshr_sext_i1_to_i128(
+; CHECK-NEXT:    [[SEXT:%.*]] = sext i1 [[A:%.*]] to i128
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i128 [[SEXT]], 42
+; CHECK-NEXT:    ret i128 [[LSHR]]
+;
+  %sext = sext i1 %a to i128
+  %lshr = lshr i128 %sext, 42
+  ret i128 %lshr
+}
+
+define i32 @lshr_sext_i1_to_i32_use(i1 %a) {
+; CHECK-LABEL: @lshr_sext_i1_to_i32_use(
+; CHECK-NEXT:    [[SEXT:%.*]] = sext i1 [[A:%.*]] to i32
+; CHECK-NEXT:    call void @use(i32 [[SEXT]])
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i32 [[SEXT]], 14
+; CHECK-NEXT:    ret i32 [[LSHR]]
+;
+  %sext = sext i1 %a to i32
+  call void @use(i32 %sext)
+  %lshr = lshr i32 %sext, 14
+  ret i32 %lshr
+}
+
+define <3 x i14> @lshr_sext_i1_to_i14_splat_vec_use1(<3 x i1> %a) {
+; CHECK-LABEL: @lshr_sext_i1_to_i14_splat_vec_use1(
+; CHECK-NEXT:    [[SEXT:%.*]] = sext <3 x i1> [[A:%.*]] to <3 x i14>
+; CHECK-NEXT:    call void @usevec(<3 x i14> [[SEXT]])
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <3 x i14> [[SEXT]], <i14 4, i14 4, i14 4>
+; CHECK-NEXT:    ret <3 x i14> [[LSHR]]
+;
+  %sext = sext <3 x i1> %a to <3 x i14>
+  call void @usevec(<3 x i14> %sext)
+  %lshr = lshr <3 x i14> %sext, <i14 4, i14 4, i14 4>
+  ret <3 x i14> %lshr
+}

diff  --git a/llvm/test/Transforms/PhaseOrdering/X86/pr52078.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr52078.ll
new file mode 100644
index 0000000000000..2fbfbca7ebe39
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/pr52078.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O2 -S < %s | FileCheck %s
+; RUN: opt -instcombine -S < %s | FileCheck %s --check-prefix=IC
+; RUN: opt -aggressive-instcombine -instcombine -S < %s | FileCheck %s --check-prefix=AIC_AND_IC
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i16 @foo(i1 %a) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:    [[TRUNC:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
+; CHECK-NEXT:    ret i16 [[TRUNC]]
+;
+; IC-LABEL: @foo(
+; IC-NEXT:    [[TRUNC:%.*]] = select i1 [[A:%.*]], i16 32767, i16 0
+; IC-NEXT:    ret i16 [[TRUNC]]
+;
+; AIC_AND_IC-LABEL: @foo(
+; AIC_AND_IC-NEXT:    [[SEXT:%.*]] = sext i1 [[A:%.*]] to i16
+; AIC_AND_IC-NEXT:    [[LSHR:%.*]] = lshr i16 [[SEXT]], 1
+; AIC_AND_IC-NEXT:    ret i16 [[LSHR]]
+;
+  %sext = sext i1 %a to i16
+  %zext = zext i16 %sext to i32
+  %lshr = lshr i32 %zext, 1
+  %trunc = trunc i32 %lshr to i16
+  ret i16 %trunc
+}
+
+define i16 @foo2(i1 %a) {
+; CHECK-LABEL: @foo2(
+; CHECK-NEXT:    [[S:%.*]] = sext i1 [[A:%.*]] to i16
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i16 [[S]], 1
+; CHECK-NEXT:    ret i16 [[LSHR]]
+;
+; IC-LABEL: @foo2(
+; IC-NEXT:    [[S:%.*]] = sext i1 [[A:%.*]] to i16
+; IC-NEXT:    [[LSHR:%.*]] = lshr i16 [[S]], 1
+; IC-NEXT:    ret i16 [[LSHR]]
+;
+; AIC_AND_IC-LABEL: @foo2(
+; AIC_AND_IC-NEXT:    [[S:%.*]] = sext i1 [[A:%.*]] to i16
+; AIC_AND_IC-NEXT:    [[LSHR:%.*]] = lshr i16 [[S]], 1
+; AIC_AND_IC-NEXT:    ret i16 [[LSHR]]
+;
+  %s = sext i1 %a to i16
+  %lshr = lshr i16 %s, 1
+  ret i16 %lshr
+}