[PATCH] D111846: [LV] Drop NUW/NSW flags from scalarized instructions that need predication

Diego Caballero via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 14 15:12:35 PDT 2021


dcaballe created this revision.
dcaballe added reviewers: fhahn, Ayal, gilr, dmgreen, spatel.
Herald added a subscriber: hiraditya.
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Herald added a subscriber: llvm-commits.

This patch fixes PR52111. The problem is that LV propagates NUW/NSW flags in instructions
that are originally guarded by a condition and its respective control flow. It may happen that
the NUW/NSW flag is only valid when the condition and control flow is in place. When the code
is vectorized and the control flow within the loop is linearized, the NUW/NSW flags may no
longer hold and lead to a poison value if they are propagated. For example, in the following
loop:

  loop2.header:
    %iv2 = phi i64 [ 0, %loop1.header ], [ %iv2.inc, %if.end ]
    %i23 = icmp eq i64 %iv2, 0
    br i1 %i23, label %if.end, label %if.then
  
  if.then:
    %i27 = sub nuw nsw i64 %iv2, 1
    %i29 = getelementptr inbounds [1 x [33 x float]], [1 x [33 x float]]* %input, i64 0, i64 %iv1, i64 %i27
  ...

'%i27' is a uniform operation related to address computation and it's guarded by condition
'%i23' (iv2 > 0). Its NUW flag is only valid due to this condition since the condition ensures
that the value of '%iv2' reaching '%i27' will always be greter than zero and, consequently,
the result of '%iv27' will always be positive. However, after vectorizing and linearizing
control flow, '%i27' (uniform, address computation) will also be executed for '%iv2 = 0' and
the NUW flag becomes invalid.

The fix drops NUW/NSW from instructions that were originally in a basic block that needed predication
and are scalarized and non-predicated after vectorization. NUW/NSW flags still make sense for
instructions that are widened since the flags will still hold for those lanes doing valid work.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111846

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
  llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
  llvm/test/Transforms/LoopVectorize/pr52111.ll

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