[PATCH] D111800: [VectorCombine] Add option to only run scalarization transforms.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

In D111800#3064573 <https://reviews.llvm.org/D111800#3064573>, @spatel wrote:

> What if we just did better in VectorCombine?
>
> We'd need to chain a bunch of combines together on paper or just implement this:
> https://llvm.org/PR52178
> ...to know if it gets us to the minimal set of shuffles in IR and/or codegen for the 'hadd' example, but it might be enough?

Yes, I think that would get us a bit further, especially on the ARM64 test case. For X86 the shuffles/add chains are a bit more difficult to tackle: it converts the 4 scalar adds to 4 vector adds which each process a single lane. I'm not sure if we will be able to cover this in VectorCombine.


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https://reviews.llvm.org/D111800