[llvm] c1d6ba5 - [RISCV][test] Add more tests of immediate materialisation

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2021-10-14T02:24:14Z
New Revision: c1d6ba54d360c953f926ea6df547b1ba0dbcdc44

URL: https://github.com/llvm/llvm-project/commit/c1d6ba54d360c953f926ea6df547b1ba0dbcdc44
DIFF: https://github.com/llvm/llvm-project/commit/c1d6ba54d360c953f926ea6df547b1ba0dbcdc44.diff

LOG: [RISCV][test] Add more tests of immediate materialisation

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D111704

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/imm.ll
    llvm/test/MC/RISCV/rv64zba-aliases-valid.s

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index d5bdeb3d61e86..cf8e81c2505af 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -1543,3 +1543,68 @@ define i64 @imm_neg_2147485013() {
 ; RV64IZBS-NEXT:    ret
   ret i64 -2147485013
 }
+
+define i64 @imm_12900924131259() {
+; RV32I-LABEL: imm_12900924131259:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 765952
+; RV32I-NEXT:    addi a0, a0, 1979
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, -1093
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: imm_12900924131259:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a0, 188
+; RV64I-NEXT:    addiw a0, a0, -1093
+; RV64I-NEXT:    slli a0, a0, 24
+; RV64I-NEXT:    addi a0, a0, 1979
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: imm_12900924131259:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    lui a0, 188
+; RV64IZBA-NEXT:    addiw a0, a0, -1093
+; RV64IZBA-NEXT:    slli a0, a0, 24
+; RV64IZBA-NEXT:    addi a0, a0, 1979
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBS-LABEL: imm_12900924131259:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    lui a0, 188
+; RV64IZBS-NEXT:    addiw a0, a0, -1093
+; RV64IZBS-NEXT:    slli a0, a0, 24
+; RV64IZBS-NEXT:    addi a0, a0, 1979
+; RV64IZBS-NEXT:    ret
+  ret i64 12900924131259
+}
+
+define i64 @imm_50394234880() {
+; RV32I-LABEL: imm_50394234880:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 768944
+; RV32I-NEXT:    addi a1, zero, 11
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: imm_50394234880:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a0, 188
+; RV64I-NEXT:    addiw a0, a0, -1093
+; RV64I-NEXT:    slli a0, a0, 16
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: imm_50394234880:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    lui a0, 188
+; RV64IZBA-NEXT:    addiw a0, a0, -1093
+; RV64IZBA-NEXT:    slli a0, a0, 16
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBS-LABEL: imm_50394234880:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    lui a0, 188
+; RV64IZBS-NEXT:    addiw a0, a0, -1093
+; RV64IZBS-NEXT:    slli a0, a0, 16
+; RV64IZBS-NEXT:    ret
+  ret i64 50394234880
+}

diff  --git a/llvm/test/MC/RISCV/rv64zba-aliases-valid.s b/llvm/test/MC/RISCV/rv64zba-aliases-valid.s
index b19109f471ed7..520b5bd706927 100644
--- a/llvm/test/MC/RISCV/rv64zba-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64zba-aliases-valid.s
@@ -32,3 +32,21 @@ li x6, 0xfffffffe
 # CHECK-S-OBJ-NEXT: addiw t2, t2, -1366
 # CHECK-S-OBJ-NEXT: zext.w t2, t2
 li x7, 0xaaaaaaaa
+
+# CHECK-S-OBJ-NOALIAS: lui t0, 188
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t0, t0, -1093
+# CHECK-S-OBJ-NOALIAS-NEXT: slli t0, t0, 24
+# CHECK-S-OBJ-NOALIAS-NEXT: addi t0, t0, 1979
+# CHECK-S-OBJ: lui t0, 188
+# CHECK-S-OBJ-NEXT: addiw t0, t0, -1093
+# CHECK-S-OBJ-NEXT: slli t0, t0, 24
+# CHECK-S-OBJ-NEXT: addi t0, t0, 1979
+li x5, 0xbbbbb0007bb
+
+# CHECK-S-OBJ-NOALIAS: lui t0, 188
+# CHECK-S-OBJ-NOALIAS-NEXT: addiw t0, t0, -1093
+# CHECK-S-OBJ-NOALIAS-NEXT: slli t0, t0, 16
+# CHECK-S-OBJ: lui t0, 188
+# CHECK-S-OBJ-NEXT: addiw t0, t0, -1093
+# CHECK-S-OBJ-NEXT: slli t0, t0, 16
+li x5, 0xbbbbb0000