[PATCH] D111538: [X86] Prefer VEX encoding in X86 assembler.

[Kan Shengchen via Phabricator via llvm-commits]

skan added a comment.

In D111538#3061307 <https://reviews.llvm.org/D111538#3061307>, @lebedev.ri wrote:

> In D111538#3061306 <https://reviews.llvm.org/D111538#3061306>, @LuoYuanke wrote:
>
>> In D111538#3061274 <https://reviews.llvm.org/D111538#3061274>, @lebedev.ri wrote:
>>
>>> In D111538#3061264 <https://reviews.llvm.org/D111538#3061264>, @LuoYuanke wrote:
>>>
>>>> In D111538#3061027 <https://reviews.llvm.org/D111538#3061027>, @lebedev.ri wrote:
>>>>
>>>>> Having something specific to some specific target in a generic code
>>>>> (esp. if there is no precedent for it) seems conceptually wrong.
>>>>
>>>> We can see in line 636, it also do some specific things for ARM. We can also see ReportMultipleNearMisses is added for ARM.
>>>
>>> I think you understand that i'm not talking about doing specific for target X - adding new hooks is fine,
>>> but specifically about checking for the subclass name and doing different stuff based on that.
>>
>> Do you have any suggestions? I don't know if there is any mechanism that can invoke target specific function in generic code in tablegen.
>
> I guess i would suggest dealing with that in the backend itself.

@lebedev.ri How about adding a hook such as hasPositionOrder, which means the order in which the instructions appear in TD file affects the order of assembler matching ?


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