[llvm] d67022f - [InstCombine] add vector splat tests for foldLogOpOfMaskedICmps(); NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 13 07:07:59 PDT 2021
Author: Sanjay Patel
Date: 2021-10-13T09:53:59-04:00
New Revision: d67022fba91b3ea3af5bcccea930cd96a430ffb2
URL: https://github.com/llvm/llvm-project/commit/d67022fba91b3ea3af5bcccea930cd96a430ffb2
DIFF: https://github.com/llvm/llvm-project/commit/d67022fba91b3ea3af5bcccea930cd96a430ffb2.diff
LOG: [InstCombine] add vector splat tests for foldLogOpOfMaskedICmps(); NFC
There's a substantial pile of scalar tests for transforms that
depend on this code, but zero vector coverage. This patch adds
a vector test next to the first scalar test in each file that
is affected by foldLogOpOfMaskedICmps.
The code that handles these transforms is artificially limited
from working with vector splat constants.
Added:
Modified:
llvm/test/Transforms/InstCombine/bit-checks.ll
llvm/test/Transforms/InstCombine/icmp-logical.ll
llvm/test/Transforms/InstCombine/onehot_merge.ll
llvm/test/Transforms/InstCombine/or.ll
llvm/test/Transforms/InstCombine/sign-test-and-or.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/bit-checks.ll b/llvm/test/Transforms/InstCombine/bit-checks.ll
index e755e50833f4c..9937a71747f79 100644
--- a/llvm/test/Transforms/InstCombine/bit-checks.ll
+++ b/llvm/test/Transforms/InstCombine/bit-checks.ll
@@ -288,6 +288,25 @@ define i32 @main4(i32 %argc) {
ret i32 %storemerge
}
+define <2 x i32> @main4_splat(<2 x i32> %argc) {
+; CHECK-LABEL: @main4_splat(
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[ARGC:%.*]], <i32 7, i32 7>
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <2 x i32> [[AND]], <i32 7, i32 7>
+; CHECK-NEXT: [[AND2:%.*]] = and <2 x i32> [[ARGC]], <i32 48, i32 48>
+; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne <2 x i32> [[AND2]], <i32 48, i32 48>
+; CHECK-NEXT: [[NOT_AND_COND:%.*]] = or <2 x i1> [[TOBOOL]], [[TOBOOL3]]
+; CHECK-NEXT: [[STOREMERGE:%.*]] = zext <2 x i1> [[NOT_AND_COND]] to <2 x i32>
+; CHECK-NEXT: ret <2 x i32> [[STOREMERGE]]
+;
+ %and = and <2 x i32> %argc, <i32 7, i32 7>
+ %tobool = icmp eq <2 x i32> %and, <i32 7, i32 7>
+ %and2 = and <2 x i32> %argc, <i32 48, i32 48>
+ %tobool3 = icmp eq <2 x i32> %and2, <i32 48, i32 48>
+ %and.cond = and <2 x i1> %tobool, %tobool3
+ %storemerge = select <2 x i1> %and.cond, <2 x i32> <i32 0, i32 0>, <2 x i32> <i32 1, i32 1>
+ ret <2 x i32> %storemerge
+}
+
define i32 @main4_logical(i32 %argc) {
; CHECK-LABEL: @main4_logical(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARGC:%.*]], 55
diff --git a/llvm/test/Transforms/InstCombine/icmp-logical.ll b/llvm/test/Transforms/InstCombine/icmp-logical.ll
index cc23b114bd01b..a9edfeb47a024 100644
--- a/llvm/test/Transforms/InstCombine/icmp-logical.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-logical.ll
@@ -15,6 +15,23 @@ define i1 @masked_and_notallzeroes(i32 %A) {
ret i1 %res
}
+define <2 x i1> @masked_and_notallzeroes_splat(<2 x i32> %A) {
+; CHECK-LABEL: @masked_and_notallzeroes_splat(
+; CHECK-NEXT: [[MASK1:%.*]] = and <2 x i32> [[A:%.*]], <i32 7, i32 7>
+; CHECK-NEXT: [[TST1:%.*]] = icmp ne <2 x i32> [[MASK1]], zeroinitializer
+; CHECK-NEXT: [[MASK2:%.*]] = and <2 x i32> [[A]], <i32 39, i32 39>
+; CHECK-NEXT: [[TST2:%.*]] = icmp ne <2 x i32> [[MASK2]], zeroinitializer
+; CHECK-NEXT: [[RES:%.*]] = and <2 x i1> [[TST1]], [[TST2]]
+; CHECK-NEXT: ret <2 x i1> [[RES]]
+;
+ %mask1 = and <2 x i32> %A, <i32 7, i32 7>
+ %tst1 = icmp ne <2 x i32> %mask1, <i32 0, i32 0>
+ %mask2 = and <2 x i32> %A, <i32 39, i32 39>
+ %tst2 = icmp ne <2 x i32> %mask2, <i32 0, i32 0>
+ %res = and <2 x i1> %tst1, %tst2
+ ret <2 x i1> %res
+}
+
define i1 @masked_and_notallzeroes_logical(i32 %A) {
; CHECK-LABEL: @masked_and_notallzeroes_logical(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
diff --git a/llvm/test/Transforms/InstCombine/onehot_merge.ll b/llvm/test/Transforms/InstCombine/onehot_merge.ll
index 8cde517dec67b..31183fe8a74a2 100644
--- a/llvm/test/Transforms/InstCombine/onehot_merge.ll
+++ b/llvm/test/Transforms/InstCombine/onehot_merge.ll
@@ -575,6 +575,23 @@ define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32
ret i1 %or
}
+define <2 x i1> @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_splat(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {
+; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_splat(
+; CHECK-NEXT: [[T0:%.*]] = shl <2 x i32> [[K:%.*]], [[C1:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = icmp slt <2 x i32> [[T0]], zeroinitializer
+; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[K]], [[C2:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = icmp slt <2 x i32> [[T2]], zeroinitializer
+; CHECK-NEXT: [[OR:%.*]] = and <2 x i1> [[T1]], [[T3]]
+; CHECK-NEXT: ret <2 x i1> [[OR]]
+;
+ %t0 = shl <2 x i32> %k, %c1
+ %t1 = icmp slt <2 x i32> %t0, zeroinitializer
+ %t2 = shl <2 x i32> %k, %c2
+ %t3 = icmp slt <2 x i32> %t2, zeroinitializer
+ %or = and <2 x i1> %t1, %t3
+ ret <2 x i1> %or
+}
+
; %t2 can be poison where as %t0 isn't; merging these two is unsafe.
define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_logical(i32 %k, i32 %c1, i32 %c2) {
; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_logical(
diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll
index c50f226438eca..00af70be740a6 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -1456,3 +1456,18 @@ define i1 @cmp_overlap(i32 %x) {
%r = or i1 %isneg, %isnotneg
ret i1 %r
}
+
+define <2 x i1> @cmp_overlap_splat(<2 x i5> %x) {
+; CHECK-LABEL: @cmp_overlap_splat(
+; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt <2 x i5> [[X:%.*]], zeroinitializer
+; CHECK-NEXT: [[NOTSUB:%.*]] = add <2 x i5> [[X]], <i5 -1, i5 -1>
+; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp slt <2 x i5> [[NOTSUB]], zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[ISNEG]], [[ISNOTNEG]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %isneg = icmp slt <2 x i5> %x, zeroinitializer
+ %negx = sub <2 x i5> zeroinitializer, %x
+ %isnotneg = icmp sgt <2 x i5> %negx, <i5 -1, i5 -1>
+ %r = or <2 x i1> %isneg, %isnotneg
+ ret <2 x i1> %r
+}
diff --git a/llvm/test/Transforms/InstCombine/sign-test-and-or.ll b/llvm/test/Transforms/InstCombine/sign-test-and-or.ll
index 8a70aae216446..c968e76cb7ac9 100644
--- a/llvm/test/Transforms/InstCombine/sign-test-and-or.ll
+++ b/llvm/test/Transforms/InstCombine/sign-test-and-or.ll
@@ -15,6 +15,19 @@ define i1 @test1(i32 %a, i32 %b) {
ret i1 %or.cond
}
+define <2 x i1> @test1_splat(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: @test1_splat(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i32> [[A:%.*]], zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[B:%.*]], zeroinitializer
+; CHECK-NEXT: [[OR_COND:%.*]] = or <2 x i1> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret <2 x i1> [[OR_COND]]
+;
+ %1 = icmp slt <2 x i32> %a, zeroinitializer
+ %2 = icmp slt <2 x i32> %b, zeroinitializer
+ %or.cond = or <2 x i1> %1, %2
+ ret <2 x i1> %or.cond
+}
+
define i1 @test1_logical(i32 %a, i32 %b) {
; CHECK-LABEL: @test1_logical(
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
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