[llvm] fb2539b - [X86][SSE] Add X86ISD::AVG to isCommutativeBinOp to support folding shuffles through the binop

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-10-13T10:54:37+01:00
New Revision: fb2539b9d88a48366859e73a2c9cea9f2cbbee5c

URL: https://github.com/llvm/llvm-project/commit/fb2539b9d88a48366859e73a2c9cea9f2cbbee5c
DIFF: https://github.com/llvm/llvm-project/commit/fb2539b9d88a48366859e73a2c9cea9f2cbbee5c.diff

LOG: [X86][SSE] Add X86ISD::AVG to isCommutativeBinOp to support folding shuffles through the binop

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/avg.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index deda710942a5d..335a51c45903a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -32787,6 +32787,7 @@ bool X86TargetLowering::isBinOp(unsigned Opcode) const {
 bool X86TargetLowering::isCommutativeBinOp(unsigned Opcode) const {
   switch (Opcode) {
   // TODO: Add more X86ISD opcodes once we have test coverage.
+  case X86ISD::AVG:
   case X86ISD::PCMPEQ:
   case X86ISD::PMULDQ:
   case X86ISD::PMULUDQ:

diff  --git a/llvm/test/CodeGen/X86/avg.ll b/llvm/test/CodeGen/X86/avg.ll
index 9841bb5ef9234..457669ec896da 100644
--- a/llvm/test/CodeGen/X86/avg.ll
+++ b/llvm/test/CodeGen/X86/avg.ll
@@ -2593,22 +2593,20 @@ define <2 x i64> @PR41316(<2 x i64>, <2 x i64>) {
   ret <2 x i64> %13
 }
 
-; FIXME: shuffle(avg(shuffle(),shuffle())) -> avg(shuffle(),shuffle())
+; shuffle(avg(shuffle(),shuffle())) -> avg(shuffle(),shuffle())
 define  <16 x i8> @fold_avgb_shuffles(<16 x i8> %x, <16 x i8> %y) {
 ; SSE2-LABEL: fold_avgb_shuffles:
 ; SSE2:       # %bb.0: # %entry
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,3,1,1]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,0,0]
-; SSE2-NEXT:    pavgb %xmm0, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; SSE2-NEXT:    pavgb %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: fold_avgb_shuffles:
 ; AVX:       # %bb.0: # %entry
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,3,1,1]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,2,0,0]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
+; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; AVX-NEXT:    vpavgb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
 ; AVX-NEXT:    retq
 entry:
    %0 = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
@@ -2622,18 +2620,12 @@ declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>)
 define <8 x i16> @fold_avgw_shuffles(<8 x i16> %x, <8 x i16> %y) {
 ; SSE2-LABEL: fold_avgw_shuffles:
 ; SSE2:       # %bb.0: # %entry
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
-; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
-; SSE2-NEXT:    pavgw %xmm0, %xmm1
-; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
+; SSE2-NEXT:    pavgw %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: fold_avgw_shuffles:
 ; AVX:       # %bb.0: # %entry
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
-; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
 ; AVX-NEXT:    vpavgw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
 ; AVX-NEXT:    retq
 entry:
    %0 = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>