[llvm] 357b8d7 - [tests] Add coverage for cases we can drop flags to propagate freeze without cost

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2021-10-12T12:30:46-07:00
New Revision: 357b8d7ddba0b4258063cda132ad03473f28b7e1

URL: https://github.com/llvm/llvm-project/commit/357b8d7ddba0b4258063cda132ad03473f28b7e1
DIFF: https://github.com/llvm/llvm-project/commit/357b8d7ddba0b4258063cda132ad03473f28b7e1.diff

LOG: [tests] Add coverage for cases we can drop flags to propagate freeze without cost

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/freeze.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/freeze.ll b/llvm/test/Transforms/InstCombine/freeze.ll
index ac30036b13ea..bb2f15f33a7c 100644
--- a/llvm/test/Transforms/InstCombine/freeze.ll
+++ b/llvm/test/Transforms/InstCombine/freeze.ll
@@ -119,8 +119,6 @@ define i1 @early_freeze_test2(i32* %ptr) {
   ret i1 %cond.fr
 }
 
-; add can overflows, so we cannot move freeze beyond add
-
 define i32 @early_freeze_test3(i32 %v1) {
 ; CHECK-LABEL: @early_freeze_test3(
 ; CHECK-NEXT:    [[V2:%.*]] = shl i32 [[V1:%.*]], 1
@@ -221,3 +219,127 @@ bb1:
 end:
   ret void
 }
+
+
+define i32 @propagate_drop_flags_add(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_flags_add(
+; CHECK-NEXT:    [[V1:%.*]] = add nuw nsw i32 [[ARG:%.*]], 2
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = add nsw nuw i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_flags_sub(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_flags_sub(
+; CHECK-NEXT:    [[V1:%.*]] = add nsw i32 [[ARG:%.*]], -2
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = sub nsw nuw i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_flags_mul(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_flags_mul(
+; CHECK-NEXT:    [[V1:%.*]] = shl nuw nsw i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = mul nsw nuw i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_flags_udiv(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_flags_udiv(
+; CHECK-NEXT:    [[V1:%.*]] = lshr exact i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = udiv exact i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_flags_sdiv(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_flags_sdiv(
+; CHECK-NEXT:    [[V1:%.*]] = ashr exact i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = sdiv exact i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_shl1(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_shl1(
+; CHECK-NEXT:    [[V1:%.*]] = shl nuw nsw i32 [[ARG:%.*]], 2
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = shl nsw nuw i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_shl2(i32 %arg, i32 %unknown) {
+; CHECK-LABEL: @propagate_drop_shl2(
+; CHECK-NEXT:    [[V1:%.*]] = shl nuw nsw i32 [[ARG:%.*]], [[UNKNOWN:%.*]]
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = shl nsw nuw i32 %arg, %unknown
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_ashr1(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_ashr1(
+; CHECK-NEXT:    [[V1:%.*]] = ashr exact i32 [[ARG:%.*]], 2
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = ashr exact i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_ashr2(i32 %arg, i32 %unknown) {
+; CHECK-LABEL: @propagate_drop_ashr2(
+; CHECK-NEXT:    [[V1:%.*]] = ashr exact i32 [[ARG:%.*]], [[UNKNOWN:%.*]]
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = ashr exact i32 %arg, %unknown
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_lshr1(i32 %arg) {
+; CHECK-LABEL: @propagate_drop_lshr1(
+; CHECK-NEXT:    [[V1:%.*]] = lshr exact i32 [[ARG:%.*]], 2
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = lshr exact i32 %arg, 2
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+define i32 @propagate_drop_lshr2(i32 %arg, i32 %unknown) {
+; CHECK-LABEL: @propagate_drop_lshr2(
+; CHECK-NEXT:    [[V1:%.*]] = lshr exact i32 [[ARG:%.*]], [[UNKNOWN:%.*]]
+; CHECK-NEXT:    [[V1_FR:%.*]] = freeze i32 [[V1]]
+; CHECK-NEXT:    ret i32 [[V1_FR]]
+;
+  %v1 = lshr exact i32 %arg, %unknown
+  %v1.fr = freeze i32 %v1
+  ret i32 %v1.fr
+}
+
+