[PATCH] D99074: [llvm][AArch64][SVE] Fold literals into math instructions

Tue Oct 12 07:31:15 PDT 2021

DavidTruby added a comment.

Hopefully this is going broadly in the direction you wanted @paulwalker-arm I just had a couple of questions about your comments

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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1828-1831
+  def : Pat<(ftype (ir_op (itype (AArch64ptrue 31)),
+                            (ftype ZPR:$Zs1),
+                            (ftype (AArch64dup (sftype A))))),
+            (!cast<Instruction>(IX) (PTRUE_S 31), ZPR:$Zs1, imm)>;
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paulwalker-arm wrote:
> Is this pattern necessary?  I'm thinking that even for the IR ops you can just pass the predicate through and thus we can reuse the first pattern.  Doing this means we'll also take advantage of the immediate forms when lowering VLS operations.
I'm not sure I understand fully; I've managed to reuse this pattern for both the op and ir_op but it definitely seems to still be necessary to have the ir_op version there. I might be wrong about what you meant though?

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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1835
+
+multiclass sve_fp_2op_i_p_zds_zx<string I, Operand imm_ty, FPImmLeaf A, FPImmLeaf B, SDPatternOperator op, SDPatternOperator ir_op = null_frag> {
+  def _UNDEF_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, imm_ty, FalseLanesUndef>;
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paulwalker-arm wrote:
> There's a bit of clash with naming here.  In the past `_zx` implied zeroing where as we now typically attach element types info for the undef case (i.e. `_hfd` in this instance) and then `zeroing_hfd` for the zeroing case.
Hopefully the new names are more what you're expecting? Let me know if not!

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https://reviews.llvm.org/D99074