[PATCH] D111551: [AArch64] Split out processor/tuning features
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 12 07:11:32 PDT 2021
david-arm marked an inline comment as done.
david-arm added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64.td:584
-def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
- "Cortex-A35 ARM processors", [
- FeatureCRC,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureNEON,
- FeaturePerfMon
- ]>;
-
-def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
- "Cortex-A53 ARM processors", [
- FeatureBalanceFPOps,
- FeatureCRC,
- FeatureCrypto,
- FeatureCustomCheapAsMoveHandling,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeaturePerfMon,
- FeaturePostRAScheduler,
- ]>;
-
-def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
- "Cortex-A55 ARM processors", [
- HasV8_2aOps,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeatureFullFP16,
- FeatureDotProd,
- FeatureRCPC,
- FeaturePerfMon,
- FeaturePostRAScheduler,
- FeatureFuseAddress,
- ]>;
-
-def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
- "Cortex-A57 ARM processors", [
- FeatureBalanceFPOps,
- FeatureCRC,
- FeatureCrypto,
- FeatureCustomCheapAsMoveHandling,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureFuseLiterals,
- FeatureNEON,
- FeaturePerfMon,
- FeaturePostRAScheduler,
- FeaturePredictableSelectIsExpensive
- ]>;
-
-def ProcA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
- "Cortex-A65 ARM processors", [
- HasV8_2aOps,
- FeatureCrypto,
- FeatureDotProd,
- FeatureFPARMv8,
- FeatureFullFP16,
- FeatureFuseAddress,
- FeatureFuseAES,
- FeatureFuseLiterals,
- FeatureNEON,
- FeatureRAS,
- FeatureRCPC,
- FeatureSSBS,
- ]>;
-
-def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
- "Cortex-A72 ARM processors", [
- FeatureCRC,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureFuseLiterals,
- FeatureNEON,
- FeaturePerfMon
- ]>;
-
-def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
- "Cortex-A73 ARM processors", [
- FeatureCRC,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeaturePerfMon
- ]>;
-
-def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
- "Cortex-A75 ARM processors", [
- HasV8_2aOps,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeatureFullFP16,
- FeatureDotProd,
- FeatureRCPC,
- FeaturePerfMon
- ]>;
-
-def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
- "Cortex-A76 ARM processors", [
- HasV8_2aOps,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeatureRCPC,
- FeatureCrypto,
- FeatureFullFP16,
- FeatureDotProd,
- FeatureSSBS
- ]>;
-
-def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
- "Cortex-A77 ARM processors", [
- HasV8_2aOps,
- FeatureCmpBccFusion,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON, FeatureRCPC,
- FeatureCrypto,
- FeatureFullFP16,
- FeatureDotProd
- ]>;
-
-def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily",
- "CortexA78",
- "Cortex-A78 ARM processors", [
- HasV8_2aOps,
- FeatureCmpBccFusion,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeatureRCPC,
- FeaturePerfMon,
- FeaturePostRAScheduler,
- FeatureSPE,
- FeatureFullFP16,
- FeatureSSBS,
- FeatureDotProd]>;
-
-def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily",
- "CortexA78C",
- "Cortex-A78C ARM processors", [
- HasV8_2aOps,
- FeatureCmpBccFusion,
- FeatureCrypto,
- FeatureDotProd,
- FeatureFlagM,
- FeatureFP16FML,
- FeatureFPARMv8,
- FeatureFullFP16,
- FeatureFuseAES,
- FeatureNEON,
- FeaturePAuth,
- FeaturePerfMon,
- FeaturePostRAScheduler,
- FeatureRCPC,
- FeatureSPE,
- FeatureSSBS]>;
-
-def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
- "CortexR82",
- "Cortex-R82 ARM Processors", [
- FeaturePostRAScheduler,
- // All other features are implied by v8_0r ops:
- HasV8_0rOps,
- ]>;
-
-def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
- "Cortex-X1 ARM processors", [
- HasV8_2aOps,
- FeatureCmpBccFusion,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeatureRCPC,
- FeaturePerfMon,
- FeaturePostRAScheduler,
- FeatureSPE,
- FeatureFullFP16,
- FeatureDotProd]>;
-
-def ProcA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
- "Fujitsu A64FX processors", [
- HasV8_2aOps,
- FeatureFPARMv8,
- FeatureNEON,
- FeatureSHA2,
- FeaturePerfMon,
- FeatureFullFP16,
- FeatureSVE,
- FeaturePostRAScheduler,
- FeatureComplxNum,
- FeatureAggressiveFMA,
- FeatureArithmeticBccFusion,
- FeaturePredictableSelectIsExpensive
- ]>;
-
-def ProcCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
- "Nvidia Carmel processors", [
- HasV8_2aOps,
- FeatureNEON,
- FeatureCrypto,
- FeatureFullFP16
- ]>;
-
+def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors">;
+def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", [FeatureFuseAES, FeatureBalanceFPOps, FeatureCustomCheapAsMoveHandling, FeaturePostRAScheduler]>;
----------------
c-rhodes wrote:
> Is there any value in defining this if the A35 has no tuning features? Same applies for others like Carmel.
Yeah we have to unfortunately even if it looks silly. That's because a lot of the tuning in AArch64Subtarget.cpp depends upon ARMProcFamily being set to the CPU.
================
Comment at: llvm/lib/Target/AArch64/AArch64.td:585
+def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors">;
+def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", [FeatureFuseAES, FeatureBalanceFPOps, FeatureCustomCheapAsMoveHandling, FeaturePostRAScheduler]>;
+def TuneA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", "Cortex-A55 ARM processors", [FeatureFuseAES, FeaturePostRAScheduler, FeatureFuseAddress]>;
----------------
c-rhodes wrote:
> I think this would easier to review if you kept the existing formatting, difficult to compare these long lines.
I'll try to make it look a bit nicer with some new lines, but it will still be difficult to review because the processor features have been pulled so the lists will be different.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D111551/new/
https://reviews.llvm.org/D111551
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