[PATCH] D111523: [AMDGPU] Don't emit 24 bit mul intrinsic for > 32 bit result.

[Abinav Puthan Purayil via Phabricator via llvm-commits]

abinavpp added a comment.

We only need to make sure that we're conforming to the semantics of the 24 bit
low-order mul instructions in the AMDGPU ISA. I agree with @foad, we shoud do
the following:

if (mul is wider than 32 bits) {

  if (numBits(a) > 24 || numBits(b) > 24)
    return false;
  
  // Check if numBits(mul(a, b)) > 32
  if (numBits(a) + numBits(b) > 32)
    return false;

}

Ideally, we're suppose to split (mul i64 a, b) to (build_pair i64 (mul24hi a,
b), (mul24 a, b)) like how getMul24() of AMDGPUISelLowering.cpp does. I'm not
sure about doing that in LLVM-IR.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D111523/new/

https://reviews.llvm.org/D111523