[PATCH] D111221: [AArch64][SVE] Improve code generation for VLS i1 masks

[David Truby via Phabricator via llvm-commits]

DavidTruby updated this revision to Diff 378986.
DavidTruby added a comment.

Added an extra condition to make the transformation sound.

In essence, we need to check that the predicate is the same
before and after the transform, modulo its size since we're
moving from a smaller to larger predicate.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111221/new/

https://reviews.llvm.org/D111221

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll

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