[PATCH] D111619: [AArch64] Improve shuffle vector by using wider types

[weiwei via Phabricator via llvm-commits]

wwei created this revision.
wwei added reviewers: dmgreen, t.p.northover, efriedma, paulwalker-arm, sdesmalen, david-arm, fhahn.
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Try to widen element type to get a new mask value for a better permutation
sequence, so that we can use NEON shuffle instructions, such as zip1/2,
UZP1/2, TRN1/2, REV, INS, etc.
For example:

  `shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>`

is equivalent to:

  `shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 1>`

Finally, we can get:

  `mov     v0.d[0], v1.d[1]`


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111619

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/concat-vector.ll
  llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll

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