[llvm] 53ebfa7 - [AArch64][GlobalISel] Fix combiner assertion in matchConstantOp().

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-10-11T15:55:13-07:00
New Revision: 53ebfa7c5d1bc121267dbf399b6386b2a3300d19

URL: https://github.com/llvm/llvm-project/commit/53ebfa7c5d1bc121267dbf399b6386b2a3300d19
DIFF: https://github.com/llvm/llvm-project/commit/53ebfa7c5d1bc121267dbf399b6386b2a3300d19.diff

LOG: [AArch64][GlobalISel] Fix combiner assertion in matchConstantOp().

We shouldn't call APInt::getSExtValue() on a >64b value.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 2b8ff6afac568..a3b2cc4dcd989 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2370,7 +2370,8 @@ bool CombinerHelper::matchConstantOp(const MachineOperand &MOP, int64_t C) {
     return false;
   auto *MI = MRI.getVRegDef(MOP.getReg());
   auto MaybeCst = isConstantOrConstantSplatVector(*MI, MRI);
-  return MaybeCst.hasValue() && MaybeCst->getSExtValue() == C;
+  return MaybeCst.hasValue() && MaybeCst->getBitWidth() <= 64 &&
+         MaybeCst->getSExtValue() == C;
 }
 
 bool CombinerHelper::replaceSingleDefInstWithOperand(MachineInstr &MI,

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
index 7bd325b2a5e62..0681a3f33a603 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
@@ -410,3 +410,26 @@ body:             |
     $q0 = COPY %ptr(<2 x p0>)
     RET_ReallyLR implicit $q0
 ...
+---
+name:            i128_or_cst
+liveins:
+  - { reg: '$x0' }
+body:             |
+  bb.1:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: i128_or_cst
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128))
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 9223372036854775808
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s128) = G_OR [[LOAD]], [[C]]
+    ; CHECK-NEXT: G_STORE [[OR]](s128), [[COPY]](p0) :: (store (s128), align 4)
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:_(p0) = COPY $x0
+    %2:_(s128) = G_LOAD %0(p0) :: (load (s128))
+    %4:_(s128) = G_CONSTANT i128 9223372036854775808
+    %5:_(s128) = G_OR %2, %4
+    G_STORE %5(s128), %0(p0) :: (store (s128), align 4)
+    RET_ReallyLR
+
+...