[PATCH] D110855: [PowerPC] Implement scheduling model for Power10

[Jinsong Ji via Phabricator via llvm-commits]

jsji accepted this revision as: jsji.
jsji added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!



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Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:109
 ; CHECK-BE-NEXT:    sldi r3, r5, 1
+; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, r6, r3
----------------
Minor issue, but this looks like slightly worse than before?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110855/new/

https://reviews.llvm.org/D110855